From 46402cbe0ba3ea92be9642cf18eedaefe57a414c Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Tue, 6 Mar 2012 17:15:43 +0000 Subject: [PATCH] re PR target/50310 (ICE: in gen_vcondv2div2df, at config/i386/sse.md:1435 with -O -ftree-vectorize and __builtin_isunordered()) 2012-03-05 Michael Meissner PR target/50310 * config/rs6000/vector.md (vector_uneq): Add support for UNEQ, LTGT, ORDERED, and UNORDERED IEEE vector comparisons. (vector_ltgt): Likewise. (vector_ordered): Likewise. (vector_unordered): Likewise. * config/rs6000/rs6000.c (rs6000_emit_vector_compare_inner): Likewise. From-SVN: r185007 --- gcc/ChangeLog | 11 +++++ gcc/config/rs6000/rs6000.c | 4 ++ gcc/config/rs6000/vector.md | 88 +++++++++++++++++++++++++++++++++++++ 3 files changed, 103 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e3bba82e6bd7..6f5d9cbfd5d8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2012-03-06 Michael Meissner + + PR target/50310 + * config/rs6000/vector.md (vector_uneq): Add support for + UNEQ, LTGT, ORDERED, and UNORDERED IEEE vector comparisons. + (vector_ltgt): Likewise. + (vector_ordered): Likewise. + (vector_unordered): Likewise. + * config/rs6000/rs6000.c (rs6000_emit_vector_compare_inner): + Likewise. + 2012-03-06 Aldy Hernandez * trans-mem.c: New typedef for tm_region_p. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 04ea22b70dd1..5558f7769f57 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -16077,6 +16077,10 @@ rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1) case EQ: case GT: case GTU: + case ORDERED: + case UNORDERED: + case UNEQ: + case LTGT: mask = gen_reg_rtx (mode); emit_insn (gen_rtx_SET (VOIDmode, mask, diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index bcb23ac5de60..6674054223b4 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -516,6 +516,94 @@ "VECTOR_UNIT_ALTIVEC_P (mode)" "") +(define_insn_and_split "*vector_uneq" + [(set (match_operand:VEC_F 0 "vfloat_operand" "") + (uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") + (match_operand:VEC_F 2 "vfloat_operand" "")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + "#" + "" + [(set (match_dup 3) + (gt:VEC_F (match_dup 1) + (match_dup 2))) + (set (match_dup 4) + (gt:VEC_F (match_dup 2) + (match_dup 1))) + (set (match_dup 0) + (not:VEC_F (ior:VEC_F (match_dup 3) + (match_dup 4))))] + " +{ + operands[3] = gen_reg_rtx (mode); + operands[4] = gen_reg_rtx (mode); +}") + +(define_insn_and_split "*vector_ltgt" + [(set (match_operand:VEC_F 0 "vfloat_operand" "") + (ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") + (match_operand:VEC_F 2 "vfloat_operand" "")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + "#" + "" + [(set (match_dup 3) + (gt:VEC_F (match_dup 1) + (match_dup 2))) + (set (match_dup 4) + (gt:VEC_F (match_dup 2) + (match_dup 1))) + (set (match_dup 0) + (ior:VEC_F (match_dup 3) + (match_dup 4)))] + " +{ + operands[3] = gen_reg_rtx (mode); + operands[4] = gen_reg_rtx (mode); +}") + +(define_insn_and_split "*vector_ordered" + [(set (match_operand:VEC_F 0 "vfloat_operand" "") + (ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") + (match_operand:VEC_F 2 "vfloat_operand" "")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + "#" + "" + [(set (match_dup 3) + (ge:VEC_F (match_dup 1) + (match_dup 2))) + (set (match_dup 4) + (ge:VEC_F (match_dup 2) + (match_dup 1))) + (set (match_dup 0) + (ior:VEC_F (match_dup 3) + (match_dup 4)))] + " +{ + operands[3] = gen_reg_rtx (mode); + operands[4] = gen_reg_rtx (mode); +}") + +(define_insn_and_split "*vector_unordered" + [(set (match_operand:VEC_F 0 "vfloat_operand" "") + (unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") + (match_operand:VEC_F 2 "vfloat_operand" "")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + "#" + "" + [(set (match_dup 3) + (ge:VEC_F (match_dup 1) + (match_dup 2))) + (set (match_dup 4) + (ge:VEC_F (match_dup 2) + (match_dup 1))) + (set (match_dup 0) + (not:VEC_F (ior:VEC_F (match_dup 3) + (match_dup 4))))] + " +{ + operands[3] = gen_reg_rtx (mode); + operands[4] = gen_reg_rtx (mode); +}") + ;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask ;; which is in the reverse order that we want (define_expand "vector_select_" -- 2.43.5