Pat Bernardi [Mon, 24 Aug 2020 14:29:32 +0000 (10:29 -0400)]
Sync the aarch64-vx7r2 libgcc config with that of Linux
This adds ${cpu_type}/t-lse and t-slibgcc-libgcc to the tmake_file
list for aarch64-vxworks7* configurations, as the Linux port does.
t-lse is needed by all triplets now anyway and the standard setting
for slibgcc makes sense as we are working on reintroducing PIC support
for RTPs on various targets. The VxWorks7 system environments are leaning
towards more and more similarilties with Linux in general, so the
closer configurations the better.
2020-11-02 Pat Bernardi <bernardi@adacore.com>
libgcc/
* config.host (aarch64-vxworks7*, tmake_file): Add
${cpu_type}/t-lse and t-slibgcc-libgcc.
Dennis Zhang [Tue, 3 Nov 2020 16:56:02 +0000 (16:56 +0000)]
aarch64: intrinsics extract half of bf16 vector
This patch implements ACLE intrinsics vget_low_bf16 and vget_high_bf16
to extract lower or higher half from a bfloat16x8 vector. The
vget_high_bf16 is done by 'dup' instruction. The vget_low_bf16 is just
to return the lower half of a vector register. Tests include both big-
and little-endian cases.
gcc/ChangeLog:
2020-11-03 Dennis Zhang <dennis.zhang@arm.com>
* config/aarch64/aarch64-simd-builtins.def (vget_lo_half): New entry.
(vget_hi_half): Likewise.
* config/aarch64/aarch64-simd.md (aarch64_vget_lo_halfv8bf): New entry.
(aarch64_vget_hi_halfv8bf): Likewise.
* config/aarch64/arm_neon.h (vget_low_bf16): New intrinsic.
(vget_high_bf16): Likewise.
gcc/testsuite/ChangeLog
* gcc.target/aarch64/advsimd-intrinsics/bf16_get.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/bf16_get-be.c: New test.
Nathan Sidwell [Tue, 3 Nov 2020 16:45:15 +0000 (08:45 -0800)]
c++: Directly fixup deferred eh-specs
eh-specifiers in a class definition are complete-definition contexts,
and we sometimes need to deferr their parsing. We create a deferred
eh specifier, which can end up persisting in the type system due to
variants being created before the deferred parse. This causes
problems in modules handling.
This patch adds fixup_deferred_exception_variants, which directly
modifies the variants of such an eh spec once parsed. As commented,
the general case is quite hard, so it doesn't deal with everything.
But I do catch the cases I encountered (from the std library).
gcc/cp/
* cp-tree.h (fixup_deferred_exception_variants): Declare.
* parser.c (cp_parser_class_specifier_1): Call it when
completing deferred parses rather than creating a variant.
(cp_parser_member_declaration): Move comment from ...
(cp_parser_noexcept_specification_opt): ... here. Refactor the
deferred parse.
* tree.c (fixup_deferred_exception_variants): New.
Nathan Sidwell [Tue, 3 Nov 2020 16:39:47 +0000 (08:39 -0800)]
c++: A couple of template instantiation cleanups
I noticed that we were handling lambda extra scope during template
instantiation in a different order to how we handle the non-template
case. Reordered that for consistency. Also some more RAII during
template instantiation.
gcc/cp/
* pt.c (tsubst_lambda_expr): Reorder extra-scope handling to match
the non-template case.
(instantiate_body): Move a couple of declarations to their
initializers.
Nathan Sidwell [Tue, 3 Nov 2020 16:35:53 +0000 (08:35 -0800)]
c++: Make extern-C mismatch an error
duplicate_decls was being lenient about extern-c mismatches, allowing
you to have two declarations in the symbol table after emitting an
error. This resulted in duplicate error messages in modules, when we
find the same problem multiple times. Let's just not let that happen.
Nathan Sidwell [Tue, 3 Nov 2020 16:32:42 +0000 (08:32 -0800)]
cpplib: Fix off-by-one error
I noticed a fencepost error in the preprocessor. We should be
checking if the next char is at the limit, not the current char (which
can't be, because we're looking at it).
libcpp/
* lex.c (_cpp_clean_line): Fix DOS off-by-one error.
Yang Yang [Tue, 3 Nov 2020 16:13:47 +0000 (16:13 +0000)]
PR target/96342 Change field "simdlen" into poly_uint64
This is the first patch of PR96342. In order to add support for
"omp declare simd", change the type of the field "simdlen" of
struct cgraph_simd_clone from unsigned int to poly_uint64 and
related adaptation. Since the length might be variable for the
SVE cases.
2020-11-03 Yang Yang <yangyang305@huawei.com>
gcc/ChangeLog:
* cgraph.h (struct cgraph_simd_clone): Change field "simdlen" of
struct cgraph_simd_clone from unsigned int to poly_uint64.
* config/aarch64/aarch64.c
(aarch64_simd_clone_compute_vecsize_and_simdlen): adaptation of
operations on "simdlen".
* config/i386/i386.c (ix86_simd_clone_compute_vecsize_and_simdlen):
Printf formats update.
* gengtype.c (main): Handle poly_uint64.
* omp-simd-clone.c (simd_clone_mangle): Likewise.Re
(simd_clone_adjust_return_type): Likewise.
(create_tmp_simd_array): Likewise.
(simd_clone_adjust_argument_types): Likewise.
(simd_clone_init_simd_arrays): Likewise.
(ipa_simd_modify_function_body): Likewise.
(simd_clone_adjust): Likewise.
(expand_simd_clones): Likewise.
* poly-int-types.h (vector_unroll_factor): New macro.
* poly-int.h (constant_multiple_p): Add two-argument versions.
* tree-vect-stmts.c (vectorizable_simd_clone_call): Likewise.
Richard Biener [Tue, 3 Nov 2020 14:03:41 +0000 (15:03 +0100)]
tree-optimization/97623 - limit PRE hoist insertion
This limits insert iteration caused by PRE insertions generating
hoist insertion opportunities and vice versa. The patch limits
the hoist insertion iterations to three by default.
2020-11-03 Richard Biener <rguenther@suse.de>
PR tree-optimization/97623
* params.opt (-param=max-pre-hoist-insert-iterations): New.
* doc/invoke.texi (max-pre-hoist-insert-iterations): Document.
* tree-ssa-pre.c (insert): Do at most max-pre-hoist-insert-iterations
hoist insert iterations.
Andrew MacLeod [Mon, 2 Nov 2020 22:04:23 +0000 (17:04 -0500)]
More Ranger cache tweaks
This patch splits the individual value propagation out from fill_block_cache,
and calls it from set_global_value when the global value is updated.
This ensures the "current" global value is reflected in the on-entry cache.
* gimple-range-cache.cc (ssa_global_cache::get_global_range): Return
true if there was a previous range set.
(ranger_cache::ranger_cache): Take a gimple_ranger parameter.
(ranger_cache::set_global_range): Propagate the value if updating.
(ranger_cache::propagate_cache): Renamed from iterative_cache_update.
(ranger_cache::propagate_updated_value): New. Split from:
(ranger_cache::fill_block_cache): Split out value propagator.
* gimple-range-cache.h (ssa_global_cache): Update prototypes.
(ranger_cache): Update prototypes.
Marek Polacek [Thu, 29 Oct 2020 19:19:51 +0000 (15:19 -0400)]
c++: Tweaks for value_dependent_expression_p.
We may not call value_dependent_expression_p on expressions that are
not potential constant expressions, otherwise value_d could crash,
as I saw recently (in C++98). So beef up the checking in i_d_e_p.
This revealed a curious issue: when we have __PRETTY_FUNCTION__ in
a template function, we set its DECL_VALUE_EXPR to error_mark_node
(cp_make_fname_decl), so potential_c_e returns false when it gets it,
but value_dependent_expression_p handles it specially and says true.
This broke lambda-generic-pretty1.C. So take care of that.
And then also tweak uses_template_parms.
gcc/cp/ChangeLog:
* constexpr.c (potential_constant_expression_1): Treat
__PRETTY_FUNCTION__ inside a template function as
potentially-constant.
* pt.c (uses_template_parms): Call
instantiation_dependent_expression_p instead of
value_dependent_expression_p.
(instantiation_dependent_expression_p): Check
potential_constant_expression before calling
value_dependent_expression_p.
PR target/97205
* cfgexpand.c (align_local_variable): Make SSA_NAMEs
at least MODE_ALIGNED.
(expand_one_stack_var_at): Increase MEM_ALIGN for SSA_NAMEs.
Richard Biener [Tue, 3 Nov 2020 11:28:03 +0000 (12:28 +0100)]
Save some memory at debug stream-in time
This allows us to release references to BLOCKs by not keeping
them rooted in the external_die_map but instead remove it from
there as soon as we created the corresponding stub DIE. For
decls it doesn't help since we still keep the decl_die_table.
2020-10-29 Andrea Corallo <andrea.corallo@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_bf16_indices_1.c:
Run it also for the arm backend.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_bf16_indices_1.c:
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_bf16_indices_1.c:
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_bf16_indices_1.c:
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_bf16_indices_1.c:
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_bf16_indices_1.c:
Likewise.
* gcc.target/arm/simd/vldn_lane_bf16_1.c: New test.
Nathan Sidwell [Tue, 3 Nov 2020 13:11:42 +0000 (05:11 -0800)]
c++: cp_tree_equal cleanups
A couple of small fixes. I noticed bind_template_template_parms was
not marking the parm a template parm (this broke some module
handling). Debugging CALL_EXPR comparisons led me to refactor
cp_tree_equal's CALL_EXPR code (and my recent fix to debug printing of
same). Finally TREE_VECS are best compared by comp_template_args. I
recall that last piece being a left over from fixes during gcc-10.
I've been using it on the modules branch since then.
gcc/cp/
* tree.c (bind_template_template_parm): Mark the parm as a
template parm.
(cp_tree_equal): Refactor CALL_EXPR. Use comp_template_args for
TREE_VECs.
Nathan Sidwell [Tue, 3 Nov 2020 13:08:18 +0000 (05:08 -0800)]
c++: rtti cleanups
Here are a few cleanups from the modules branch. Generally some RAII,
and a bit of lazy namespace pushing.
gcc/cp/
* rtti.c (init_rtti_processing): Move var decl to its init.
(get_tinfo_decl): Likewise. Break out creation to called helper
...
(get_tinfo_decl_direct): ... here.
(build_dynamic_cast_1): Move var decls to their initializers.
(tinfo_base_init): Set decl's location to BUILTINS_LOCATION.
(get_tinfo_desc): Only push ABI namespace when needed. Set type's
context.
Nathan Sidwell [Tue, 3 Nov 2020 12:59:48 +0000 (04:59 -0800)]
libcpp: dependency emission tidying
This patch cleans up the interface to the dependency generation a
little. We now only check the option in one place, and the
cpp_get_deps function returns nullptr if there are no dependencies. I
also reworded the -MT and -MQ help text to be make agnostic -- as
there are ideas about emitting, say, JSON.
libcpp/
* include/mkdeps.h: Include cpplib.h
(deps_write): Adjust first parm type.
* mkdeps.c: Include internal.h
(make_write): Adjust first parm type. Check phony option
directly.
(deps_write): Adjust first parm type.
* init.c (cpp_read_main_file): Use get_deps.
* directives.c (cpp_get_deps): Check option before initializing.
gcc/c-family/
* c.opt (MQ,MT): Reword description to be make-agnostic.
gcc/fortran/
* cpp.c (gfc_cpp_add_dep): Only add dependency if we're recording
them.
(gfc_cpp_init): Likewise for target.
Dennis Zhang [Tue, 3 Nov 2020 13:00:51 +0000 (13:00 +0000)]
aarch64: ACLE intrinsics convert BF16 to Float32
This patch enables intrinsics to convert BFloat16 scalar and vector
operands to Float32 modes. The intrinsics are implemented by shifting
each BFloat16 item 16 bits to left using shl/shll/shll2 instructions.
gcc/ChangeLog:
2020-11-03 Dennis Zhang <dennis.zhang@arm.com>
* config/aarch64/aarch64-simd-builtins.def(vbfcvt): New entry.
(vbfcvt_high, bfcvt): Likewise.
* config/aarch64/aarch64-simd.md(aarch64_vbfcvt<mode>): New entry.
(aarch64_vbfcvt_highv8bf, aarch64_bfcvtsf): Likewise.
* config/aarch64/arm_bf16.h (vcvtah_f32_bf16): New intrinsic.
* config/aarch64/arm_neon.h (vcvt_f32_bf16): Likewise.
(vcvtq_low_f32_bf16, vcvtq_high_f32_bf16): Likewise.
gcc/testsuite/ChangeLog
* gcc.target/aarch64/advsimd-intrinsics/bfcvt-compile.c
(test_vcvt_f32_bf16, test_vcvtq_low_f32_bf16): New tests.
(test_vcvtq_high_f32_bf16, test_vcvth_f32_bf16): Likewise.
Olivier Hainque [Tue, 3 Nov 2020 09:51:43 +0000 (09:51 +0000)]
Add dg-require-effective-target fpic to gcc i386 tests
This change adds
/* { dg-require-effective-target fpic } */
to tests in gcc.target/i386 that do use -fpic or -fPIC
but don't currently query the target support.
This corresponds to what many other fpic tests do
and helps the vxWorks ports at least, as -fpic is
typically not supported in at least one of the two
major modes of such port (kernel vs RTP).
Richard Biener [Tue, 3 Nov 2020 09:24:02 +0000 (10:24 +0100)]
testsuite/97688 - fix check_vect () with __AVX2__
This fixes the cpuid check to always specify a subleaf zero
which is required to detect AVX2 and doesn't hurt for level one.
Without this fix we get zero runtime coverage when -mavx2 is
specified.
2020-11-03 Richard Biener <rguenther@suse.de>
PR testsuite/97688
* gcc.dg/vect/tree-vect.h (check_vect): Fix the x86 cpuid
check to always specify subleaf zero.
This restores not tracking SLP nodes for induction initial values
in not nested context because this interferes with peeling and
epilogue vectorization.
2020-11-03 Richard Biener <rguenther@suse.de>
PR tree-optimization/97678
* tree-vect-slp.c (vect_build_slp_tree_2): Do not track
the initial values of inductions when not nested.
* tree-vect-loop.c (vectorizable_induction): Look at
PHI node initial values again for SLP and not nested
inductions. Handle LOOP_VINFO_MASK_SKIP_NITERS and cost
invariants.
Thomas Schwinge [Tue, 27 Oct 2020 16:13:16 +0000 (17:13 +0100)]
[OpenACC] More precise diagnostics for 'gang', 'worker', 'vector' clauses with arguments on 'loop' only allowed in 'kernels' regions
Instead of at the location of the 'loop' directive, 'error_at' the location of
the improper clause, and 'inform' at the location of the enclosing parent
compute construct/routine.
The Fortran testcases come with some XFAILing, to be resolved later.
gcc/
* omp-low.c (scan_omp_for) <OpenACC>: More precise diagnostics for
'gang', 'worker', 'vector' clauses with arguments only allowed in
'kernels' regions.
gcc/testsuite/
* c-c++-common/goacc/pr92793-1.c: Extend.
* gfortran.dg/goacc/pr92793-1.f90: Likewise.
Kewen Lin [Tue, 3 Nov 2020 02:51:47 +0000 (02:51 +0000)]
pass: Run cleanup passes before SLP [PR96789]
As the discussion in PR96789, we found that some scalar stmts
which can be eliminated by some passes after SLP, but we still
modeled their costs when trying to SLP, it could impact
vectorizer's decision. One typical case is the case in PR96789
on target Power.
As Richard suggested there, this patch is to introduce one pass
called pre_slp_scalar_cleanup which has some secondary clean up
passes, for now they are FRE and DSE. It introduces one new
TODO flags group called pending TODO flags, unlike normal TODO
flags, the pending TODO flags are passed down in the pipeline
until one of its consumers can perform the requested action.
Consumers should then clear the flags for the actions that they
have taken.
Soem compilation time statistics on all SPEC2017 INT bmks were
collected on one Power9 machine for several option sets below:
A1: -Ofast -funroll-loops
A2: -O1
A3: -O1 -funroll-loops
A4: -O2
A5: -O2 -funroll-loops
the corresponding increment rate is trivial:
A1 A2 A3 A4 A5
0.08% 0.00% -0.38% -0.10% -0.05%
Bootstrapped/regtested on powerpc64le-linux-gnu P8.
gcc/ChangeLog:
PR tree-optimization/96789
* function.h (struct function): New member unsigned pending_TODOs.
* passes.c (class pass_pre_slp_scalar_cleanup): New class.
(make_pass_pre_slp_scalar_cleanup): New function.
(pass_data_pre_slp_scalar_cleanup): New pass data.
* passes.def: (pass_pre_slp_scalar_cleanup): New pass, add
pass_fre and pass_dse as its children.
* timevar.def (TV_SCALAR_CLEANUP): New timevar.
* tree-pass.h (PENDING_TODO_force_next_scalar_cleanup): New
pending TODO flag.
(make_pass_pre_slp_scalar_cleanup): New declare.
* tree-ssa-loop-ivcanon.c (tree_unroll_loops_completely_1):
Once any outermost loop gets unrolled, flag cfun pending_TODOs
PENDING_TODO_force_next_scalar_cleanup on.
Martin Storsjö [Tue, 8 Sep 2020 12:21:51 +0000 (15:21 +0300)]
libgcc: Expose the instruction pointer and stack pointer in SEH _Unwind_Backtrace
Previously, the SEH version of _Unwind_Backtrace did unwind
the stack and call the provided callback function as intended,
but there was little the caller could do within the callback to
actually get any info about that particular level in the unwind.
Set the ra and cfa pointers, which are used by _Unwind_GetIP
and _Unwind_GetCFA, to allow using these functions from the
callacb to inspect the state at each stack frame.
2020-09-08 Martin Storsjö <martin@martin.st>
libgcc/
* unwind-seh.c (_Unwind_Backtrace): Set the ra and cfa pointers
before calling the callback.
This moves an #ifdef block of code from calls.c to
targetm.function_ok_for_sibcall. Only two targets, x86 and rs6000,
define REG_PARM_STACK_SPACE or OUTGOING_REG_PARM_STACK_SPACE macros
that might vary depending on the called function. Macros like
UNITS_PER_WORD don't change over a function boundary, nor does the
MIPS ABI, nor does TARGET_64BIT on PA-RISC. Other targets are even
more trivially proven to not need the calls.c code.
Besides cleaning up a small piece of #ifdef code, the motivation for
this patch is to allow tail calls on PowerPC for functions that
require less reg_parm_stack_space than their caller. The original
code in calls.c only permitted tail calls when exactly equal, but on
PowerPC we can tail call if the callee has less or equal
REG_PARM_STACK_SPACE than the caller, as demonstrated by the
testcase. So we should use
/* If reg parm stack space increases, we cannot sibcall. */
if (REG_PARM_STACK_SPACE (decl ? decl : fntype)
> INCOMING_REG_PARM_STACK_SPACE (current_function_decl))
and note the change to use INCOMING_REG_PARM_STACK_SPACE.
REG_PARM_STACK_SPACE has always been wrong there for PowerPC. See
https://gcc.gnu.org/pipermail/gcc-patches/2014-May/389867.html for why
if you're curious. Not that it matters, because PowerPC can do
without this check entirely, relying on a stack slot test in generic
code.
a) The generic code checks that arg passing stack in the callee is not
greater than that in the caller, and,
b) ELFv2 only allocates reg_parm_stack_space when some parameter is
passed on the stack.
Point (b) means that zero reg_parm_stack_space implies zero stack
space, and non-zero reg_parm_stack_space implies non-zero stack
space. So the case of 0 reg_parm_stack_space in the caller and 64 in
the callee will be caught by (a).
* ira.c (ira_remove_scratches): Rename to remove_scratches. Make
it static and returning flag of any change.
(ira.c): Call ira_expand_reg_equiv in case of removing scratches.
H.J. Lu [Mon, 21 Sep 2020 12:33:46 +0000 (05:33 -0700)]
x86: Also require MMX for __builtin_ia32_maskmovq
MMX emulation with SEE is implemented at MMX intrinsic level, not at MMX
instruction level. _mm_maskmove_si64 intrinsic for "MASKMOVQ mm1, mm2"
is emulated with __builtin_ia32_maskmovdqu. Since SSE "MASKMOVQ mm1, mm2"
builtin function, __builtin_ia32_maskmovq, can't be emulated with XMM
registers, make __builtin_ia32_maskmovq also require MMX instead of SSE
only.
gcc/
PR target/97140
* config/i386/i386-expand.c (ix86_expand_builtin): Require MMX
for __builtin_ia32_maskmovq.
gcc/testsuite/
PR target/97140
* gcc.target/i386/pr97140.c: New test.
Patrick Palka [Mon, 2 Nov 2020 18:19:29 +0000 (13:19 -0500)]
c++: Don't purge the satisfaction caches
The adoption of P2104 ("Disallow changing concept values") means we can
memoize the result of satisfaction indefinitely and no longer have to
clear the satisfaction caches on various events that would affect
satisfaction. To that end, this patch removes the invalidation routine
clear_satisfaction_cache and adjusts its callers appropriately.
This provides a large reduction in compile time and memory use in some
cases. For example, on the libstdc++ test std/ranges/adaptor/join.cc,
compile time and memory usage drops nearly 75%, from 7.5s/770MB to
2s/230MB, with a --enable-checking=release compiler.
Carl Love [Mon, 31 Aug 2020 21:12:31 +0000 (16:12 -0500)]
Add bcd builtings listed in appendix B of the ABI
2020-10-29 Carl Love <cel@us.ibm.com>
gcc/
PR target/93449
* config/rs6000/altivec.h (__builtin_bcdadd, __builtin_bcdadd_lt,
__builtin_bcdadd_eq, __builtin_bcdadd_gt, __builtin_bcdadd_ofl,
__builtin_bcdadd_ov, __builtin_bcdsub, __builtin_bcdsub_lt,
__builtin_bcdsub_eq, __builtin_bcdsub_gt, __builtin_bcdsub_ofl,
__builtin_bcdsub_ov, __builtin_bcdinvalid, __builtin_bcdmul10,
__builtin_bcddiv10, __builtin_bcd2dfp, __builtin_bcdcmpeq,
__builtin_bcdcmpgt, __builtin_bcdcmplt, __builtin_bcdcmpge,
__builtin_bcdcmple): Add defines.
* config/rs6000/altivec.md: Add UNSPEC_BCDSHIFT.
(BCD_TEST): Add le, ge to code iterator.
Add VBCD mode iterator.
(bcd<bcd_add_sub>_test, *bcd<bcd_add_sub>_test2,
bcd<bcd_add_sub>_<code>, bcd<bcd_add_sub>_<code>): Add mode to name.
Change iterator from V1TI to VBCD.
(*bcdinvalid_<mode>, bcdshift_v16qi): New define_insn.
(bcdinvalid_<mode>, bcdmul10_v16qi, bcddiv10_v16qi): New define.
* config/rs6000/dfp.md (dfp_denbcd_v16qi_inst): New define_insn.
(dfp_denbcd_v16qi): New define_expand.
* config/rs6000/rs6000-builtin.def (BU_P8V_MISC_1): New define.
(BCDADD): Replaced with BCDADD_V1TI and BCDADD_V16QI.
(BCDADD_LT): Replaced with BCDADD_LT_V1TI and BCDADD_LT_V16QI.
(BCDADD_EQ): Replaced with BCDADD_EQ_V1TI and BCDADD_EQ_V16QI.
(BCDADD_GT): Replaced with BCDADD_GT_V1TI and BCDADD_GT_V16QI.
(BCDADD_OV): Replaced with BCDADD_OV_V1TI and BCDADD_OV_V16QI.
(BCDSUB_V1TI, BCDSUB_V16QI, BCDSUB_LT_V1TI, BCDSUB_LT_V16QI,
BCDSUB_LE_V1TI, BCDSUB_LE_V16QI, BCDSUB_EQ_V1TI, BCDSUB_EQ_V16QI,
BCDSUB_GT_V1TI, BCDSUB_GT_V16QI, BCDSUB_GE_V1TI, BCDSUB_GE_V16QI,
BCDSUB_OV_V1TI, BCDSUB_OV_V16QI, BCDINVALID_V1TI, BCDINVALID_V16QI,
BCDMUL10_V16QI, BCDDIV10_V16QI, DENBCD_V16QI): New builtin definitions.
(BCDADD, BCDADD_LT, BCDADD_EQ, BCDADD_GT, BCDADD_OV, BCDSUB, BCDSUB_LT,
BCDSUB_LE, BCDSUB_EQ, BCDSUB_GT, BCDSUB_GE, BCDSUB_OV, BCDINVALID,
BCDMUL10, BCDDIV10, DENBCD): New overload definitions.
* config/rs6000/rs6000-call.c (P8V_BUILTIN_VEC_BCDADD, P8V_BUILTIN_VEC_BCDADD_LT,
P8V_BUILTIN_VEC_BCDADD_EQ, P8V_BUILTIN_VEC_BCDADD_GT, P8V_BUILTIN_VEC_BCDADD_OV,
P8V_BUILTIN_VEC_BCDINVALID, P9V_BUILTIN_VEC_BCDMUL10, P8V_BUILTIN_VEC_DENBCD.
P8V_BUILTIN_VEC_BCDSUB, P8V_BUILTIN_VEC_BCDSUB_LT, P8V_BUILTIN_VEC_BCDSUB_LE,
P8V_BUILTIN_VEC_BCDSUB_EQ, P8V_BUILTIN_VEC_BCDSUB_GT, P8V_BUILTIN_VEC_BCDSUB_GE,
P8V_BUILTIN_VEC_BCDSUB_OV): New overloaded specifications.
(CODE_FOR_bcdadd): Replaced with CODE_FOR_bcdadd_v16qi and CODE_FOR_bcdadd_v1ti.
(CODE_FOR_bcdadd_lt): Replaced with CODE_FOR_bcdadd_lt_v16qi and CODE_FOR_bcdadd_lt_v1ti.
(CODE_FOR_bcdadd_eq): Replaced with CODE_FOR_bcdadd_eq_v16qi and CODE_FOR_bcdadd_eq_v1ti.
(CODE_FOR_bcdadd_gt): Replaced with CODE_FOR_bcdadd_gt_v16qi and CODE_FOR_bcdadd_gt_v1ti.
(CODE_FOR_bcdsub): Replaced with CODE_FOR_bcdsub_v16qi and CODE_FOR_bcdsub_v1ti.
(CODE_FOR_bcdsub_lt): Replaced with CODE_FOR_bcdsub_lt_v16qi and CODE_FOR_bcdsub_lt_v1ti.
(CODE_FOR_bcdsub_eq): Replaced with CODE_FOR_bcdsub_eq_v16qi and CODE_FOR_bcdsub_eq_v1ti.
(CODE_FOR_bcdsub_gt): Replaced with CODE_FOR_bcdsub_gt_v16qi and CODE_FOR_bcdsub_gt_v1ti.
(rs6000_expand_ternop_builtin): Add CODE_FOR_dfp_denbcd_v16qi to else if.
* doc/extend.texi: Add documentation for new builtins.
gcc/testsuite/
* gcc.target/powerpc/bcd-2.c: Add include altivec.h.
* gcc.target/powerpc/bcd-3.c: Add include altivec.h.
* gcc.target/powerpc/bcd-4.c: New test.
I fell over an ICE where wide_int_to_type_1's expectations of pointer
value caching didn't match that of cache_integer_cst's behaviour. I
don't know why it only exhibited on the modules branch, but it seems
pretty wrong. This patch matches up the behaviours and adds a comment
about that.
gcc/
* tree.c (cache_integer_cst): Fixup pointer caching to match
wide_int_to_type_1's expectations. Add comment.
Nathan Sidwell [Mon, 2 Nov 2020 16:38:30 +0000 (08:38 -0800)]
core: debug-print whole call expr
In debugging some call-expr handling, I got confused because the debug
printer elided NULL call operands. This changes the printer to display
them as NULL.
gcc/
* print-tree.c (print_node): Display all the operands of a call
expr.
Nathan Sidwell [Mon, 2 Nov 2020 16:29:58 +0000 (08:29 -0800)]
cpplib: Macro use location and comparison
Our macro use hook passes a location, but doesn't recieve it from the
using location. This patch adds the extra location_t parameter and
passes it though.
A second cleanup is breaking out the macro comparison code from the
redefinition warning. That;ll turn out useful for modules.
Finally, there's a filename comparison needed for the location
optimization of rewinding from line 2 (occurs during the emission of
builtin macros).
libcpp/
* internal.h (_cpp_notify_macro_use): Add location parm.
(_cpp_maybe_notify_macro_use): Likewise.
* directives.c (_cpp_do_file_change): Check we've not changed file
when optimizing a rewind.
(do_ifdef): Pass location to _cpp_maybe_notify_macro_use.
(do_ifndef): Likewise. Delete obsolete comment about powerpc.
* expr.c (parse_defined): Pass location to
_cpp_maybe_notify_macro_use.
* macro.c (enter_macro_context): Likewise.
(warn_of_redefinition): Break out helper function. Call it.
(compare_macros): New function broken out of warn_of_redefinition.
(_cpp_new_macro): Zero all fields.
(_cpp_notify_macro_use): Add location parameter.
Sudakshina Das [Mon, 2 Nov 2020 15:52:22 +0000 (15:52 +0000)]
[PATCH] aarch64: Fix PR97638
Currently the testcase in the patch was failing to produce
a 'bti c' at the beginning of the function. This was because
in aarch64_pac_insn_p, we were wrongly returning at the first
check!
2020-10-30 Sudakshina Das <sudi.das@arm.com>
gcc/ChangeLog:
PR target/97638
* config/aarch64/aarch64-bti-insert.c (aarch64_pac_insn_p): Update
return value on INSN_P check.
gcc/testsuite/ChangeLog:
PR target/97638
* gcc.target/aarch64/pr97638.c: New test.a
Richard Biener [Mon, 2 Nov 2020 11:38:04 +0000 (12:38 +0100)]
Rewrite SLP induction vectorization
This rewrites SLP induction vectorization to handle different
inductions in the different SLP lanes. It also changes SLP
build to represent the initial value (but not the cycle) so
it can be enhanced to handle outer loop vectorization later.
Note this FAILs gcc.dg/vect/costmodel/x86_64/costmodel-pr30843.c
because it removes one CSE optimization that no longer works
with non-uniform initial value and step. I'll see to recover
from this after outer loop vectorization of inductions works.
It might be a bit friendlier to variable-size vectors now
but then we're now building the step vector from scalars ...
Martin Jambor [Mon, 2 Nov 2020 14:43:28 +0000 (15:43 +0100)]
ipa-cp: New debug counters for IPA-CP
Martin Liška has been asking me to add debug counters to the IPA-CP pass so
that testcase reductions are easier. The pass already has one for the bit
value propagation, so this patch adds one for value_range propagation
and one for the actual constant propagation.
gcc/ChangeLog:
2020-10-30 Martin Jambor <mjambor@suse.cz>
* dbgcnt.def (ipa_cp_values): New counter.
(ipa_cp_vr): Likewise.
* ipa-cp.c (decide_about_value): Check and bump ipa_cp_values debug
counter.
(decide_whether_version_node): Likewise.
(ipcp_store_vr_results):Check and bump ipa_cp_vr debug counter.
Christophe Lyon [Mon, 2 Nov 2020 14:40:10 +0000 (14:40 +0000)]
arm: Fix multiple inheritance thunks for thumb-1 with -mpure-code
When -mpure-code is used, we cannot load delta from code memory (like
we do without -mpure-code).
This patch builds the value of mi_delta into r3 with a series of
movs/adds/lsls.
We also do some cleanup by not emitting the function address and delta
via .word directives at the end of the thunk since we don't use them
with -mpure-code.
No need for new testcases, this bug was already identified by:
g++.dg/ipa/pr46287-3.C
g++.dg/ipa/pr46984.C
g++.dg/opt/thunk1.C
g++.dg/torture/pr46287.C
g++.dg/torture/pr45699.C
Christophe Lyon [Mon, 2 Nov 2020 14:39:52 +0000 (14:39 +0000)]
arm: Call thumb1_gen_const_int from thumb1_movsi_insn
thumb1_movsi_insn used the same algorithm to build a constant in asm
than thumb1_gen_const_int_1 does in RTL. Since the previous patch added
support for asm generation in thumb1_gen_const_int_1, this patch calls
it from thumb1_movsi_insn to avoid duplication.
We need to introduce a new proxy function, thumb1_gen_const_int_print
to select the right template.
This patch also adds a new testcase as the updated alternative is only
used by thumb-1 processors that also support movt/movw.
Christophe Lyon [Mon, 2 Nov 2020 14:39:24 +0000 (14:39 +0000)]
arm: Improve thumb1_gen_const_int
Enable thumb1_gen_const_int to generate RTL or asm depending on the
context, so that we avoid duplicating code to handle constants in
Thumb-1 with -mpure-code.
Use a template so that the algorithm is effectively shared, and
rely on two classes to handle the actual emission as RTL or asm.
The generated sequence is improved to handle right-shiftable and small
values with less instructions. We now generate:
The patch adds a testcase which does not fully exercise
thumb1_gen_const_int, as other existing patterns already catch small
constants. These parts of thumb1_gen_const_int are used by
arm_thumb1_mi_thunk.
gcc/
* config/arm/arm.c (thumb1_const_rtl, thumb1_const_print): New
classes.
(thumb1_gen_const_int): Rename to ...
(thumb1_gen_const_int_1): ... New helper function. Add capability
to emit either RTL or asm, improve generated code.
(thumb1_gen_const_int_rtl): New function.
* config/arm/arm-protos.h (thumb1_gen_const_int): Rename to
thumb1_gen_const_int_rtl.
* config/arm/thumb1.md: Call thumb1_gen_const_int_rtl instead
of thumb1_gen_const_int.
Thomas Schwinge [Fri, 30 Oct 2020 12:13:51 +0000 (13:13 +0100)]
Further improve Fortran column location information [PR92793]
Building on top of commit 9c81750c5bedd7883182ee2684a012c6210ebe1d "Fortran] PR
92793 - fix column used for error diagnostic", there is another place where we
have to use 'gfc_get_location' returning column-corrected locations.
For example, this improves column location information for OMP constructs.
Thomas Schwinge [Thu, 29 Oct 2020 09:29:19 +0000 (10:29 +0100)]
libgomp testsuite: tell warning from error diagnostics, etc. [PR80219, PR85303]
This changes makes 'dg-warning', 'dg-error', 'dg-bogus', 'dg-message' behave as
expected, and also enables use of relative line numbers as well as 'dg-line'.
This avoids analyzing reductions that are not relevant (thus dead)
which eventually will lead into crashes because the participating
stmts meta is not analyzed. For this to work the patch also
properly removes reduction groups that are not uniformly recognized
as patterns.
2020-11-02 Richard Biener <rguenther@suse.de>
PR tree-optimization/97558
* tree-vect-loop.c (vect_fixup_scalar_cycles_with_patterns):
Check for any mismatch in pattern vs. non-pattern and dissolve
the group if there is one.
* tree-vect-slp.c (vect_analyze_slp_instance): Avoid
analyzing not relevant reductions.
(vect_analyze_slp): Avoid analyzing not relevant reduction
groups.
Kito Cheng [Fri, 19 Jun 2020 07:36:23 +0000 (00:36 -0700)]
RISC-V: Add configure option: --with-multilib-generator to flexible config multi-lib settings.
- Able to configure complex multi-lib rule in configure time, without modify
any in-tree source.
- I was consider to implmenet this into `--with-multilib-list` option,
but I am not sure who will using that with riscv*-*-elf*, so I decide to
using another option name for that.
- --with-multilib-generator will pass arguments to multilib-generator, and
then using the generated multi-lib config file to build the toolchain.
e.g. Build riscv gcc, default arch/abi is rv64gc/lp64, and build multilib
for rv32imafd/ilp32 and rv32i/ilp32; rv32ic/ilp32 will reuse
rv32i/ilp32.
$ <GCC-SRC>/configure \
--target=riscv64-elf \
--with-arch=rv64gc --with-abi=lp64 \
--with-multilib-generator=rv32i-ilp32--c;rv32imafd-ilp32--
V3 Changes:
- Rename --with-multilib-config to --with-multilib-generator
- Check --with-multilib-generator and --with-multilib-list can't be used at
same time.
V2 Changes:
- Fix --with-multilib-config hanling on non riscv*-*-elf* triple.
Christophe Lyon [Mon, 2 Nov 2020 07:34:50 +0000 (07:34 +0000)]
arm: Improve handling of relocations with small offsets with -mpure-code on v6m (PR96770)
With -mpure-code on v6m (thumb-1), we can use small offsets with
upper/lower relocations to avoid the extra addition of the
offset.
This patch accepts expressions symbol+offset as legitimate constants
when the literal pool is disabled, making sure that the offset is
within the range supported by thumb-1 [0..255] as described in the
AAELF32 documentation.
It also makes sure that thumb1_movsi_insn emits an error in case we
try to use it with an unsupported RTL construct.
gcc/
PR target/96770
* config/arm/arm.c (thumb_legitimate_constant_p): Accept
(symbol_ref + addend) when literal pool is disabled.
(arm_valid_symbolic_address_p): Add support for thumb-1 without
MOVT/MOVW.
* config/arm/thumb1.md (*thumb1_movsi_insn): Accept (symbol_ref +
addend) in the pure-code alternative.
gcc/testsuite/
PR target/96770
* gcc.target/arm/pure-code/pr96770.c: New test.
Christophe Lyon [Mon, 2 Nov 2020 07:31:22 +0000 (07:31 +0000)]
arm: Avoid indirection with -mpure-code on v6m (PR96967)
With -mpure-code on v6m (thumb-1), to avoid a useless indirection when
building the address of a symbol, we want to consider SYMBOL_REF as a
legitimate constant. This way, we build the address using a series of
upper/lower relocations instead of loading the address from memory.
This patch also fixes a missing "clob" conds attribute for
thumb1_movsi_insn, needed because that alternative clobbers the flags.
gcc/
PR target/96967
* config/arm/arm.c (thumb_legitimate_constant_p): Add support for
disabled literal pool in thumb-1.
* config/arm/thumb1.md (thumb1_movsi_symbol_ref): Remove.
(*thumb1_movsi_insn): Add support for SYMBOL_REF with -mpure-code.
gcc/testsuite
PR target/96967
* gcc.target/arm/pure-code/pr96767.c: New test.
Iain Sandoe [Fri, 30 Oct 2020 19:06:58 +0000 (19:06 +0000)]
Objective-C/C++ : Improve '@' keyword locations.
When we are lexing tokens for Objective-C, we combine '@' tokens
with a following keyword (when that keyword is a valid Objective-C
one or, for Objective-C, one of the C++ keywords that can appear in
this position). The responsibility is passed on to the parser to
validate the resulting combination.
The combination of tokens was being done without applying the rule
to their locations - so that we get:
@property
^
instead of what the user might expect:
@property
^~~~~~~~~
This patch combines the source range of the keyword with that of the
'@' sign - which improves diagnostics.
gcc/c-family/ChangeLog:
* c-lex.c (c_lex_with_flags): When combining '@' with a
keyword for Objective-C, combine the location ranges too.
Iain Sandoe [Fri, 30 Oct 2020 19:24:07 +0000 (19:24 +0000)]
Objective-C++ : Address a FIXME.
We can avoid the spurious additional complaint about a closing
')' by short-circuiting the test in the case we know there's a
syntax error already reported.
gcc/cp/ChangeLog:
* parser.c (cp_parser_objc_at_property_declaration): Use any
exisiting syntax error to suppress complaints about a missing
closing parenthesis in parsing property attributes.
gcc/testsuite/ChangeLog:
* obj-c++.dg/property/at-property-1.mm: Adjust test after
fixing spurious error output.
Iain Buclaw [Sun, 1 Nov 2020 15:39:10 +0000 (16:39 +0100)]
ipa: Fix segmentation fault in function_summary<clone_info*>::get(cgraph_node*)
PR 97660 occurs when cgraph_node::get returns NULL, and this NULL
cgraph_node is then passed to clone_info::get. As the original assert
prior to the regressing change in r11-4587 allowed for the cgraph_node
to be NULL, clone_info::get is now only called when cgraph_node::get
returns a nonnull value.
Jonathan Wakely [Sun, 1 Nov 2020 10:56:36 +0000 (10:56 +0000)]
libstdc++: Define type traits for wchar_t even when libc support missing
This meets the requirement that std::is_integral_v<wchar_t> is true,
even when full library support for wchar_t via specializations of
char_traits etc. is not provided. This is done by checking
__WCHAR_TYPE__ to see if the compiler knows about the type, rather than
checking the library's own _GLIBCXX_USE_WCHAR_T autoconf macro.
This assumes that the C++ compiler correctly defines wchar_t as a
distinct type, not a typedef for one of the other integeral types. This
is always true for G++ and should be true for any supported non-GNU
compilers.
Similarly, the std::make_unsigned and std::make_signed traits and the
internal helpers std::__is_integer and std::__is_char are also changed
to depend on the same macro.
libstdc++-v3/ChangeLog:
* include/std/type_traits (is_integral<wchar_t>)
(make_unsigned<wchar_t>, make_signed<wchar_t>): Define based
on #ifdef __WCHAR_TYPE__ instead of _GLIBCXX_USE_WCHAR_T.
* include/bits/cpp_type_traits.h (__is_integer<wchar_t>)
(__is_char<wchar_t>): Likewise.
Jonathan Wakely [Sat, 31 Oct 2020 07:16:47 +0000 (07:16 +0000)]
libstdc++: Prefer double to long double in std::shuffle_order_engine
The transition algorithm for std::shuffle_order_engine uses long double
to ensure that the value (max() - min() + 1) can be accurately
represented, to avoid bias in the shuffling. However, when the base
engine's range is small enough we can avoid slower long double
arithmetic by using double. For example, long double is unnecessary for
any base engine returning 32-bit values.
This makes std::knuth_b::operator() about 15% faster on x86_64, and
probably even more on targets where long double uses soft-float.
libstdc++-v3/ChangeLog:
* include/bits/random.h (independent_bit_engine): Fix typo
in comment.
(shuffle_order_engine): Fix incorrect description in comment.
* include/bits/random.tcc (__representable_as_double
(__p1_representable_as_double): New helper functions.
(shuffle_order_engine::operator()): Use double for calculation
if (max() - min() + 1) is representable as double.
* testsuite/26_numerics/random/pr60037-neg.cc: Adjust dg-error
line number.
Jonathan Wakely [Sat, 31 Oct 2020 00:52:57 +0000 (00:52 +0000)]
libstdc++: Use double for unordered container load factors [PR 96958]
My previous commit for this PR changed the types from long double to
double, but didn't change the uses of __builtin_ceill and
__builtin_floorl. It also failed to change the non-inline functions in
src/c++11/hashtable_c++0x.cc. This should fix it properly now.
libstdc++-v3/ChangeLog:
PR libstdc++/96958
* include/bits/hashtable_policy.h (_Prime_rehash_policy)
(_Power2_rehash_policy): Use ceil and floor instead of ceill and
floorl.
* src/c++11/hashtable_c++0x.cc (_Prime_rehash_policy): Likewise.
Use double instead of long double.
git://gcc.gnu.org / gcc.git / log