Thomas Schwinge [Thu, 25 Jun 2020 09:59:42 +0000 (11:59 +0200)]
libgomp HSA/GCN plugins: don't prepend the 'HSA_RUNTIME_LIB' path to 'libhsa-runtime64.so'
For unknown reasons, this had gotten added for the libgomp HSA plugin in commit b8d89b03db5f212919e4571671ebb4f5f8b1e19d (r242749) "Remove build dependence on
HSA run-time", and later propagated into the GCN plugin.
Jakub Jelinek [Thu, 25 Mar 2021 10:33:35 +0000 (11:33 +0100)]
c-family: Fix up -Wduplicated-branches for union members [PR99565]
Honza has fairly recently changed operand_equal_p to compare
DECL_FIELD_OFFSET for COMPONENT_REFs when comparing addresses.
As the first testcase in this patch shows, while that is very nice
for optimizations, for the -Wduplicated-branches warning it causes
regressions. Pedantically a union in both C and C++ has only one
active member at a time, so using some other union member even if it has the
same type is UB, so I think the warning shouldn't warn when it sees access
to different fields that happen to have the same offset and should consider
them different.
In my first attempt to fix this I've keyed the old behavior on
OEP_LEXICOGRAPHIC, but unfortunately that has various problems, the warning
has a quick non-lexicographic compare in build_conditional_expr* and another
lexicographic more expensive one later during genericization and turning the
first one into lexicographic would mean wasting compile time on large
conditionals.
So, this patch instead introduces a new OEP_ flag and makes sure to pass it
to operand_equal_p in all -Wduplicated-branches cases.
The cvt.c changes are because on the other testcase we were warning with
UNKNOWN_LOCATION, so the user wouldn't really know where the questionable
code is.
2021-03-25 Jakub Jelinek <jakub@redhat.com>
PR c++/99565
* tree-core.h (enum operand_equal_flag): Add OEP_ADDRESS_OF_SAME_FIELD.
* fold-const.c (operand_compare::operand_equal_p): Don't compare
field offsets if OEP_ADDRESS_OF_SAME_FIELD.
* c-warn.c (do_warn_duplicated_branches): Pass also
OEP_ADDRESS_OF_SAME_FIELD to operand_equal_p.
* c-typeck.c (build_conditional_expr): Pass OEP_ADDRESS_OF_SAME_FIELD
to operand_equal_p.
* call.c (build_conditional_expr_1): Pass OEP_ADDRESS_OF_SAME_FIELD
to operand_equal_p.
* cvt.c (convert_to_void): Preserve location_t on COND_EXPR or
or COMPOUND_EXPR.
* g++.dg/warn/Wduplicated-branches6.C: New test.
* g++.dg/warn/Wduplicated-branches7.C: New test.
H.J. Lu [Wed, 24 Mar 2021 03:04:58 +0000 (20:04 -0700)]
x86: Skip ISA check for always_inline in system headers
For always_inline in system headers, we don't know if caller's ISAs are
compatible with callee's ISAs until much later. Skip ISA check for
always_inline in system headers if caller has target attribute.
gcc/
PR target/98209
PR target/99744
* config/i386/i386.c (ix86_can_inline_p): Don't check ISA for
always_inline in system headers.
Thomas Schwinge [Thu, 11 Mar 2021 09:52:59 +0000 (10:52 +0100)]
'libgomp.oacc-fortran/derivedtypes-arrays-1.f90' OpenACC 'serial' construct diagnostic for nvptx offloading
Fixup for recent commit d28f3da11d8c0aed9b746689d723022a9b5ec04c "openacc: Fix
lowering for derived-type mappings through array elements". With nvptx
offloading we see the usual:
[...]/libgomp.oacc-fortran/derivedtypes-arrays-1.f90: In function 'MAIN__._omp_fn.0':
[...]/libgomp.oacc-fortran/derivedtypes-arrays-1.f90:90:40: warning: using vector_length (32), ignoring 1
libgomp/
* testsuite/libgomp.oacc-fortran/derivedtypes-arrays-1.f90:
OpenACC 'serial' construct diagnostic for nvptx offloading.
This avoids confusing the hybrid vectorization code with SLP
patterns by not marking SLP pattern covered stmts as patterns
(they are marked as SLP patterns already). This means that loop
vectorization will vectorize the scalar stmt rather than the SLP
pattern stmt (which it can't anyway).
2021-03-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/99746
* tree-vect-slp-patterns.c (complex_pattern::build): Do not mark
the scalar stmt as patterned. Instead set up required things
manually.
David Malcolm [Thu, 25 Mar 2021 00:47:57 +0000 (20:47 -0400)]
analyzer; reset sm-state for SSA names at def-stmts [PR93695,PR99044,PR99716]
Various false positives from -fanalyzer involve SSA names in loops,
where sm-state associated with an SSA name from one iteration is
erroneously reused in a subsequent iteration.
For example, PR analyzer/99716 describes a false
"double 'fclose' of FILE 'fp'"
on:
for (i = 0; i < 2; ++i) {
FILE *fp = fopen ("/tmp/test", "w");
fprintf (fp, "hello");
fclose (fp);
}
where fp_7 transitions to "closed" at the fclose, but is not
reset at the subsequent fopen, leading to the false positive
when the fclose is re-reached.
The fix is to reset sm-state for svalues that involve an SSA name
at the SSA name's def-stmt, since the def-stmt effectively changes
the meaning of those related svalues.
gcc/analyzer/ChangeLog:
PR analyzer/93695
PR analyzer/99044
PR analyzer/99716
* engine.cc (exploded_node::on_stmt): Clear sm-state involving
an SSA name at the def-stmt of that SSA name.
* program-state.cc (sm_state_map::purge_state_involving): New.
* program-state.h (sm_state_map::purge_state_involving): New decl.
* region-model.cc (selftest::test_involves_p): New.
(selftest::analyzer_region_model_cc_tests): Call it.
* svalue.cc (class involvement_visitor): New class
(svalue::involves_p): New.
* svalue.h (svalue::involves_p): New decl.
gcc/testsuite/ChangeLog:
PR analyzer/93695
PR analyzer/99044
PR analyzer/99716
* gcc.dg/analyzer/attr-malloc-CVE-2019-19078-usb-leak.c: Remove
xfail.
* gcc.dg/analyzer/pr93695-1.c: New test.
* gcc.dg/analyzer/pr99044-1.c: New test.
* gcc.dg/analyzer/pr99044-2.c: New test.
* gcc.dg/analyzer/pr99716-1.c: New test.
* gcc.dg/analyzer/pr99716-2.c: New test.
* gcc.dg/analyzer/pr99716-3.c: New test.
Martin Jambor [Wed, 24 Mar 2021 19:27:27 +0000 (20:27 +0100)]
ipa: Check that scalar types that IPA-CP comes up with are sane (PR99122)
This patch fixes the last bit of PR 99122 where various bits of IPA
infrastructure are presented with a program with type mismatches that
make it have undefined behavior, and when inlining or performing
IPA-CP, and encountering such mismatch, we basically try to
VIEW_CONVERT_EXPR whatever the caller has into whatever the callee has
or simply use an empty constructor if that cannot be done. This
however does not work when the callee has VLA parameters because we
ICE in the process.
Richi has already disabled inlining for such cases, this patch avoids
the issue in IPA-CP. It adds checks that whatever constant the
propagation arrived at is actually compatible or fold_convertible to
the callees formal parameer type. Unlike in the past, we now have
types of all parameters of functions that we have analyzed, even with
LTO, and so can do it.
This should prevent only bogus propagations. I have looked at the
effect of the patch on WPA of Firefox and did not have any.
I have bootstrapped and LTO bootstrapped and tested the patch on
x86_64-linux. OK for trunk? And perhaps later for GCC 10 too?
Thanks
gcc/ChangeLog:
2021-02-26 Martin Jambor <mjambor@suse.cz>
PR ipa/99122
* ipa-cp.c (initialize_node_lattices): Mark as bottom all
parameters with unknown type.
(ipacp_value_safe_for_type): New function.
(propagate_vals_across_arith_jfunc): Verify that the constant type
can be used for a type of the formal parameter.
(propagate_vals_across_ancestor): Likewise.
(propagate_scalar_across_jump_function): Likewise. Pass the type
also to propagate_vals_across_ancestor.
gcc/testsuite/ChangeLog:
2021-02-26 Martin Jambor <mjambor@suse.cz>
PR ipa/99122
* gcc.dg/pr99122-3.c: Remove -fno-ipa-cp from options.
Jakub Jelinek [Wed, 24 Mar 2021 10:22:35 +0000 (11:22 +0100)]
arm: Fix some more vec-common.md patterns for iwmmxt [PR99724]
The following patch fixes similar issues as in PR98849;
in older gcc versions, the expanders were present in neon.md guarded
with TARGET_NEON, but they got moved to vec-common.md and guarded with
ARM_HAVE_<MODE>_ARITH so that they handle both MVE and Neon.
The macros are enabled for some modes even for iwmmxt which has some
vector support for those modes, but only limited. In particular,
neither the one_cmpl, nor neg, nor movmisalign patterns are present.
For some reason I've failed to construct something that ICEs with
movmisalign, so that is not covered by the testsuite, but both
one_cmpl and neg ICE.
Alexandre Oliva [Wed, 24 Mar 2021 08:50:37 +0000 (05:50 -0300)]
run sysconf-requiring test on systems that support it
Some gcc.target/i386 tests requires the mmap feature, but that's not
enough for the test to be able to call sysconf.
This patch introduces a sysconf feature, analogous to mmap, and adds
it to tests in gcc.target/i386 that call sysconf.
There are other tests within gcc.dg and g++.dg that call sysconf, but
I haven't added the tag to them, because they already cover it with
target triplets. I was a little nervous about dropping the triplets,
and saw how they implied sysconf, so I left those alone.
for gcc/ChangeLog
* doc/sourcebuild.texi (sysconf): New effective target.
Alexandre Oliva [Wed, 24 Mar 2021 08:44:36 +0000 (05:44 -0300)]
tighten funcspec regexps
In -mcmodel=large, callee symbols are pulled ahead of the call insns.
The patterns in funcspec-[12].c tests in gcc.target/i386 match even
line breaks between 'call' and a function symbol expected to be
called, however, so it ends up unexpectedly matching a previous,
unrelated indirect call, up to the insn that loads the address of the
intended callee to a register, for all but the first callee, that
doesn't have a call insn before it.
All of these apparent passes are false positives. We are NOT
generating the expected call insns.
This patch fixes only the patterns, so that they won't trigger false
positives any more. There are several dozens of other tests that fail
with -mcmodel=large for similar reasons, but I'm still not sure about
how to deal with them. I see no point in holding up this small
improvement over the lack of a larger solution of a different problem,
though.
for gcc/testsuite/ChangeLog
* gcc.target/i386/funcspec-2.c: Tighten regexps to avoid false
positives with -mcmodel=large.
* gcc.target/i386/funcspec-3.c: Likewise.
Alexandre Oliva [Wed, 24 Mar 2021 08:44:35 +0000 (05:44 -0300)]
fix ssse3_pshufbv8qi3 post-reload const pool load
The split in ssse3_pshufbv8qi3 forces a const vector into the constant
pool, and loads from it. That runs after reload, so if the load
requires any reloading, we're out of luck. Indeed, if the load
address is not legitimate, e.g. -mcmodel=large, the insn is no longer
recognized.
This patch turns the constant into an input operand, introduces an
expander to generate the constant unconditionally, and arranges for
this input operand to be retained as an unused immediate in the
alternatives that don't undergo splitting, and for it to be loaded
into the scratch register for those that do.
It is now the register allocator that arranges to load the const
vector into a register, so it deals with whatever legitimizing steps
needed for the target configuration.
for gcc/ChangeLog
* config/i386/predicates.md (reg_or_const_vec_operand): New.
* config/i386/sse.md (ssse3_pshufbv8qi3): Add an expander for
the now *-prefixed insn_and_split, turn the splitter const vec
into an input for the insn, making it an ignored immediate for
non-split cases, and loaded into the scratch register
otherwise.
[PR99581] Use relaxed memory for more aarch64 memory constraints
The original patch for PR99581 resulted in GCC testsuite regression as
some constraints were not declared as relaxed memory ones. This patch
fixes this.
gcc/ChangeLog:
PR target/99581
* config/aarch64/constraints.md (Utq, UOb, UOh, UOw, UOd, UOty):
Use define_relaxed_memory_constraint for them.
Nathan Sidwell [Tue, 23 Mar 2021 19:23:30 +0000 (12:23 -0700)]
c++: Note duplicates in symbol table [PR 99283]
I ran into this reducing 99283, we were failing to mark binding
vectors when the current TU declares a duplicate decl (as opposed to
an import introduces a duplicate).
PR c++/99283
gcc/cp/
* name-lookup.c (check_module_override): Set global or partition
DUP on the binding vector.
gcc/testsuite/
* g++.dg/modules/pr99283-1_a.H: New.
* g++.dg/modules/pr99283-1_b.H: New.
Commit efb6bc55a93a ("fwprop: Allow (subreg (mem)) simplifications")
introduced a check that was supposed to look at the propagated def's
number of uses. It uses insn_info::num_uses (), which in reality
returns the number of uses def's insn has. The whole change therefore
works only by accident.
Fix by looking at set_info's uses instead of insn_info's uses. This
requires passing around set_info instead of insn_info.
gcc/ChangeLog:
2021-03-02 Ilya Leoshkevich <iii@linux.ibm.com>
* fwprop.c (fwprop_propagation::fwprop_propagation): Look at
set_info's uses.
(try_fwprop_subst_note): Use set_info instead of insn_info.
(try_fwprop_subst_pattern): Likewise.
(try_fwprop_subst_notes): Likewise.
(try_fwprop_subst): Likewise.
(forward_propagate_subreg): Likewise.
(forward_propagate_and_simplify): Likewise.
(forward_propagate_into): Likewise.
* rtl-ssa/accesses.h (set_info::single_nondebug_use) New
method.
(set_info::single_nondebug_insn_use): Likewise.
(set_info::single_phi_use): Likewise.
* rtl-ssa/member-fns.inl (set_info::single_nondebug_use) New
method.
(set_info::single_nondebug_insn_use): Likewise.
(set_info::single_phi_use): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/s390/vector/long-double-asm-abi.c: New test.
Moritz Sichert [Tue, 23 Mar 2021 15:47:37 +0000 (15:47 +0000)]
libstdc++: Avoid accidental ADL when calling make_reverse_iterator
std::ranges::reverse_view uses make_reverse_iterator in its
implementation as described in [range.reverse.view]. This accidentally
allows ADL as an unqualified name is used in the call. According to
[contents], however, this should be treated as a qualified lookup into
the std namespace.
This leads to errors due to ambiguous name lookups when another
make_reverse_iterator function is found via ADL.
libstdc++-v3/Changelog:
* include/std/ranges (reverse_view::begin, reverse_view::end):
Qualify make_reverse_iterator calls to avoid ADL.
* testsuite/std/ranges/adaptors/reverse.cc: Test that
views::reverse works when make_reverse_iterator is defined
in an associated namespace.
testsuite/arm: Add arm_dsp_ok effective target and use it in arm/acle/dsp_arith.c
gcc.target/arm/acle/dsp_arith.c uses DSP intrinsics, which arm_acle.h
defines only with __ARM_FEATURE_DSP, so make the test check for that
property rather than arm_qbit_ok.
However, the existing arm_dsp effective target only checks if DSP
features are supported with the current multilib rather than trying
-march and -mfloat-abi options. Thus we introduce a similar effective
target, arm_dsp_ok and associated dg-add-options.
This makes dsp_arith.c unsupported rather than failed when no option
combination is suitable, for instance when running the tests with
-mcpu=cortex-m3.
testsuite/arm: Fix -mfloat-abi order in arm_v8_1m_mve_ok_nocache and arm_v8_1m_mve_fp_ok_nocache
Make the order in which we try -mfloat-abi options consistent with the
other similar effective targets: try softfp first, then hard.
This shows that a few tests implicitly rely on -mfloat-abi=hard, so we
add this option via dg-additional-options so that it comes after any
potential -mfloat-abi option that the preceding effective-targets
might have added.
armv8_1m-fpXX-move-1.c tests don't need arm_hard_ok because they don't
include arm_mve.h: adding -mfloat-abi=hard when using a soft/softfp
toolchain does not lead to the missing include gnu/stubs-*.h error.
This patch makes armv8_1m-fpXX-move-1.c pass on arm-linux-gnueabi, and
the other tests become unsupported (instead of fail) on this target.
On arm-eabi with default cpu/fpu/mode and a+rm multilibs, the same
mve/intrinsics/* tests become unsupported instead of pass because
arm_hard_ok fails with "selected processor lacks an FPU". Since we
also override the fpu via dg-options, we'd need another effective
target (say arm_hard_mve_ok) that would check -mfloat-abi=hard
-mfpu=auto -march=armv8.1-m.main+mve.fp at the same time. But we have
already so many arm effective targets, it doesn't seem like a good way
forward.
testsuite/arm: Add arm_hard_ok check in armv8_2-fp16-scalar-2.c
This test relies on -mfloat-abi=hard to pass (otherwise
test_mov_imm_[12] directly build the 1.0 fp16 representation via movw
r0, #15360 rather than using vmov.f16 s0, #1.0e+0 as expected by
scan-assembler-times)
Adding the arm_hard_ok check makes the test unsupported eg. on
arm-linux-gnueabi instead of reporting a failure.
testsuite/arm: Add arm_softfp_ok or arm_hard_ok as needed.
Several tests override the -mfloat-abi option detected by their
effective targets. Make sure it is supported, so that these tests are
unsupported rather than failures (the inclusion of arm_neon.h
otherwise fails for lack of gnu/stubs-*.h)
This avoids failures with
bfloat16_simd_2_1.c
bfloat16_simd_3_1.c
bf16_vldn_1.c
bf16_vstn_1.c on arm-linux-gnueabi
and
pr51968.c
bfloat16_simd_1_2.c
bfloat16_simd_2_2.c
bfloat16_simd_3_2.c on arm-linux-gnueabihf.
On arm-eabi with default cpu/fpu/mode and a+rm multilibs,
bfloat16_simd_2_1.c, bfloat16_simd_3_1.c, bf16_vstn_1.c and
bf16_vldn_1.c become unsupported instead of pass because arm_hard_ok
fails with "selected processor lacks an FPU". Since we also override
the fpu in dg-additional-options, we'd need another effective target
(say arm_hard_neon_ok) that would check -mfloat-abi=hard -mfpu=neon at
the same time. But we have already so many arm effective targets, it
doesn't seem like a good way forward.
These tests pass with their current dg-add-options, no need to force
-mfloat=abi.
I've noticed no impact on armv8_1m-shift-imm-1.c and
armv8_1m-shift-reg-1.c, bf16_reinterpret.c now passes on
arm-linux-gnueabi and bf16_dup.c now passes on arm-linux-gnueabihf.
This allows pr51534.c to pass when forcing -mfloat-abi=soft in
runtestflags, otherwise we get an error '-mfloat-abi=soft and
-mfloat-abi=hard may not be used together' because we try to compile
with both flags.
testsuite/arm: Add arm_v8_2a_i8mm options in gcc.target/arm/simd/vmmla_1.c
We need to add the options corresponding to the arm_v8_2a_i8mm_ok
effective target in order to use the right float-abi option:
-mfloat-abi=softfp makes the test pass for arm-linux-gnueabi,
while no -mfloat-abi option is needed for arm-linux-gnueabihf.
Christophe Lyon [Thu, 18 Mar 2021 14:02:53 +0000 (14:02 +0000)]
testsuite/arm: Add arm_v8_2a_fp16_neon and arm_v8_2a_bf16_neon options
A few tests lack the dg-add-options directives associated with the
dg-require-effective-target they are using. Adding them enables to
pass the right float-abi option, and thus make the tests pass instead
of emit an error.
For instance, we now pass -mfloat-abi=softfp on arm-linux-gnueabi
targets and the tests pass.
Jonathan Wakely [Tue, 23 Mar 2021 13:08:32 +0000 (13:08 +0000)]
libstdc++: Disable "ALT128" long double support for Clang
Clang does not currently support the __ibm128 type [1] and only supports
the __ieee128 type in the unreleased 12.0.0 version [2]. That means it
is not possible to provide support for -mabi=ieeelongdouble with Clang
in an ABI compatible way (as we do for GCC by defining new facets and
other types in the __gnu_cxx_ldbl128 namespace).
By preventing the definition of _GLIBCXX_LONG_DOUBLE_ALT128_COMPAT when
compiling with Clang, all uses of __ibm128 and __ieee128 types will be
disabled. This can be revisited in future when Clang supports the types
(and provides a way to detect that support using the preprocessor).
Marek Polacek [Wed, 10 Mar 2021 00:23:48 +0000 (19:23 -0500)]
c++: Fix bogus warning in deprecated namespace [PR99318]
In GCC 10, I introduced cp_warn_deprecated_use_scopes so that we can
handle attribute deprecated on a namespace declaration. This
function walks the decl's contexts so that we warn for code like
namespace [[deprecated]] N { struct S { }; }
N::S s;
We call cp_warn_deprecated_use_scopes when we encounter a TYPE_DECL.
But in the following testcase we have a TYPE_DECL whose context is
a deprecated function; that itself is not a reason to warn. This
patch limits for which entities we call cp_warn_deprecated_use;
essentially it's what can follow ::.
I noticed that we didn't test that
struct [[deprecated]] S { static void fn(); };
S::fn();
produces the expected warning, so I've added gen-attrs-73.C.
gcc/cp/ChangeLog:
PR c++/99318
* decl2.c (cp_warn_deprecated_use_scopes): Only call
cp_warn_deprecated_use when decl is a namespace, class, or enum.
gcc/testsuite/ChangeLog:
PR c++/99318
* g++.dg/cpp0x/attributes-namespace6.C: New test.
* g++.dg/cpp0x/gen-attrs-73.C: New test.
aarch64: Make aarch64_add_offset work with -ftrapv [PR99540]
aarch64_add_offset uses expand_mult to multiply the SVE VL by an
out-of-range constant. expand_mult takes an argument to indicate
whether the multiplication is signed or unsigned, but in this
context the multiplication is effectively signless and so the
choice seemed arbitrary.
However, one of the things that the signedness input does is
indicate whether signed overflow should be trapped for -ftrapv.
We don't want that here, so we must treat the multiplication
as unsigned.
gcc/
2021-03-23 Jakub Jelinek <jakub@redhat.com>
PR target/99540
* config/aarch64/aarch64.c (aarch64_add_offset): Tell
expand_mult to perform an unsigned rather than a signed
multiplication.
gcc/testsuite/
2021-03-23 Richard Sandiford <richard.sandiford@arm.com>
PR target/99540
* gcc.dg/vect/pr99540.c: New test.
Nathan Sidwell [Tue, 23 Mar 2021 12:18:04 +0000 (05:18 -0700)]
c++: Over-zealous assert [PR 99239]
This was simply an overzealous assert. Possibly correct thinking at
the time that code was written, but not true now. Of course we can
have imported artificial decls.
Marcus Comstedt [Fri, 19 Mar 2021 19:49:06 +0000 (20:49 +0100)]
RISC-V: Fix trampoline generation on big endian
gcc/
* config/riscv/riscv.c (riscv_swap_instruction): New function
to byteswap an SImode rtx containing an instruction.
(riscv_trampoline_init): Byteswap the generated instructions
when needed.
Jakub Jelinek [Tue, 23 Mar 2021 09:23:42 +0000 (10:23 +0100)]
c++: Diagnose references to void in structured bindings [PR99650]
We ICE on the following testcase, because std::tuple_element<...,...>::type
is void and for structured bindings we therefore need to create
void & or void && which is invalid. We created such REFERENCE_TYPE and
later ICEd in the middle-end.
The following patch fixes it by diagnosing that.
2021-03-23 Jakub Jelinek <jakub@redhat.com>
PR c++/99650
* decl.c (cp_finish_decomp): Diagnose void initializers when
using tuple_element and get.
Jonathan Wakely [Mon, 22 Mar 2021 17:11:21 +0000 (17:11 +0000)]
libstdc++: Implement string_view range constructor for C++20
This implements the new string_view constructor proposed by P1989R2.
This hasn't been voted into the C++23 draft yet, but it's been reviewed
by LWG and is expected to be approved at the next WG21 meeting.
libstdc++-v3/ChangeLog:
* include/std/string_view (basic_string_view(Range&&)): Define new
constructor and deduction guide.
* testsuite/21_strings/basic_string_view/cons/char/range_c++20.cc: New test.
* testsuite/21_strings/basic_string_view/cons/wchar_t/range_c++20.cc: New test.
We were not correctly handling cross-module redeclarations of
partial-specializations. They have their own TEMPLATE_DECL, which we
need to locate. I had a FIXME there about this case. Guess it's
fixed now.
[PR99581] Define relaxed memory and use it for aarch64
aarch64 needs to skip memory address validation for LD1R insns. Skipping
the address validation may result in LRA crash for some targets when usual
memory constraint is used. This patch introduces define_relaxed_memory_constraint,
skipping address validation for it, and defining relaxed memory for
aarch64 LD1r insn memory operand.
gcc/ChangeLog:
PR target/99581
* config/aarch64/constraints.md (UtQ): Use
define_relaxed_memory_constraint for it.
* doc/md.texi (define_relaxed_memory_constraint): Describe it.
* genoutput.c (main): Process DEFINE_RELAXED_MEMORY_CONSTRAINT.
* genpreds.c (constraint_data): Add bitfield is_relaxed_memory.
(have_relaxed_memory_constraints): New static var.
(relaxed_memory_start, relaxed_memory_end): Ditto.
(add_constraint): Add arg is_relaxed_memory. Check name for
relaxed memory. Set up is_relaxed_memory in constraint_data and
have_relaxed_memory_constraints. Adjust calls.
(choose_enum_order): Process relaxed memory.
(write_tm_preds_h): Ditto.
(main): Process DEFINE_RELAXED_MEMORY_CONSTRAINT.
* gensupport.c (process_rtx): Process DEFINE_RELAXED_MEMORY_CONSTRAINT.
* ira-costs.c (record_reg_classes): Process CT_RELAXED_MEMORY.
* ira-lives.c (single_reg_class): Use
insn_extra_relaxed_memory_constraint.
* ira.c (ira_setup_alts): CT_RELAXED_MEMORY.
* lra-constraints.c (valid_address_p): Use
insn_extra_relaxed_memory_constraint instead of other memory
constraints.
(process_alt_operands): Process CT_RELAXED_MEMORY.
(curr_insn_transform): Use insn_extra_relaxed_memory_constraint.
* recog.c (asm_operand_ok, preprocess_constraints): Process
CT_RELAXED_MEMORY.
* reload.c (find_reloads): Ditto.
* rtl.def (DEFINE_RELAXED_MEMORY_CONSTRAINT): New.
* stmt.c (parse_input_constraint): Use
insn_extra_relaxed_memory_constraint.
Jonathan Wakely [Mon, 22 Mar 2021 15:15:12 +0000 (15:15 +0000)]
libstdc++: Add noexcept to std::begin etc as per LWG 2280 and 3537
This implements the proposed changes for LWG 3537 (which we're allowed
to do as an extension whatever the outcome of the issue). I noticed we
didn't implement LWG 2280 completely, as the std::begin and std::end
overloads for arrays were not noexcept.
libstdc++-v3/ChangeLog:
* include/bits/range_access.h (begin(T (&)[N]), end(T (&)[N])):
Add missing 'noexcept' as per LWG 2280.
(rbegin(T (&)[N]), rend(T (&)[N]), rbegin(initializer_list<T>))
(rend(initializer_list<T>)): Add 'noexcept' as per LWG 3537.
* testsuite/24_iterators/range_access/range_access.cc: Check for
expected noexcept specifiers. Check result types of generic
std::begin and std::end overloads.
* testsuite/24_iterators/range_access/range_access_cpp14.cc:
Check for expected noexcept specifiers.
* testsuite/24_iterators/range_access/range_access_cpp17.cc:
Likewise.
Nathan Sidwell [Thu, 18 Mar 2021 12:12:59 +0000 (05:12 -0700)]
c++: duplicate alias templates with decltype [PR 99425]
This failure was ultimately from incorrect handling of alias
templates, but required a specific set of occurrences to happen in the
specialization hash table. This cleans up the specialization
streaming to add alias instantiations at the same point as other
instantiations. I also removed some unneeded global variables dealing
with mapping of duplicate decl contexts.
Alex Coplan [Mon, 22 Mar 2021 14:43:15 +0000 (14:43 +0000)]
arm: Fix MVE ICEs with vector moves and -mpure-code [PR97252]
This fixes around 500 ICEs in the testsuite which can be seen when
testing with -march=armv8.1-m.main+mve -mfloat-abi=hard -mpure-code
(leaving the testsuite free of ICEs in this configuration). All of the
ICEs are in arm_print_operand (which is expecting a mem and gets another
rtx, e.g. a const_vector) when running the output code for
*mve_mov<mode> in alternative 4.
The issue is that MVE vector moves were relying on the arm_reorg pass to
move constant vectors that we can't easily synthesize to the literal
pool. This doesn't work for -mpure-code where the literal pool is
disabled. LLVM puts these in .rodata: I've chosen to do the same here.
With this change, for -mpure-code, we no longer want to allow a constant
on the RHS of a vector load in RA. To achieve this, I added a new
constraint which matches constants only if the literal pool is
available.
gcc/ChangeLog:
PR target/97252
* config/arm/arm-protos.h (neon_make_constant): Add generate
argument to guard emitting insns, default to true.
* config/arm/arm.c (arm_legitimate_constant_p_1): Reject
CONST_VECTORs which neon_make_constant can't handle.
(neon_vdup_constant): Add generate argument, avoid emitting
insns if it's not set.
(neon_make_constant): Plumb new generate argument through.
* config/arm/constraints.md (Ui): New. Use it...
* config/arm/mve.md (*mve_mov<mode>): ... here.
* config/arm/vec-common.md (movv8hf): Use neon_make_constant to
synthesize constants.
Richard Biener [Mon, 22 Mar 2021 08:32:28 +0000 (09:32 +0100)]
Warn to not add debug hook targets
This adds a boiler-plate warning to the debug hooks structure to
strongly discourage people from adding new debug hook targets since
we want to get rid of the current abstraction in favor of maintaining
a DWARF view of debug in the middle-end and have support for alternate
output formats to be generated off that DWARF representation.
This avoids endless cycling when a PHI node with unchanged backedge
value (the PHI result appearing there) is subject to CSE since doing
that effectively alters the hash entry. The way to avoid this is
to ignore such edges when processing the PHI node.
2021-03-22 Richard Biener <rguenther@suse.de>
PR tree-optimization/99694
* tree-ssa-sccvn.c (visit_phi): Ignore edges with the
PHI result.
Jakub Jelinek [Mon, 22 Mar 2021 07:52:04 +0000 (08:52 +0100)]
debug: Fix __int128 handling in dwarf2out [PR99562]
The PR66728 changes broke __int128 handling.
It emits wide_int numbers in their minimum unsigned precision
rather than in their full precision.
The problem is then that e.g. the DW_OP_implicit_value path:
int_mode = as_a <scalar_int_mode> (mode);
loc_result = new_loc_descr (DW_OP_implicit_value,
GET_MODE_SIZE (int_mode), 0);
loc_result->dw_loc_oprnd2.val_class = dw_val_class_wide_int;
loc_result->dw_loc_oprnd2.v.val_wide = ggc_alloc<wide_int> ();
*loc_result->dw_loc_oprnd2.v.val_wide = rtx_mode_t (rtl, int_mode);
emits invalid DWARF. In particular this patch fixes there multiple
occurences of:
.byte 0x9e # DW_OP_implicit_value
.uleb128 0x10
.quad 0xffffffffffffffff
+ .quad 0
.quad .LVL46 # Location list begin address (*.LLST40)
.quad .LFE14 # Location list end address (*.LLST40)
where we said the value has 16 byte size but then only emitted 8 byte value.
My understanding is that most of the places that use val_wide expect
the precision they chose (the one of the mode they want etc.), the only
exception is the add_const_value_attribute case where it deals with
VOIDmode CONST_WIDE_INTs, for that I agree when we don't have a mode
we need to fallback to minimum precision (not sure if maximum of
min_precision UNSIGNED and SIGNED wouldn't be better, then consumers
would know if it is signed or unsigned by looking at the MSB),
but that code already computes the precision, just decided to
create the wide_int with much larger precision (e.g. 512 bit
on x86_64).
2021-03-22 Jakub Jelinek <jakub@redhat.com>
PR debug/99562
PR debug/66728
* dwarf2out.c (get_full_len): Use get_precision rather than
min_precision.
(add_const_value_attribute): Make sure add_AT_wide argument has
precision prec rather than some very wide one.
Kewen Lin [Thu, 18 Mar 2021 06:22:59 +0000 (01:22 -0500)]
rs6000: Fix some unexpected empty split conditions
This patch is to fix empty split-conditions of some
define_insn_and_split definitions where their conditions for
define_insn part aren't empty. As Segher and Mike pointed
out, they can sometimes lead to unexpected consequences.
Bootstrapped/regtested on powerpc64le-linux-gnu P9 and
powerpc64-linux-gnu P8.
Xionghu Luo [Mon, 22 Mar 2021 02:14:02 +0000 (21:14 -0500)]
rs6000: Convert the vector set variable idx to DImode [PR98914]
vec_insert defines the element argument type to be signed int by ELFv2
ABI. When expanding a vector with a variable rtx, convert the rtx type
to DImode to support both intrinsic usage and other callers from
rs6000_expand_vector_init produced by v[k] = val when k is long type.
Jakub Jelinek [Sun, 21 Mar 2021 16:27:39 +0000 (17:27 +0100)]
dwarf2out: Fix debug info for 2 byte floats [PR99388]
Aarch64, ARM and a couple of other architectures have 16-bit floats, HFmode.
As can be seen e.g. on
void
foo (void)
{
__fp16 a = 1.0;
asm ("nop");
a = 2.0;
asm ("nop");
a = 3.0;
asm ("nop");
}
testcase, GCC mishandles this on the dwarf2out.c side by assuming all
floating point types have sizes in multiples of 4 bytes, so what GCC emits
is it says that e.g. the DW_OP_implicit_value will be 2 bytes but then
doesn't emit anything and so anything emitted after it is treated by
consumers as the value and then they get out of sync.
real_to_target which insert_float uses indeed fills it that way, but putting
into an array of long 32 bits each time, but for the half floats it puts
everything into the least significant 16 bits of the first long no matter
what endianity host or target has.
The following patch fixes it. With the patch the -g -O2 -dA output changes
(in a cross without .uleb128 support):
.byte 0x9e // DW_OP_implicit_value
.byte 0x2 // uleb128 0x2
+ .2byte 0x3c00 // fp or vector constant word 0
.byte 0x7 // DW_LLE_start_end (*.LLST0)
.8byte .LVL1 // Location list begin address (*.LLST0)
.8byte .LVL2 // Location list end address (*.LLST0)
.byte 0x4 // uleb128 0x4; Location expression size
.byte 0x9e // DW_OP_implicit_value
.byte 0x2 // uleb128 0x2
+ .2byte 0x4000 // fp or vector constant word 0
.byte 0x7 // DW_LLE_start_end (*.LLST0)
.8byte .LVL2 // Location list begin address (*.LLST0)
.8byte .LFE0 // Location list end address (*.LLST0)
.byte 0x4 // uleb128 0x4; Location expression size
.byte 0x9e // DW_OP_implicit_value
.byte 0x2 // uleb128 0x2
+ .2byte 0x4200 // fp or vector constant word 0
.byte 0 // DW_LLE_end_of_list (*.LLST0)
Bootstrapped/regtested on x86_64-linux, aarch64-linux and
armv7hl-linux-gnueabi, ok for trunk?
I fear the CONST_VECTOR case is still broken, while HFmode elements of vectors
should be fine (it uses eltsize of the element sizes) and likewise SFmode could
be fine, DFmode vectors are emitted as two 32-bit ints regardless of endianity
and I'm afraid it can't be right on big-endian. But I haven't been able to
create a testcase that emits a CONST_VECTOR, for e.g. unused vector vars
with constant operands we emit CONCATN during expansion and thus ...
DW_OP_*piece for each element of the vector and for
DW_TAG_call_site_parameter we give up (because we handle CONST_VECTOR only
in loc_descriptor, not mem_loc_descriptor).
2021-03-21 Jakub Jelinek <jakub@redhat.com>
PR debug/99388
* dwarf2out.c (insert_float): Change return type from void to
unsigned, handle GET_MODE_SIZE (mode) == 2 and return element size.
(mem_loc_descriptor, loc_descriptor, add_const_value_attribute):
Adjust callers.
Jakub Jelinek [Sat, 20 Mar 2021 16:02:06 +0000 (17:02 +0100)]
c-family: Fix PR94272 -fcompare-debug issue even for C [PR99230]
The following testcase results in -fcompare-debug failure.
The problem is the similar like in PR94272
https://gcc.gnu.org/pipermail/gcc-patches/2020-March/542562.html
When genericizing, with -g0 we have just a TREE_SIDE_EFFECTS DO_STMT
in a branch of if, while with -g we have that wrapped into
TREE_SIDE_EFFECTS STATEMENT_LIST containing DEBUG_BEGIN_STMT and that
DO_STMT.
The do loop is empty with 0 condition, so c_genericize_control_stmt
turns it into an empty statement (without TREE_SIDE_EFFECTS).
For -g0 that means that suddenly the if branch doesn't have side effects
and is expanded differently. But with -g we still have TREE_SIDE_EFFECTS
STATEMENT_LIST containing DEBUG_BEGIN_STMT and non-TREE_SIDE_EFFECTS stmt.
The following patch fixes that by detecting this case and removing
TREE_SIDE_EFFECTS.
And, so that we don't duplicate the same code, changes the C++ FE to
just call the c_genericize_control_stmt function that can now handle it.
[PR99680] Check empty constraint before using CONSTRAINT_LEN.
It seems CONSTRAINT_LEN treats constraint '\0' as one having length 1. Therefore we
read after the constraint string. The patch fixes it.
gcc/ChangeLog:
PR rtl-optimization/99680
* lra-constraints.c (skip_contraint_modifiers): Rename to skip_constraint_modifiers.
(process_address_1): Check empty constraint before using
CONSTRAINT_LEN.
Jakub Jelinek [Fri, 19 Mar 2021 21:54:31 +0000 (22:54 +0100)]
c: Fix up -Wunused-but-set-* warnings for _Atomics [PR99588]
As the following testcases show, compared to -D_Atomic= case we have many
-Wunused-but-set-* warning false positives.
When an _Atomic variable/parameter is read, we call mark_exp_read on it in
convert_lvalue_to_rvalue, but build_atomic_assign does not.
For consistency with the non-_Atomic case where we mark_exp_read the lhs
for lhs op= ... but not for lhs = ..., this patch does that too.
But furthermore we need to pattern match the trees emitted by _Atomic store,
so that _Atomic store itself is not marked as being a variable read, but
when the result of the store is used, we mark it.
2021-03-19 Jakub Jelinek <jakub@redhat.com>
PR c/99588
* c-typeck.c (mark_exp_read): Recognize what build_atomic_assign
with modifycode NOP_EXPR produces and mark the _Atomic var as read
if found.
(build_atomic_assign): For modifycode of NOP_EXPR, use COMPOUND_EXPRs
rather than STATEMENT_LIST. Otherwise call mark_exp_read on lhs.
Set TREE_SIDE_EFFECTS on the TARGET_EXPR.
* gcc.dg/Wunused-var-5.c: New test.
* gcc.dg/Wunused-var-6.c: New test.
Jonathan Wakely [Fri, 19 Mar 2021 19:42:18 +0000 (19:42 +0000)]
libstdc++: Add std::is_scoped_enum for C++23
Implement this C++23 feature, as proposed by P1048R1.
This implementation assumes that a C++23 compiler supports concepts
already. I don't see any point in using preprocessor hacks to detect
compilers which define __cplusplus to a post-C++20 value but don't
support concepts yet.
libstdc++-v3/ChangeLog:
* include/std/type_traits (is_scoped_enum): Define.
* include/std/version (__cpp_lib_is_scoped_enum): Define.
* testsuite/20_util/is_scoped_enum/value.cc: New test.
* testsuite/20_util/is_scoped_enum/version.cc: New test.
Thomas Koenig [Fri, 19 Mar 2021 19:49:38 +0000 (20:49 +0100)]
Add size check to vector-matrix matmul.
It turns out the library version is much faster for vector-matrix
multiplications for large sizes than what inlining can produce.
Use size checks for switching between this and inlining for
that case to.
gcc/fortran/ChangeLog:
* frontend-passes.c (inline_limit_check): Add rank_a
argument. If a is rank 1, set the second dimension to 1.
(inline_matmul_assign): Pass rank_a argument to inline_limit_check.
(call_external_blas): Likewise.
gcc/testsuite/ChangeLog:
* gfortran.dg/inline_matmul_6.f90: Adjust count for
_gfortran_matmul.
[PR99663] Don't use unknown constraint for address constraint in process_address_1.
s390x has insns using several alternatives with address constraints. Even
if we don't know at this stage what alternative will be used, we still can say
that is an address constraint. So don't use unknown constraint in this
case when there are multiple constraints or/and alternative.
gcc/ChangeLog:
PR target/99663
* lra-constraints.c (process_address_1): Don't use unknown
constraint for address constraint.
Jakub Jelinek [Fri, 19 Mar 2021 17:36:56 +0000 (18:36 +0100)]
c++: Only reject reinterpret casts from pointers to integers for manifestly_const_eval evaluation [PR99456]
My PR82304/PR95307 fix moved reinterpret cast from pointer to integer
diagnostics from cxx_eval_outermost_constant_expr where it caught
invalid code only at the outermost level down into
cxx_eval_constant_expression.
Unfortunately, it regressed following testcase, we emit worse code
including dynamic initialization of some vars.
While the initializers are not constant expressions due to the
reinterpret_cast in there, there is no reason not to fold them as an
optimization.
I've tried to make this dependent on !ctx->quiet, but that regressed
two further tests, and on ctx->strict, which regressed other tests,
so this patch bases that on manifestly_const_eval.
The new testcase is now optimized as much as it used to be in GCC 10
and the only regression it causes is an extra -Wnarrowing warning
on vla22.C test on invalid code (which the patch adjusts).
2021-03-19 Jakub Jelinek <jakub@redhat.com>
PR c++/99456
* constexpr.c (cxx_eval_constant_expression): For CONVERT_EXPR from
INDIRECT_TYPE_P to ARITHMETIC_TYPE_P, when !ctx->manifestly_const_eval
don't diagnose it, set *non_constant_p nor return t.
* g++.dg/opt/pr99456.C: New test.
* g++.dg/ext/vla22.C: Expect a -Wnarrowing warning for c++11 and
later.
Olivier Hainque [Fri, 19 Mar 2021 15:21:38 +0000 (15:21 +0000)]
target/99660 - missing VX_CPU_PREFIX for vxworksae
This fixes an oversight which causes make all-gcc
to fail for --target=*vxworksae or vxworksmils, a regression
introduced by the recent VxWorks7 related updates.
Both AE and MILS variants resort to a common config/vxworksae.h,
which misses a definition of VX_CPU_PREFIX expected by port
specific headers.
which costs the cost for the load-and-split and the cost of the external splat,
and the one for blending them while in reality it's just a scalar load and
insert.
The compiler (with the cost model disabled) generates
H.J. Lu [Thu, 18 Mar 2021 18:47:46 +0000 (11:47 -0700)]
x86: Issue error for return/argument only with function body
If we never generate function body, we shouldn't issue errors for return
nor argument. Add silent_p to i386 machine_function to avoid issuing
errors for return and argument without function body.
gcc/
PR target/99652
* config/i386/i386-options.c (ix86_init_machine_status): Set
silent_p to true.
* config/i386/i386.c (init_cumulative_args): Set silent_p to
false.
(construct_container): Return early for return and argument
errors if silent_p is true.
* config/i386/i386.h (machine_function): Add silent_p.
Jakub Jelinek [Fri, 19 Mar 2021 12:48:44 +0000 (13:48 +0100)]
arm: Fix mve_vshlq* [PR99593]
As mentioned in the PR, before the r11-6708-gbfab355012ca0f5219da8beb04f2fdaf757d34b7
change v[al]shr<mode>3 expanders were expanding the shifts by register
to gen_ashl<mode>3_{,un}signed which don't support immediate CONST_VECTOR
shift amounts, but now expand to mve_vshlq_<supf><mode> which does.
The testcase ICEs, because the constraint doesn't match the predicate and
because LRA works solely with the constraints, so it can e.g. from REG_EQUAL
propagate there a CONST_VECTOR which matches the constraint but fails the
predicate and only later on other passes will notice the predicate fails
and ICE.
Fixed by adding a constraint that matches the immediate part of the
predicate.
PR target/99593
* config/arm/constraints.md (Ds): New constraint.
* config/arm/vec-common.md (mve_vshlq_<supf><mode>): Use w,Ds
constraint instead of w,Dm.
git://gcc.gnu.org / gcc.git / log