RISC-V/testsuite: Add branched cases for FP cond-move operations

Verify, for Ventana and Zicond targets and the ordered floating-point
conditional-move operations that already work as expected, that
if-conversion does *not* trigger at `-mbranch-cost=2' setting, which
makes original branched code sequences cheaper than their branchless
equivalents if-conversion would emit.  Cover all ordered floating-point
relational operations to make sure no corner case escapes.

gcc/testsuite/
* gcc.target/riscv/movdibfge-ventana.c: New test.
* gcc.target/riscv/movdibfge-zicond.c: New test.
* gcc.target/riscv/movdibfgt-ventana.c: New test.
* gcc.target/riscv/movdibfgt-zicond.c: New test.
* gcc.target/riscv/movdibfle-ventana.c: New test.
* gcc.target/riscv/movdibfle-zicond.c: New test.
* gcc.target/riscv/movdibflt-ventana.c: New test.
* gcc.target/riscv/movdibflt-zicond.c: New test.
* gcc.target/riscv/movdibfne-ventana.c: New test.
* gcc.target/riscv/movdibfne-zicond.c: New test.
* gcc.target/riscv/movsibfge-ventana.c: New test.
* gcc.target/riscv/movsibfge-zicond.c: New test.
* gcc.target/riscv/movsibfgt-ventana.c: New test.
* gcc.target/riscv/movsibfgt-zicond.c: New test.
* gcc.target/riscv/movsibfle-ventana.c: New test.
* gcc.target/riscv/movsibfle-zicond.c: New test.
* gcc.target/riscv/movsibflt-ventana.c: New test.
* gcc.target/riscv/movsibflt-zicond.c: New test.
* gcc.target/riscv/movsibfne-ventana.c: New test.
* gcc.target/riscv/movsibfne-zicond.c: New test.

RISC-V/testsuite: Add branchless cases for integer cond-move operations

Verify, for T-Head, Ventana and Zicond targets and the integer
conditional-move operations that already work as expected, if-conversion
to trigger via `noce_try_cmove' at the respective sufficiently high
`-mbranch-cost=' settings that make branchless code sequences produced
by if-conversion cheaper than their original branched equivalents, and
that extraneous instructions such as SNEZ, etc. are not present in
output.  Cover all integer relational operations to make sure no corner
case escapes.

gcc/testsuite/
* gcc.target/riscv/movdieq-thead.c: New test.
* gcc.target/riscv/movdige-ventana.c: New test.
* gcc.target/riscv/movdige-zicond.c: New test.
* gcc.target/riscv/movdigeu-ventana.c: New test.
* gcc.target/riscv/movdigeu-zicond.c: New test.
* gcc.target/riscv/movdigt-ventana.c: New test.
* gcc.target/riscv/movdigt-zicond.c: New test.
* gcc.target/riscv/movdile-ventana.c: New test.
* gcc.target/riscv/movdile-zicond.c: New test.
* gcc.target/riscv/movdileu-ventana.c: New test.
* gcc.target/riscv/movdileu-zicond.c: New test.
* gcc.target/riscv/movdilt-ventana.c: New test.
* gcc.target/riscv/movdilt-zicond.c: New test.
* gcc.target/riscv/movdine-thead.c: New test.
* gcc.target/riscv/movsieq-thead.c: New test.
* gcc.target/riscv/movsige-ventana.c: New test.
* gcc.target/riscv/movsige-zicond.c: New test.
* gcc.target/riscv/movsigeu-ventana.c: New test.
* gcc.target/riscv/movsigeu-zicond.c: New test.
* gcc.target/riscv/movsigt-ventana.c: New test.
* gcc.target/riscv/movsigt-zicond.c: New test.
* gcc.target/riscv/movsile-ventana.c: New test.
* gcc.target/riscv/movsile-zicond.c: New test.
* gcc.target/riscv/movsileu-ventana.c: New test.
* gcc.target/riscv/movsileu-zicond.c: New test.
* gcc.target/riscv/movsilt-ventana.c: New test.
* gcc.target/riscv/movsilt-zicond.c: New test.
* gcc.target/riscv/movsine-thead.c: New test.

RISC-V/testsuite: Add branched cases for integer cond-move operations

Verify, for T-Head, Ventana and Zicond targets and the integer
conditional-move operations that already work as expected, that
if-conversion does *not* trigger at the respective sufficiently low
`-mbranch-cost=' settings that make original branched code sequences
cheaper than their branchless equivalents if-conversion would emit.
Cover all integer relational operations to make sure no corner case
escapes.

The reason to XFAIL movdibne-thead.c and movsibne-thead.c is the
branchless T-Head sequence:

sub a1,a0,a1
th.mveqz a2,a3,a1
mv a0,a2
ret

produced rather than its original branched counterpart:

beq a0,a1,.L3
mv a0,a2
ret
.L3:
mv a0,a3
ret

at `-mbranch-cost=1', even though under this setting the latter sequence
is obviously cheaper performance-wise.  This is because the final move
instruction in the branchless sequence is not counted towards its cost
and consequently the cost of both sequences works out at 8 each, making
if-conversion prefer the branchless variant.  Use the XFAIL mark to keep
track of these cases for future consideration.

gcc/testsuite/
* gcc.target/riscv/movdibeq-thead.c: New test.
* gcc.target/riscv/movdibge-ventana.c: New test.
* gcc.target/riscv/movdibge-zicond.c: New test.
* gcc.target/riscv/movdibgeu-ventana.c: New test.
* gcc.target/riscv/movdibgeu-zicond.c: New test.
* gcc.target/riscv/movdibgt-ventana.c: New test.
* gcc.target/riscv/movdibgt-zicond.c: New test.
* gcc.target/riscv/movdible-ventana.c: New test.
* gcc.target/riscv/movdible-zicond.c: New test.
* gcc.target/riscv/movdibleu-ventana.c: New test.
* gcc.target/riscv/movdibleu-zicond.c: New test.
* gcc.target/riscv/movdiblt-ventana.c: New test.
* gcc.target/riscv/movdiblt-zicond.c: New test.
* gcc.target/riscv/movdibne-thead.c: New test.
* gcc.target/riscv/movsibeq-thead.c: New test.
* gcc.target/riscv/movsibge-ventana.c: New test.
* gcc.target/riscv/movsibge-zicond.c: New test.
* gcc.target/riscv/movsibgeu-ventana.c: New test.
* gcc.target/riscv/movsibgeu-zicond.c: New test.
* gcc.target/riscv/movsibgt-ventana.c: New test.
* gcc.target/riscv/movsibgt-zicond.c: New test.
* gcc.target/riscv/movsible-ventana.c: New test.
* gcc.target/riscv/movsible-zicond.c: New test.
* gcc.target/riscv/movsibleu-ventana.c: New test.
* gcc.target/riscv/movsibleu-zicond.c: New test.
* gcc.target/riscv/movsiblt-ventana.c: New test.
* gcc.target/riscv/movsiblt-zicond.c: New test.
* gcc.target/riscv/movsibne-thead.c: New test.

RISC-V: Rework branch costing model for if-conversion

The generic branch costing model for if-conversion assumes a fixed cost
of COSTS_N_INSNS (2) for a conditional branch, and that one half of that
cost comes from a preceding condition-set instruction, such as with
MODE_CC targets, and then the other half of that cost is for the actual
branch instruction.  This is hardcoded for `if_info.original_cost' in
`noce_find_if_block' and regardless of the cost set for branches via
BRANCH_COST.

Then `default_max_noce_ifcvt_seq_cost' instructs if-conversion to prefer
a branchless sequence as costly as high as triple the BRANCH_COST value
set.  This is apparently to make up for the inability to accurately
guess the branch penalty.

Consequently for the BRANCH_COST of 3 we commonly set for tuning,
if-conversion will consider branchless sequences costing 3 * 3 - 2 = 7
instruction units more than a corresponding branch sequence.  For the
BRANCH_COST of 4 such as with `sifive-7-series' tuning this is even
worse, at 3 * 4 - 2 = 10.  Effectively it means a branchless sequence
will always be chosen if available, even a very inefficient one.

Rework the branch costing model to better match our architecture,
observing in particular that we have no preparatory instructions for
branches so that the cost of a branch is naked BRANCH_COST plus any
extra overhead the processing of a branch's source RTX might incur.

Provide TARGET_INSN_COST and TARGET_MAX_NOCE_IFCVT_SEQ_COST handlers
than that return suitable cost based on BRANCH_COST.  The latter hook
usually returns a value that is lower than the cost of the corresponding
branched sequence.  This is because we don't really want to produce a
branchless sequence that is more expensive than the original branched
sequence.  If this turns out too conservative for some corner case, then
this choice might be revisited.

Then we don't want to fiddle with `noce_find_if_block' without a lot of
cross-target verification, so add TARGET_NOCE_CONVERSION_PROFITABLE_P
defined such that it subtracts the fixed COSTS_N_INSNS (2) cost from the
cost of the original branched sequence supplied and instead adds actual
branch cost calculated from the conditional branch instruction used.  It
is then further tweaked according to simple analysis of the replacement
branchless sequence produced so as to cancel the cost of an extraneous
zero extend operation produced by `noce_try_store_flag_mask' as observed
with gcc/testsuite/gcc.target/riscv/pr105314.c.

Tweak the testsuite accordingly and set `-mbranch-cost=' explicitly for
the relevant cases so that the expected if-conversion transformation is
made regardless of the default BRANCH_COST value of tuning in effect.
Some of these settings will be lowered later on as deficiencies in
branchless sequence generation have been fixed that lower their cost
calculated by if-conversion.

gcc/
* config/riscv/riscv.cc (riscv_insn_cost): New function.
(riscv_max_noce_ifcvt_seq_cost): Likewise.
(riscv_noce_conversion_profitable_p): Likewise.
(TARGET_INSN_COST): New macro.
(TARGET_MAX_NOCE_IFCVT_SEQ_COST): New macro.
(TARGET_NOCE_CONVERSION_PROFITABLE_P): New macro.

gcc/testsuite/
* gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_imm_imm.c:
Explicitly set the branch cost.
* gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_imm_reg.c:
Likewise.
* gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_reg_reg.c:
Likewise.
* gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_imm_imm.c:
Likewise.
* gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_imm_reg.c:
Likewise.
* gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_reg_reg.c:
Likewise.

RISC-V: Simplify EQ vs NE selection in `riscv_expand_conditional_move'

Just choose between EQ and NE at `gen_rtx_fmt_ee' invocation, removing
an extraneous variable only referred once and improving code clarity.

gcc/
* config/riscv/riscv.cc (riscv_expand_conditional_move): Remove
extraneous variable for EQ vs NE operation selection.

RISC-V: Use `nullptr' in `riscv_expand_conditional_move'

Use `nullptr' for consistency rather than 0 to initialize `invert_ptr'.

gcc/
* config/riscv/riscv.cc (riscv_expand_conditional_move): Use
`nullptr' rather than 0 to initialize a pointer.

RISC-V: Avoid repeated GET_MODE calls in `riscv_expand_conditional_move'

Use `mode0' and `mode1' shorthands respectively for `GET_MODE (op0)' and
`GET_MODE (op1)' to improve code readability.

gcc/
* config/riscv/riscv.cc (riscv_expand_conditional_move): Use
`mode0' and `mode1' for `GET_MODE (op0)' and `GET_MODE (op1)'.

RISC-V: Fix `mode' usage in `riscv_expand_conditional_move'

In `riscv_expand_conditional_move' `mode' is initialized right away from
`GET_MODE (dest)', so remove needless references that refrain from using
the local variable.

gcc/
* config/riscv/riscv.cc (riscv_expand_conditional_move): Use
`mode' for `GET_MODE (dest)' throughout.

RISC-V: Sanitise NEED_EQ_NE_P case with `riscv_emit_int_compare'

For the NEED_EQ_NE_P `riscv_emit_int_compare' is documented to only emit
EQ or NE comparisons against zero, however it does not catch incorrect
use where a non-equality comparison has been requested and falls through
to the general case then.  Add a safety guard to catch such a case then.

Arguably the NEED_EQ_NE_P case would best be moved into a function of
its own, but let's leave it for a separate cleanup.

gcc/
* config/riscv/riscv.cc (riscv_emit_int_compare): Bail out if
NEED_EQ_NE_P but the comparison is neither EQ nor NE.

RISC-V: Reorder comment on SFB patterns

Our `mov<mode>cc' expander is no longer specific to short forward branch
targets, so move its associated comment accordingly.

gcc/
* config/riscv/riscv.md (mov<mode>cc): Move comment on SFB
patterns over to...
(*mov<GPR:mode><X:mode>cc): ... here.

RISC-V/testsuite: Add cases for integer SFB cond-move operations

Verify, for short forward branch targets and the conditional-move
operations that already work as expected, that if-conversion triggers
via `noce_try_cmove' already at `-mbranch-cost=1' and that extraneous
instructions such as SNEZ, etc. are not present in output.  Cover all
integer relational operations to make sure no corner case escapes.

gcc/testsuite/
* gcc.target/riscv/movdieq-sfb.c: New test.
* gcc.target/riscv/movdige-sfb.c: New test.
* gcc.target/riscv/movdigeu-sfb.c: New test.
* gcc.target/riscv/movdigt-sfb.c: New test.
* gcc.target/riscv/movdigtu-sfb.c: New test.
* gcc.target/riscv/movdile-sfb.c: New test.
* gcc.target/riscv/movdileu-sfb.c: New test.
* gcc.target/riscv/movdilt-sfb.c: New test.
* gcc.target/riscv/movdiltu-sfb.c: New test.
* gcc.target/riscv/movdine-sfb.c: New test.
* gcc.target/riscv/movsieq-sfb.c: New test.
* gcc.target/riscv/movsige-sfb.c: New test.
* gcc.target/riscv/movsigeu-sfb.c: New test.
* gcc.target/riscv/movsigt-sfb.c: New test.
* gcc.target/riscv/movsigtu-sfb.c: New test.
* gcc.target/riscv/movsile-sfb.c: New test.
* gcc.target/riscv/movsileu-sfb.c: New test.
* gcc.target/riscv/movsilt-sfb.c: New test.
* gcc.target/riscv/movsiltu-sfb.c: New test.
* gcc.target/riscv/movsine-sfb.c: New test.

testsuite: Add cases for conditional-move and conditional-add operations

Add generic execution tests for expressions that are expected to expand
to conditional-move and conditional-add operations where supported.  To
ensure no corner case escapes all relational operators are extensively
covered for integer comparisons and all ordered operators are covered
for floating-point comparisons.  Unordered operators are not covered at
this point as they'd require a different input data set.

gcc/testsuite/
* gcc.dg/torture/addieq.c: New test.
* gcc.dg/torture/addifeq.c: New test.
* gcc.dg/torture/addifge.c: New test.
* gcc.dg/torture/addifgt.c: New test.
* gcc.dg/torture/addifle.c: New test.
* gcc.dg/torture/addiflt.c: New test.
* gcc.dg/torture/addifne.c: New test.
* gcc.dg/torture/addige.c: New test.
* gcc.dg/torture/addigeu.c: New test.
* gcc.dg/torture/addigt.c: New test.
* gcc.dg/torture/addigtu.c: New test.
* gcc.dg/torture/addile.c: New test.
* gcc.dg/torture/addileu.c: New test.
* gcc.dg/torture/addilt.c: New test.
* gcc.dg/torture/addiltu.c: New test.
* gcc.dg/torture/addine.c: New test.
* gcc.dg/torture/addleq.c: New test.
* gcc.dg/torture/addlfeq.c: New test.
* gcc.dg/torture/addlfge.c: New test.
* gcc.dg/torture/addlfgt.c: New test.
* gcc.dg/torture/addlfle.c: New test.
* gcc.dg/torture/addlflt.c: New test.
* gcc.dg/torture/addlfne.c: New test.
* gcc.dg/torture/addlge.c: New test.
* gcc.dg/torture/addlgeu.c: New test.
* gcc.dg/torture/addlgt.c: New test.
* gcc.dg/torture/addlgtu.c: New test.
* gcc.dg/torture/addlle.c: New test.
* gcc.dg/torture/addlleu.c: New test.
* gcc.dg/torture/addllt.c: New test.
* gcc.dg/torture/addlltu.c: New test.
* gcc.dg/torture/addlne.c: New test.
* gcc.dg/torture/movieq.c: New test.
* gcc.dg/torture/movifeq.c: New test.
* gcc.dg/torture/movifge.c: New test.
* gcc.dg/torture/movifgt.c: New test.
* gcc.dg/torture/movifle.c: New test.
* gcc.dg/torture/moviflt.c: New test.
* gcc.dg/torture/movifne.c: New test.
* gcc.dg/torture/movige.c: New test.
* gcc.dg/torture/movigeu.c: New test.
* gcc.dg/torture/movigt.c: New test.
* gcc.dg/torture/movigtu.c: New test.
* gcc.dg/torture/movile.c: New test.
* gcc.dg/torture/movileu.c: New test.
* gcc.dg/torture/movilt.c: New test.
* gcc.dg/torture/moviltu.c: New test.
* gcc.dg/torture/movine.c: New test.
* gcc.dg/torture/movleq.c: New test.
* gcc.dg/torture/movlfeq.c: New test.
* gcc.dg/torture/movlfge.c: New test.
* gcc.dg/torture/movlfgt.c: New test.
* gcc.dg/torture/movlfle.c: New test.
* gcc.dg/torture/movlflt.c: New test.
* gcc.dg/torture/movlfne.c: New test.
* gcc.dg/torture/movlge.c: New test.
* gcc.dg/torture/movlgeu.c: New test.
* gcc.dg/torture/movlgt.c: New test.
* gcc.dg/torture/movlgtu.c: New test.
* gcc.dg/torture/movlle.c: New test.
* gcc.dg/torture/movlleu.c: New test.
* gcc.dg/torture/movllt.c: New test.
* gcc.dg/torture/movlltu.c: New test.
* gcc.dg/torture/movlne.c: New test.

Daily bump.

Fix 'gcc.dg/tree-ssa/return-value-range-1.c' for 'char' defaulting to 'unsigned'

... added in recent commit 53ba8d669550d3a1f809048428b97ca607f95cf5
"inter-procedural value range propagation", fixed in
commit 878a860cae78146d98d7a21612f0bcec0930a9c2
"Fix 'gcc.dg/tree-ssa/return-value-range-1.c'".

gcc/testsuite/
* gcc.dg/tree-ssa/return-value-range-1.c: Fix.

vect: Allow reduc_index != 1 for COND_OPs.

In PR112406 Tamar found another problem with COND_OP reductions.
I wrongly assumed that the reduction variable will always remain in
operand 1, just as we create the COND_OP in ifcvt.  But of course,
addition being commutative, we are free to swap operand 1 and 2 and we
end up with e.g.

 _ifc__60 = .COND_ADD (_2, _6, MADPictureC1_lsm.10_25, MADPictureC1_lsm.10_25);

which does not pass the asserts I put in place.

This patch removes this restriction and allows the reduction index to be
2 as well.

gcc/ChangeLog:

PR middle-end/112406

* tree-vect-loop.cc (vectorize_fold_left_reduction): Allow
reduction index != 1.
(vect_transform_reduction): Handle reduction index != 1.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/pr112406-2.c: New test.

RISC-V: testsuite: Fix popcount test.

Due to Jakub's recent middle-end changes we now vectorize some more
popcount instances.  This patch just adjusts the dump check.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/unop/popcount.c: Adjust check.
* lib/target-supports.exp: Add riscv_zbb.

RISC-V: testsuite: Add rv64 requirement for bug-9 and bug-14.

This adds an effective target requirement to compile the tests.  Since
we disabled 64-bit indices on rv32 targets those tests should be
unsupported on rv32.

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/bug-14.C: Add
dg-require-effective-target rv64.
* g++.target/riscv/rvv/base/bug-9.C: Ditto.

RISC-V: testsuite: Do not set default arch for RVV.

This removes setting of the default arch and abi in the testsuite.  We
should directly use what the target provides.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/rvv.exp:  Remove -march and -mabi from
default CFLAGS.

sanitizer: Fix build on SPARC/Solaris with Solaris as [PR112562]

Solaris as apparently doesn't accept %function and requires @function
instead.

This cherry-picks upstream commit.

2023-11-21  Jakub Jelinek  <jakub@redhat.com>

PR sanitizer/112562
* sanitizer_common/sanitizer_asm.h: Cherry-pick llvm-project revision
a855a16a02e76a0f4192c038bb64f3773947a2f7.
* interception/interception.h: Likewise.

gfortran: Rely on dg-do-what-default to avoid running pr85853.f90, pr107254.f90 and vect-alias-check-1.F90 on non-vector targets

Testcases in gfortran.dg/vect/vect.exp rely on
check_vect_support_and_set_flags to set dg-do-what-default and avoid
running vector tests on non-vector targets. The three testcases in this
patch overwrite the default with dg-do run which causes issues
for non-vector targets.

Removing the dg-do run directive resolves this issue for non-vector
targets (while still running the tests on vector targets).

gcc/testsuite/ChangeLog:

* gfortran.dg/vect/pr107254.f90: Remove dg-do run directive.
* gfortran.dg/vect/pr85853.f90: Ditto.
* gfortran.dg/vect/vect-alias-check-1.F90: Ditto.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>

libstdc++: Do not declare strtok for C++26 freestanding (P2937R0)

This was recently approved for C++26.

We should define the __cpp_lib_freestanding_cstring macro in <string.h>
as well as <cstring>, but we do not currently install our own <string.h>
for most targets.

libstdc++-v3/ChangeLog:

* include/bits/version.def (freestanding_cstring): Add.
* include/bits/version.h: Regenerate.
* include/c_compatibility/string.h (strtok): Do not declare for
C++26 freestanding.
* include/c_global/cstring (strtok): Likewise.
* testsuite/21_strings/headers/cstring/version.cc: New test.

libstdc++: Add freestanding feature test macros (P2407R5)

This C++26 change makes several classes "partially freestanding", but we
already fully supported them in freestanding mode. All we need to do is
define the new feature test macros and add tests for them.

libstdc++-v3/ChangeLog:

* include/bits/version.def (freestanding_algorithm)
(freestanding_array, freestanding_optional)
(freestanding_string_view, freestanding_variant): Add.
* include/bits/version.h: Regenerate.
* include/std/algorithm (__glibcxx_want_freestanding_algorithm):
Define.
* include/std/array (__glibcxx_want_freestanding_array):
Define.
* include/std/optional (__glibcxx_want_freestanding_optional):
Define.
* include/std/string_view
(__glibcxx_want_freestanding_string_view): Define.
* include/std/variant (__glibcxx_want_freestanding_variant):
Define.
* testsuite/20_util/optional/version.cc: Add checks for
__cpp_lib_freestanding_optional.
* testsuite/20_util/variant/version.cc: Add checks for
__cpp_lib_freestanding_variant.
* testsuite/23_containers/array/tuple_interface/get_neg.cc:
Adjust dg-error line numbers.
* testsuite/21_strings/basic_string_view/requirements/version.cc:
New test.
* testsuite/23_containers/array/requirements/version.cc: New
test.
* testsuite/25_algorithms/fill_n/requirements/version.cc: New
test.
* testsuite/25_algorithms/swap_ranges/requirements/version.cc:
New test.

libstdc++: Add std::span::at for C++26 (P2821R5)

Also define the new feature test macros from P2833R2, indicating that
std::span and std::expected are supported for freestanding mode.

libstdc++-v3/ChangeLog:

* include/bits/version.def (freestanding_expected): New macro.
(span): Add C++26 value.
* include/bits/version.h: Regenerate.
* include/std/expected (__glibcxx_want_freestanding_expected):
Define.
* include/std/span (span::at): New member function.
* testsuite/20_util/expected/version.cc: Add checks for
__cpp_lib_freestanding_expected.
* testsuite/23_containers/span/2.cc: Moved to...
* testsuite/23_containers/span/version.cc: ...here. Add checks
for __cpp_lib_span in <span> as well as in <version>.
* testsuite/23_containers/span/1.cc: Removed.
* testsuite/23_containers/span/at.cc: New test.

libstdc++: Fix std::tr2::dynamic_bitset support for alternate characters

libstdc++-v3/ChangeLog:

* include/tr2/dynamic_bitset (dynamic_bitset): Pass zero and one
characters to _M_copy_from_string.
* testsuite/tr2/dynamic_bitset/string.cc: New test.

libstdc++: Remove outdated references to buildstat.html

The buildstat.html pages have not existed since gcc-8 so remove
referencs to them in the libstdc++ manual.

libstdc++-v3/ChangeLog:

* doc/html/*: Regenerate.
* doc/xml/faq.xml: Remove reference to buildstat.html pages.
* doc/xml/manual/test.xml: Likewise

Add an aligned_register_operand predicate

This patch adds a target-independent aligned_register_operand
predicate, for use with register constraints that use filters
to impose an alignment.  The definition deliberately jetisons
some of the historical baggage in general_operand.

gcc/
* common.md (aligned_register_operand): New predicate.

ira: Handle register filters

This patch makes IRA apply register filters when picking hard registers.
All the new code should be optimised away on targets that don't use
register filters.  On targets that do use them, the new register_filters
bitfield is expected to be only a handful of bits.

Information about register filters is recorded in process_bb_node_lives.
The information isn't really related to liveness, but it's a convenient
point because (a) we've already built the allocno structures and
(b) we've already extracted the insn and preprocessed the constraints.

gcc/
* ira-int.h (ira_allocno): Add a register_filters field.
(ALLOCNO_REGISTER_FILTERS): New macro.
(ALLOCNO_SET_REGISTER_FILTERS): Likewise.
* ira-build.cc (ira_create_allocno): Initialize register_filters.
(create_cap_allocno): Propagate register_filters.
(propagate_allocno_info): Likewise.
(propagate_some_info_from_allocno): Likewise.
* ira-lives.cc (process_register_constraint_filters): New function.
(process_bb_node_lives): Use it to record register filter
information.
* ira-color.cc (assign_hard_reg): Check register filters.
(improve_allocation, fast_allocation): Likewise.

lra: Handle register filters

This patch makes LRA apply register filters.  This plus the recog
change is enough for correct code generation, but a follow-on IRA
patch improves the allocation.

All the new code should be optimised away on targets that don't
use register filters.  That's because get_register_filter just
wraps "return nullptr" on those targets.

gcc/
* lra-constraints.cc (process_alt_operands): Check register filters.

recog: Handle register filters

The main (but simplest) part of this patch makes constrain_operands
take register filters into account.

The rest of the patch adds register filter information to
operand_alternative.  Generally, if two register constraints
have different register filters, it's better if they're in separate
alternatives.  However, the syntax doesn't enforce that, and we can't
assert it due to inline asms.  So it's a choice between (a) adding
code to enforce consistent filters or (b) dealing with mixes of filters
in a conservatively correct way (in the sense of not allowing invalid
operands).  The latter seems much easier.

The patch therefore adds a mask of the filters that apply
to at least one constraint in a given operand alternative.
A register is OK if it passes all of the filters in the mask.

gcc/
* recog.h (operand_alternative): Add a register_filters field.
(alternative_register_filters): New function.
* recog.cc (preprocess_constraints): Calculate the filters field.
(constrain_operands): Check register filters.

Add register filter operand to define_register_constraint

The main way of enforcing registers to be aligned is through
HARD_REGNO_MODE_OK.  But this is a global property that applies
to all operands.  A given (regno, mode) pair is either globally
valid or globally invalid.

This patch instead adds a way of specifying that individual operands
must be aligned.  More generally, it allows constraints to specify
a C++ condition that the operand's REGNO must satisfy.  The condition
must be invariant for a given set of target options, so that it can
be precomputed and cached as a HARD_REG_SET.

This information will be used in very compile-time-sensitive
parts of the compiler.  A lot of the complication is in allowing
the information to be stored and tested without much memory cost,
and without impacting targets that don't use the feature.

Specifically:

- Constraints are encouraged to test the absolute REGNO rather than
  an offset from the start of the containing class.  For example,
  all constraints for even registers should use the same condition,
  such as "regno % 2 == 0".  This requires the classes to start at
  even register boundaries, but that's already an implicit
  requirement due to things like the ira-costs.cc code that begins:

      /* Some targets allow pseudos to be allocated to unaligned sequences
 of hard registers.  However, selecting an unaligned sequence can
 unnecessarily restrict later allocations.  So increase the cost of
 unaligned hard regs to encourage the use of aligned hard regs.  */

- Each unique condition is given a "filter identifier".

- The total number of filters is given by NUM_REGISTER_FILTERS,
  defined automatically in insn-config.h.  Structures can therefore use
  a bitfield of NUM_REGISTER_FILTERS to represent a mask of filters.

- There is a new target global, target_constraints, that caches the
  HARD_REG_SET for each filter.

- There is a function for looking up the HARD_REG_SET filter for a given
  constraint and one for looking up the filter id.  Both simply return
  a constant on targets that don't use the feature.

- There are functions for testing a register against a specific filter,
  or against a mask of filters.

This patch just adds the information.  Later ones make use of it.

gcc/
* rtl.def (DEFINE_REGISTER_CONSTRAINT): Add an optional filter
operand.
* doc/md.texi (define_register_constraint): Document it.
* doc/tm.texi.in: Reference it in discussion about aligned registers.
* doc/tm.texi: Regenerate.
* gensupport.h (register_filters, get_register_filter_id): Declare.
* gensupport.cc (register_filter_map, register_filters): New variables.
(get_register_filter_id): New function.
(process_define_register_constraint): Likewise.
(process_rtx): Pass define_register_constraints to
process_define_register_constraint.
* genconfig.cc (main): Emit a definition of NUM_REGISTER_FILTERS.
* genpreds.cc (constraint_data): Add a filter field.
(add_constraint): Update accordingly.
(process_define_register_constraint): Pass the filter operand.
(write_init_reg_class_start_regs): New function.
(write_get_register_filter): Likewise.
(write_get_register_filter_id): Likewise.
(write_tm_preds_h): Write a definition of target_constraints,
plus helpers to test its contents.  Write the get_register_filter*
functions.
(write_insn_preds_c): Write init_reg_class_start_regs.
* reginfo.cc (init_reg_class_start_regs): Declare.
(init_reg_sets): Call it.
* target-globals.h (this_target_constraints): Declare.
(target_globals): Add a constraints field.
(restore_target_globals): Update accordingly.
* target-globals.cc: Include tm_p.h.
(default_target_globals): Initialize the constraints field.
(save_target_globals): Handle the constraints field.
(target_globals::~target_globals): Likewise.

tree-optimization/112623 - forwprop VEC_PACK_TRUNC generation

For vec_pack_trunc patterns there can be an ambiguity for the
source mode for BFmode vs HFmode.  The vectorizer checks
the insns operand mode for this, the following makes forwprop
do the same.  That of course doesn't help if the target supports
both conversions.

PR tree-optimization/112623
* tree-ssa-forwprop.cc (simplify_vector_constructor):
Check the source mode of the insn for vector pack/unpacks.

* gcc.target/i386/pr112623.c: New testcase.

Move VF based dependence check

The following moves the check whether the maximum vectorization
factor determined by data dependence analysis is in conflict with
the chosen vectorization factor to after the point where we applied
both the SLP and the unrolling adjustment to the vectorization
factor.  We check the latter before applying unrolling, but the
SLP adjustment can result in both missed optimization and wrong-code.

* tree-vect-loop.cc (vect_analyze_loop_2): Move check
of VF against max_vf until VF is final.

optimize std::vector::push_back

this patch speeds up the push_back at -O3 significantly by making the
reallocation to be inlined by default.  _M_realloc_insert is general
insertion that takes iterator pointing to location where the value
should be inserted.  As such it contains code to move other entries around
that is quite large.

Since appending to the end of array is common operation, I think we should
have specialized code for that.  Sadly it is really hard to work out this
from IPA passes, since we basically care whether the iterator points to
the same place as the end pointer, which are both passed by reference.
This is inter-procedural value numbering that is quite out of reach.

I also added extra check making it clear that the new length of the vector
is non-zero.  This saves extra conditionals.  Again it is quite hard case
since _M_check_len seem to be able to return 0 if its parameter is 0.
This never happens here, but we are not able to propagate this early nor
at IPA stage.

libstdc++-v3/ChangeLog:

PR libstdc++/110287
PR middle-end/109811
PR middle-end/109849
* include/bits/stl_vector.h (_M_realloc_append): New member function.
(push_back): Use it.
* include/bits/vector.tcc: (emplace_back): Use it.
(_M_realloc_insert): Let compiler know that new vector size is non-zero.
(_M_realloc_append): New member function.

d: Merge upstream dmd ff57fec515, druntime ff57fec515, phobos 17bafda79.

D front-end changes:

    - Import dmd v2.106.0-rc.1.
    - New'ing multi-dimensional arrays are now are converted to a single
      template call `_d_newarraymTX'.

D runtime changes:

    - Import druntime v2.106.0-rc.1.

Phobos changes:

    - Import phobos v2.106.0-rc.1.

gcc/d/ChangeLog:

* dmd/MERGE: Merge upstream dmd ff57fec515.
* dmd/VERSION: Bump version to v2.106.0-rc.1.
* expr.cc (ExprVisitor::visit (CatAssignExp *)): Update for new
front-end interface.
(ExprVisitor::visit (NewExp *)): Likewise.
* runtime.def (NEWARRAYMTX): Remove.
(NEWARRAYMITX): Remove.

libphobos/ChangeLog:

* libdruntime/MERGE: Merge upstream druntime ff57fec515.
* src/MERGE: Merge upstream phobos 17bafda79.

gcc/testsuite/ChangeLog:

* gdc.dg/asm1.d: Adjust expected diagnostic.

RISC-V: Disallow COSNT_VECTOR for DI on RV32

This bug is exposed when testing on zvl512b RV32 system.

The rootcause is RA reload DI CONST_VECTOR into vmv.v.x then it ICE.

So disallow DI CONST_VECTOR on RV32.

PR target/112598

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_const_insns): Disallow DI CONST_VECTOR on RV32.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr112598-1.c: New test.

d: Merge upstream dmd 65a3da148c, phobos fc06c514a.

D front-end changes:

    - Import latest bug fixes from dmd v2.106.0-beta.1.

Phobos changes:

    - Import latest bug fixes from phobos v2.106.0-beta.1.
    - `std.range.primitives.isForwardRange' now takes an optional
      element type.

gcc/d/ChangeLog:

* dmd/MERGE: Merge upstream dmd 65a3da148c.

libphobos/ChangeLog:

* src/MERGE: Merge upstream phobos fc06c514a.

AArch64: only emit mismatch error when features would be disabled.

At the moment we emit a warning whenever you specify both -march and -mcpu
and the architecture of them differ.  The idea originally was that the user may
not be aware of this change.

However this has a few problems:

1.  Architecture revisions is not an observable part of the architecture,
    extensions are.  Starting with GCC 14 we have therefore relaxed the rule that
    all extensions can be enabled at any architecture level.  Therefore it's
    incorrect, or at least not useful to keep the check on architecture.

2.  It's problematic in Makefiles and other build systems, where you want to
    for certain files enable CPU specific builds.  i.e. you may be by default
    building for -march=armv8-a but for some file for -mcpu=neoverse-n1.  Since
    there's no easy way to remove the earlier options we end up warning and
    there's no way to disable just this warning.  Build systems compiling with
    -Werror face an issue in this case that compiling with GCC is needlessly
    hard.

3. It doesn't actually warn for cases that may lead to issues, so e.g.
   -march=armv8.2-a+sve -mcpu=neoverse-n1 does not give a warning that SVE would
   be disabled.

For this reason I have one of two proposals:

1.  Just remove this warning all together.

2.  Rework the warning based on extensions and only warn when features would be
    disabled by the presence of the -mcpu.  This is the approach this patch has
    taken.

As examples:

> aarch64-none-linux-gnu-gcc -march=armv8.2-a+sve -mcpu=neoverse-n1
cc1: warning: switch ‘-mcpu=neoverse-n1’ conflicts with ‘-march=armv8.2-a+sve’ switch and resulted in options +crc+sve+norcpc+nodotprod being added                                                                                                                                        .arch armv8.2-a+crc+sve

> aarch64-none-linux-gnu-gcc -march=armv8.2-a -mcpu=neoverse-n1
> aarch64-none-linux-gnu-gcc -march=armv8.2-a+dotprod -mcpu=neoverse-n1
> aarch64-none-linux-gnu-gcc -march=armv8.2-a+dotprod -mcpu=neoverse-n2
<no warning>

The one remaining issue here is that if both -march and -mcpu are specified we
pick the -march.  This is not particularly obvious and for the use case to be
more useful I think it makes sense to pick the CPU's arch?

I did not make that change in the patch as it changes semantics.

Note that I can't write a test for this because dg-warning expects warnings to
be at a particular line and doesn't support warnings at the "global" level.

gcc/ChangeLog:

* config/aarch64/aarch64.cc (aarch64_override_options): Rework warnings.

AArch64: Add new generic-armv9-a CPU and make it the default for Armv9

This patch adds a new generic scheduling model "generic-armv9-a" and makes it
the default for all Armv9 architectures.

-mcpu=generic and -mtune=generic is kept around for those that really want the
previous cost model.

gcc/ChangeLog:

PR target/111370
* config/aarch64/aarch64-arches.def (armv9-a, armv9.1-a, armv9.2-a,
armv9.3-a): Update to generic-armv9-a.
* config/aarch64/aarch64-cores.def (generic-armv9-a): New.
* config/aarch64/aarch64-tune.md: Regenerate.
* config/aarch64/aarch64.cc: Include generic_armv9_a.h.
* config/aarch64/tuning_models/generic_armv9_a.h: New file.

AArch64: Add new generic-armv8-a CPU and make it the default.

This patch adds a new generic scheduling model "generic-armv8-a" and makes it
the default for all Armv8 architectures.

-mcpu=generic and -mtune=generic is kept around for those that really want the
previous cost model.

This shows on SPECCPU 2017 the following:

generic:  SPECINT 1.0% improvement in geomean, SPECFP -0.6%.  The SPECFP is due
          to fotonik3d_r where we vectorize an FP calculation that only ever
  needs one lane of the result.  This I believe is a generic costing bug
  but at the moment we can't change costs of FP and INT independently.
  So will defer updating that cost to stage3 after Richard's other
  costing updates land.

generic SVE: SPECINT 1.1% improvement in geomean, SPECFP 0.7% improvement.

gcc/ChangeLog:

PR target/111370
* config/aarch64/aarch64-arches.def (armv8-9, armv8-a, armv8.1-a,
armv8.2-a, armv8.3-a, armv8.4-a, armv8.5-a, armv8.6-a, armv8.7-a,
armv8.8-a): Update to generic_armv8_a.
* config/aarch64/aarch64-cores.def (generic-armv8-a): New.
* config/aarch64/aarch64-tune.md: Regenerate.
* config/aarch64/aarch64.cc: Include generic_armv8_a.h
* config/aarch64/aarch64.h (TARGET_CPU_DEFAULT): Change to
TARGET_CPU_generic_armv8_a.
* config/aarch64/tuning_models/generic_armv8_a.h: New file.

gcc/testsuite/ChangeLog:

PR target/111370
* gcc.target/aarch64/sve/cond_asrd_1.c: Updated.
* gcc.target/aarch64/sve/cond_cnot_4.c: Likewise.
* gcc.target/aarch64/sve/cond_unary_5.c: Likewise.
* gcc.target/aarch64/sve/cond_uxt_5.c: Likewise.
* gcc.target/aarch64/target_attr_13.c: Likewise.
* gcc.target/aarch64/target_attr_15.c: Likewise.

AArch64: Remove special handling of generic cpu.

In anticipation of adding new generic turning values this removes the hardcoding
of the "generic" CPU and instead just specifies it as a normal CPU.

No change in behavior is expected.

gcc/ChangeLog:

PR target/111370
* config/aarch64/aarch64-cores.def: Add generic.
* config/aarch64/aarch64-opts.h (enum aarch64_proc): Remove generic.
* config/aarch64/aarch64-tune.md: Regenerate
* config/aarch64/aarch64.cc (all_cores): Remove generic
* config/aarch64/aarch64.h (enum target_cpus): Remove
TARGET_CPU_generic.

AArch64: Refactor costs models to different files.

This patch series attempts to move the generic cost model in AArch64 to a new
and modern generic standard.  The current standard is quite old and generates
very suboptimal code out of the box for user of GCC.

The goal is for the new cost model to be beneficial on newer/current Arm
Microarchitectures while not being too negative for older ones.

It does not change any core specific optimization.  The final changes reflect
both performance optimizations and size optimizations.

This first patch just re-organizes the cost structures to their own files.
The AArch64.cc file has gotten very big and it's hard to follow.

No functional changes are expected from this change.  Note that since all the
structures have private visibility I've put them in header files instead.

gcc/ChangeLog:

PR target/111370
* config/aarch64/aarch64.cc (generic_addrcost_table,
exynosm1_addrcost_table,
xgene1_addrcost_table,
thunderx2t99_addrcost_table,
thunderx3t110_addrcost_table,
tsv110_addrcost_table,
qdf24xx_addrcost_table,
a64fx_addrcost_table,
neoversev1_addrcost_table,
neoversen2_addrcost_table,
neoversev2_addrcost_table,
generic_regmove_cost,
cortexa57_regmove_cost,
cortexa53_regmove_cost,
exynosm1_regmove_cost,
thunderx_regmove_cost,
xgene1_regmove_cost,
qdf24xx_regmove_cost,
thunderx2t99_regmove_cost,
thunderx3t110_regmove_cost,
tsv110_regmove_cost,
a64fx_regmove_cost,
neoversen2_regmove_cost,
neoversev1_regmove_cost,
neoversev2_regmove_cost,
generic_vector_cost,
a64fx_vector_cost,
qdf24xx_vector_cost,
thunderx_vector_cost,
tsv110_vector_cost,
cortexa57_vector_cost,
exynosm1_vector_cost,
xgene1_vector_cost,
thunderx2t99_vector_cost,
thunderx3t110_vector_cost,
ampere1_vector_cost,
generic_branch_cost,
generic_tunings,
cortexa35_tunings,
cortexa53_tunings,
cortexa57_tunings,
cortexa72_tunings,
cortexa73_tunings,
exynosm1_tunings,
thunderxt88_tunings,
thunderx_tunings,
tsv110_tunings,
xgene1_tunings,
emag_tunings,
qdf24xx_tunings,
saphira_tunings,
thunderx2t99_tunings,
thunderx3t110_tunings,
neoversen1_tunings,
ampere1_tunings,
ampere1a_tunings,
neoversev1_vector_cost,
neoversev1_tunings,
neoverse512tvb_vector_cost,
neoverse512tvb_tunings,
neoversen2_vector_cost,
neoversen2_tunings,
neoversev2_vector_cost,
neoversev2_tunings
a64fx_tunings): Split into own files.
* config/aarch64/tuning_models/a64fx.h: New file.
* config/aarch64/tuning_models/ampere1.h: New file.
* config/aarch64/tuning_models/ampere1a.h: New file.
* config/aarch64/tuning_models/cortexa35.h: New file.
* config/aarch64/tuning_models/cortexa53.h: New file.
* config/aarch64/tuning_models/cortexa57.h: New file.
* config/aarch64/tuning_models/cortexa72.h: New file.
* config/aarch64/tuning_models/cortexa73.h: New file.
* config/aarch64/tuning_models/emag.h: New file.
* config/aarch64/tuning_models/exynosm1.h: New file.
* config/aarch64/tuning_models/generic.h: New file.
* config/aarch64/tuning_models/neoverse512tvb.h: New file.
* config/aarch64/tuning_models/neoversen1.h: New file.
* config/aarch64/tuning_models/neoversen2.h: New file.
* config/aarch64/tuning_models/neoversev1.h: New file.
* config/aarch64/tuning_models/neoversev2.h: New file.
* config/aarch64/tuning_models/qdf24xx.h: New file.
* config/aarch64/tuning_models/saphira.h: New file.
* config/aarch64/tuning_models/thunderx.h: New file.
* config/aarch64/tuning_models/thunderx2t99.h: New file.
* config/aarch64/tuning_models/thunderx3t110.h: New file.
* config/aarch64/tuning_models/thunderxt88.h: New file.
* config/aarch64/tuning_models/tsv110.h: New file.
* config/aarch64/tuning_models/xgene1.h: New file.

AArch64: Add pattern for unsigned widenings (uxtl) to zip{1,2}

This changes unpack instructions to use zip{1,2} when doing a zero-extending
widening operation.  Permutes generally have a higher throughput than the
widening operations. Zeros are shuffled into the top half of the registers.

The testcase

void d2 (unsigned * restrict a, unsigned short *b, int n)
{
    for (int i = 0; i < (n & -8); i++)
      a[i] = b[i];
}

now generates:

        movi    v1.4s, 0
.L3:
        ldr     q0, [x1], 16
        zip1    v2.8h, v0.8h, v1.8h
        zip2    v0.8h, v0.8h, v1.8h
        stp     q2, q0, [x0]
        add     x0, x0, 32
        cmp     x1, x2
        bne     .L3

instead of:

.L3:
        ldr     q0, [x1], 16
        uxtl    v1.4s, v0.4h
        uxtl2   v0.4s, v0.8h
        stp     q1, q0, [x0]
        add     x0, x0, 32
        cmp     x1, x2
        bne     .L3

Since we need the extra 0 register we do this only for the vectorizer's lo/hi
pairs when we know the 0 will be floated outside of the loop.

This gives an 8% speed-up in Imagick in SPECCPU 2017 on Neoverse V2.

gcc/ChangeLog:

* config/aarch64/aarch64-simd.md (vec_unpack<su>_lo_<mode,
vec_unpack<su>_lo_<mode): Split into...
(vec_unpacku_lo_<mode, vec_unpacks_lo_<mode,
vec_unpacku_lo_<mode, vec_unpacks_lo_<mode): ...These.
(aarch64_usubw<mode>_<PERM_EXTEND:perm_hilo>_zip): New.
(aarch64_uaddw<mode>_<PERM_EXTEND:perm_hilo>_zip): New.
* config/aarch64/iterators.md (PERM_EXTEND, perm_index): New.
(perm_hilo): Add UNSPEC_ZIP1, UNSPEC_ZIP2.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/simd/vmovl_high_1.c: Update codegen.
* gcc.target/aarch64/uxtl-combine-1.c: New test.
* gcc.target/aarch64/uxtl-combine-2.c: New test.
* gcc.target/aarch64/uxtl-combine-3.c: New test.
* gcc.target/aarch64/uxtl-combine-4.c: New test.
* gcc.target/aarch64/uxtl-combine-5.c: New test.
* gcc.target/aarch64/uxtl-combine-6.c: New test.

AArch64: only discount MLA for vector and scalar statements

In testcases gcc.dg/tree-ssa/slsr-19.c  and gcc.dg/tree-ssa/slsr-20.c we have a
fairly simple computation.  On the current generic costing we generate:

f:
        add     w0, w0, 2
        madd    w1, w0, w1, w1
        lsl     w0, w1, 1
        ret

but on any other cost model but generic (including the new up coming generic)
we generate:

f:
        adrp    x2, .LC0
        dup     v31.2s, w0
        fmov    s30, w1
        ldr     d29, [x2, #:lo12:.LC0]
        add     v31.2s, v31.2s, v29.2s
        mul     v31.2s, v31.2s, v30.s[0]
        addp    v31.2s, v31.2s, v31.2s
        fmov    w0, s31
        ret
.LC0:
        .word   2
        .word   4

This seems to be because the vectorizer thinks the vector transfers are free:

x1_4 + x2_6 1 times vector_stmt costs 0 in body
x1_4 + x2_6 1 times vec_to_scalar costs 0 in body

This happens because the stmt it's using to get the cost of register transfers
for the given type happens to be one feeding into a MUL.  we incorrectly
discount the + for the register transfer.

This is fixed by guarding the check for aarch64_multiply_add_p with a kind
check and only do it for scalar_stmt and vector_stmt.

I'm sending this separate to my patch series but it's required for it.
It also seems to fix overvectorization cases in fotonik3d_r in SPECCPU 2017.

gcc/ChangeLog:

* config/aarch64/aarch64.cc (aarch64_adjust_stmt_cost): Guard mla.
(aarch64_vector_costs::count_ops): Likewise.

RISC-V: Add missing dump check of pr112438.c

Notice the dump check is missing, add it.

Committed as it is obvious.
gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr112438.c: Add missing dump check.

Fix 'gcc.dg/tree-ssa/return-value-range-1.c'

... added in recent commit 53ba8d669550d3a1f809048428b97ca607f95cf5
"inter-procedural value range propagation".

gcc/testsuite/
* gcc.dg/tree-ssa/return-value-range-1.c: Fix.

gcov: Fix integer types in gen_counter_update()

This change fixes issues like this:

  gcc.dg/gomp/pr27573.c: In function ‘main._omp_fn.0’:
  gcc.dg/gomp/pr27573.c:19:1: error: non-trivial conversion in ‘ssa_name’
     19 | }
        | ^
  long int
  long unsigned int
  # .MEM_19 = VDEF <.MEM_18>
  __gcov7.main._omp_fn.0[0] = PROF_time_profile_12;
  during IPA pass: profile
  gcc.dg/gomp/pr27573.c:19:1: internal compiler error: verify_gimple failed

gcc/ChangeLog:

PR middle-end/112634

* tree-profile.cc (gen_assign_counter_update): Cast the unsigned result type of
__atomic_add_fetch() to the signed counter type.
(gen_counter_update): Fix formatting.

ada: Fix miscompilation of loop over boolean range

The optimized form generated in this case turns out to be problematic.

gcc/ada/

* gcc-interface/trans.cc (Loop_Statement_to_gnu): Always use the
simpler form for a loop with a boolean iteration variable.

ada: Fix issue with indefinite vector of overaligned unconstrained array

The problem is that the aligning machinery is not consistently triggered,
depending on whether a constrained view or the nominal unconstrained view
of the element type is used to perform the allocations and deallocations.

gcc/ada/

* gcc-interface/decl.cc (gnat_to_gnu_entity) <E_Array_Subtype>: Put
the alignment directly on the type in the constrained case too.
* gcc-interface/utils.cc (maybe_pad_type): For an array type, take
the alignment of the element type as the original alignment.

ada: Compiler crash on container aggregate with loop_parameter_specifications

The compiler crashes on a container aggregate with more than one
iterated_element_association given by a loop_parameter_specification.
In such a case, the tree contains N_Iterated_Component_Association
nodes rather than N_Iterated_Element_Association nodes, and the code
for handling those needs to obtain the bounds from the Discrete_Choices
field of each N_Iterated_Component_Association rather than assuming
that the association has a normal list of choices.

gcc/ada/

* sem_aggr.adb (Resolve_Container_Aggregate): In the case where Comp
is an N_Iterated_Component_Association, pick up Discrete_Choices rather
than Choices.

ada: Another couple of cleanups in the finalization machinery

For package specs and bodies that need finalizers, Build_Finalizer is
invoked from the Standard scope so it needs to adjust the scope stack
before creating new objects; this changes it to do so only once.

For other kinds of scopes, it is invoked from Expand_Cleanup_Actions,
which assumes that the correct scope is already on the stack; that's
why Cleanup_Scopes adjusts the scope stack explicitly, but it should
use Pop_Scope instead of End_Scope to do it.

gcc/ada/

* exp_ch7.adb (Build_Finalizer): For package specs and bodies, push
and pop the specs onto the scope stack only once.
* inline.adb (Cleanup_Scopes): Call Pop_Scope instead of End_Scope.

ada: Deep delta aggregates in postconditions

Fix a bug in handling array-valued deep delta aggregates occurring in
postconditions. The bug could result in a spurious compilation failure.

gcc/ada/

* sem_aggr.adb (Resolve_Delta_Array_Aggregate): In the case of a
deep delta choice, the expected type for the expression will
typically not be the component type of the array type, so a call
to Analyze_And_Resolve that assumes otherwise would be an error.
It turns out that such a call, while wrong, is usually harmless
because the expression has already been marked as analyzed. This
doesn't work if the aggregate occurs in a postcondition and, in
any case, we don't want to rely on this. So do not perform the
call in the deep case.

ada: Small consistency fix for -gnatwv warning

The goal is to arrange for the warning to be issued consistently between
objects whose address is taken and objects whose address is not taken.

gcc/ada/

* sem_warn.adb (Check_References.Type_OK_For_No_Value_Assigned):
New predicate.
(Check_References): For Warn_On_No_Value_Assigned, use the same test
on the type in the address-not-taken and default cases.

gcc/testsuite/ChangeLog:

* gnat.dg/warn25.adb: Add xfail.

ada: Compiler error reporting illegal prefix on legal loop iterator with "in"

During semantic analysis, the compiler fails to determine the cursor type
in the case of a generalized iterator loop with "in", in the case where the
iterator type has a parent type that is a controlled type (for example) and
its ancestor iterator interface type is given after as a progenitor. It also
improperly determines the ancestor interface type during expansion (within
Expand_Iterator_Loop_Over_Container), for both "in" and "of" iterator forms.
The FE was assuming that the iterator interface is simply the parent type
of the iterator type, but that type can occur later in the interface list,
or be inherited. A new function is added that properly locates a type's
iterator interface ancestor, if any, and is called for analysis and expansion.

gcc/ada/

* exp_ch5.adb (Expand_Iterator_Loop_Over_Container): Retrieve the
iteration type's iteration interface progenitor via
Iterator_Interface_Ancestor, in the case of both "in" and "of"
iterators. Narrow the scope of Pack, so it's declared and
initialized only within the code related to "of" iterators, and
change its name to Cont_Type_Pack. Adjust comments.
* sem_ch5.adb (Get_Cursor_Type): In the case of a derived type,
retrieve the iteration type's iterator interface progenitor (if it
exists) via Iterator_Interface_Ancestor rather than assuming that
the parent type is the interface progenitor.
* sem_util.ads (Iterator_Interface_Ancestor): New function.
* sem_util.adb (Iterator_Interface_Ancestor): New function
returning a type's associated iterator interface type, if any, by
collecting and traversing the type's interfaces.

ada: Fix internal error on 'Address of task component

This happens when the prefix of the selected component is of an access type,
i.e. there is an implicit dereference. because the prefix is not resolved.

gcc/ada/

* sem_attr.adb (Resolve_Attribute) <Attribute_Address>: Remove the
bypass for prefixes with task type.

ada: Avoid Style_Checks pragmas affecting other units

gcc/ada/

* par.adb: Restore Style_Checks after parsing each unit.

ada: Fix type for SPARK expansion on deep delta aggregates

gcc/ada/

* exp_spark.adb (Expand_SPARK_Delta_Or_Aggregate): Fix type.

ada: Further cleanup in finalization machinery

The bodies of generic units are instantiated separately by GNAT at the end
of the processing of the compilation unit.  This requires the deferral of
the generation of cleanups and finalization actions in enclosing scopes,
except for instantiations in generic units where they are not generated.

The criterion used to detect this latter case is Inside_A_Generic, but this
global variable is not properly updated during the instantiation of generic
bodies, leading to problems with nested instantiations, so it is changed to
Expander_Active instead.  As a matter of fact, the exact same idiom is used
a few lines above to clear the Needs_Body variable.

gcc/ada/

* sem_ch12.adb (Analyze_Package_Instantiation): Test Expander_Active
to detect generic contexts for the generation of cleanup actions.

ada: Fix string indexing within GNAT.Calendar.Time_IO.Value

The patch fixes an issue in the compiler whereby calls to
GNAT.Calendar.Time_IO.Value where the actual for formal String Date with
indexing starting at any value besides one would result in a spurious runtime
exception.

gcc/ada/

* libgnat/g-catiio.adb (Value): Modify conditionals to use 'Last
instead of 'Length

ada: Small improvement to Null_Status function

The function is used to optimize away access checks.

gcc/ada/

* sem_util.adb (Null_Status): Deal with unchecked type conversions.

ada: Further cleanup in finalization machinery

This removes the specific treatment of transient scopes in initialization
procedures, which is obsolete.

gcc/ada/

* exp_aggr.adb (Convert_To_Assignments): Do not treat initialization
procedures specially when it comes to creating a transient scope.
* exp_ch7.adb (Build_Finalizer.Process_Declarations): Likewise.
* exp_util.adb (Requires_Cleanup_Actions): Likewise.

ada: Use CLOCK_MONOTONIC on VxWorks

The monotonic clock keeps track of the time that has elapsed since
system startup; that is, the value returned by clock_gettime() is the
amount of time (in seconds and nanoseconds) that has passed since the
system booted. The monotonic clock cannot be reset. As a result,
time interval measurements made relative to the monotonic clock are
not subject to errors resulting from the clock time being unexpectedly
adjusted between the interval start and end.

gcc/ada/

* s-oscons-tmplt.c: #define CLOCK_RT_Ada "CLOCK_MONOTONIC" for
__vxworks

ada: Deep delta aggregates cleanup.

Cleanup after the introduction of deep delta aggregates.
Eliminate a new gnatcheck message.

gcc/ada/

* sem_aggr.adb: Replace "not Present (...)" call with "No (...)" call.

ada: Small cleanup in finalization machinery

This removes an obsolete flag and adjusts a couple of obsolete comments.

gcc/ada/

* gen_il-fields.ads (Opt_Field_Enum): Remove Is_Finalization_Wrapper
* gen_il-gen-gen_nodes.adb (N_Block_Statement): Likewise.
* sinfo.ads (Is_Finalization_Wrapper): Delete.
* exp_ch7.adb (Build_Finalizer.Process_Declarations): Adjust comment
and remove obsolete code testing the Is_Finalization_Wrapper flag.
* exp_util.adb (Requires_Cleanup_Actions): Likewise.

ada: Runtime recompilation instructions improvements.

Revise instructions to work on both cross and native targets hosted
on Linux

gcc/ada/

* libgnat/libada.gpr: Revise section 1

ada: Deep delta aggregates

Add support for "deep" delta aggregates, a GNAT-defined language extension
conditionally enabled via the -gnatX0 switch. In a deep delta aggregate, a
delta choice may specify a subcomponent (as opposed to just a component).

gcc/ada/

* par.adb: Add new Boolean variable Inside_Delta_Aggregate.
* par-ch4.adb (P_Simple_Expression): Add support for a deep delta
aggregate choice. We turn a sequence of selectors into a peculiar
tree. We build a component (Indexed or Selected) whose prefix is
another such component, etc. The leftmost prefix at the bottom of
the tree has a "name" which is the first selector, without any
further prefix. For something like "with delta (1)(2) => 3" where
the type of the aggregate is an array of arrays of integers, we'll
build an N_Indexed_Component whose prefix is an integer literal 1.
This is consistent with the trees built for "regular"
(Ada-defined) delta aggregates.
* sem_aggr.adb (Is_Deep_Choice, Is_Root_Prefix_Of_Deep_Choice):
New queries.
(Resolve_Deep_Delta_Assoc): new procedure.
(Resolve_Delta_Array_Aggregate): call Resolve_Deep_Delta_Assoc in
deep case.
(Resolve_Delta_Record_Aggregate): call Resolve_Deep_Delta_Assoc in
deep case.
(Get_Component_Type): new function replaces old Get_Component
function.
* sem_aggr.ads (Is_Deep_Choice, Is_Root_Prefix_Of_Deep_Choice):
New queries.
* exp_aggr.adb (Expand_Delta_Array_Aggregate): add nested function
Make_Array_Delta_Assignment_LHS; call it instead of
Make_Indexed_Component.
(Expand_Delta_Record_Aggregate): add nested function
Make_Record_Delta_Assignment_LHS; call it instead of
Make_Selected_Component.
* exp_spark.adb (Expand_SPARK_Delta_Or_Update): Insert range
checks for indexes in deep delta aggregates.

ada: Fix Ada.Text_IO.Delete with "encoding=8bits" form

Before this patch, on Windows, file with non-ASCII Latin1 names could be created
with Ada.Text_IO.Create by passing "encoding=8bits" through the Form
parameter and a Latin1-encoded string through the Name parameter,
but calling Ada.Text_IO.Delete on them raised an illegitimate exception.

This patch fixes this by making the wrappers of the unlink system function
aware of the encoding value passed through the Form parameter. It also
removes an unnecessary curly-brace block.

gcc/ada/

* adaint.c (__gnat_unlink): Add new parameter and fix text
conversion on Windows. Remove unnecessary curly braces.
* adaint.h (__gnat_unlink): Add new parameter.
* libgnat/i-cstrea.ads (unlink): Adapt to __gnat_unlink signature
change.
* libgnat/i-cstrea.adb (unlink): New Subprogram definition.
* libgnat/s-crtl.ads (unlink): Adapt to __gnat_unlink signature
change.
* libgnat/s-fileio.adb (Delete): Pass encoding argument to unlink.

ada: Fix spurious error on call with default parameter in generic package

This occurs when the default value is a function call returning a private
type, and is caused by a bad interaction between two internal mechanisms.

gcc/ada/

* sem_ch12.adb (Save_Global_References.Set_Global_Type): Beef up
comment about the setting of the full view.
* sem_res.adb (Resolve_Actuals.Insert_Default): Add another bypass
for the case of a generic context.

ada: Fix misplaced index directive in documentation

The index directive must be located before the indexed element, at least
for the generated texinfo to be correct. See:

https://www.sphinx-doc.org/en/master/usage/restructuredtext/directives.html#directive-index

This was reported along with changes done in https://inbox.sourceware.org/gcc-patches/20230223102714.3606058-3-arsen@aarsen.me/

gcc/ada/

* doc/gnat_ugn/the_gnat_compilation_model.rst: Move index
directives.
* gnat_ugn.texi: Regenerate.

ada: Fix SCOs generation for aspect specifications

The recent overhaul for the representation of aspect specifications in
the tree broke SCOs generation: decisions that appeared in aspects were
processed twice, leading to the emission of erroneous obligations. Tweak
SCOs generation to skip aspect specifications the second time to go back
to the previous behavior.

gcc/ada/

* par_sco.adb (Process_Decisions)<Process_Node>: Skip aspect
specifications.

ada: Always use -gnatg in run-time GPR files

This patch makes it so -gnatg is always passed to the compiler when
rebuilding the run-time library with the dedicated GPR files. Before
this patch, if a user rebuilt the run-time with -XADAFLAGS=XXX where
XXX didn't include "-gnatg", the build would immediately fail. This
case occurs when following the instructions in libada.gpr, which
use '-XADAFLAGS="-gnatn"'.

gcc/ada/

* libgnat/libgnat_common.gpr: Unconditionally pass -gnatg.

ada: Trivial typo fix in comment

gcc/ada/

* exp_util.ads: Typo fix.

gcov: Formatting fixes

I've noticed the r14-5579 commit introduced some formatting issues,
this patch fixes what I saw.

2023-11-21  Jakub Jelinek  <jakub@redhat.com>

gcc/
* tree-profile.cc (gen_counter_update, tree_profiling): Formatting
fixes.
libgcc/
* libgcov.h (GCOV_SUPPORTS_ATOMIC): Formatting fixes.

testsuite: Fix up pr111309-2.c on arm [PR111309]

ARM defaults to -fshort-enums and the following testcase FAILs there in 2
lines.  The difference is that in C++, E0 has enum E type, which normally
has unsigned int underlying type, so it isn't int nor something that
promotes to int, which is why we diagnose it (in C it is promoted to int).
But with -fshort-enums, the underlying type is unsigned char in that case,
which promotes to int just fine.

The following patch adjusts the expectations, such that we don't expect
it on arm or when people manually test with -fshort-enums.

2023-11-21  Jakub Jelinek  <jakub@redhat.com>

PR c/111309
* c-c++-common/pr111309-2.c (foo): Don't expect errors for C++ with
-fshort-enums if second argument is E0.

builtins: Fix fold_builtin_query clzg/ctzg side-effects handling [PR112639]

As the testcase shows, I've missed one spot where initially the code thinks
it could use 2 argument IFN_CLZ/IFN_CTZ form, but then verifies it can't
because it doesn't have the right target value and turns it into the
arg0 ? arg1 : .C[LT]Z (arg0)
form.  That form evaluates the argument twice though and so needs save_expr,
which I've missed to call in that case.  In other cases where it is known
from the beginning that it will be needed (e.g. the __builtin_clzg case
on types smaller than unsigned int where we'll need to add an addend
to the clz value) or the unsigned __int128 expansion called save_expr
before.

2023-11-21  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/112639
* builtins.cc (fold_builtin_bit_query): If arg0 has side-effects, arg1
is specified but cleared, call save_expr on arg0.

* gcc.dg/torture/pr112639.c: New test.

[APX PPX] Support Intel APX PPX

PPX stands for Push-Pop Acceleration. PUSH/PUSH2 and its corresponding POP
can be marked with a 1-bit hint to indicate that the POP reads the
value written by the PUSH from the stack. The processor tracks these marked
instructions internally and fast-forwards register data between
matching PUSH and POP instructions, without going through memory or
through the training loop of the Fast Store Forwarding Predictor (FSFP).
This feature can also be adopted to PUSH2/POP2.

For GCC, we emit explicit suffix 'p' (paired) to indicate the push/pop
pair are marked with PPX hint. To separate form original push/pop, we
add an UNSPEC on top of those PUSH/POP patterns.

In the first implementation we only emit them under prologue/epilogue
when saving/restoring callee-saved registers to make sure push/pop are
paired. So an extra flag was added to check if PPX insns can be emitted
for those register save/restore interfaces.

The PPX hint is purely a performance hint. If the 'p' suffix is not
emitted for paired push/pop, the PPX optimization will be disabled,
while program sematic will not be affected at all.

gcc/ChangeLog:

* config/i386/i386-expand.h (gen_push): Add default bool
parameter.
(gen_pop): Likewise.
* config/i386/i386-opts.h (enum apx_features): Add apx_ppx, add
it to apx_all.
* config/i386/i386.cc (ix86_emit_restore_reg_using_pop): Add
ppx_p parameter for function declaration.
(gen_push2): Add ppx_p parameter, emit push2p if ppx_p is true.
(gen_push): Likewise.
(ix86_emit_restore_reg_using_pop2): Likewise for pop2p.
(ix86_emit_save_regs): Emit pushp/push2p under TARGET_APX_PPX.
(ix86_emit_restore_reg_using_pop): Add ppx_p, emit popp insn
and adjust cfi when ppx_p is ture.
(ix86_emit_restore_reg_using_pop2): Add ppx_p and parse to its
callee.
(ix86_emit_restore_regs_using_pop2): Likewise.
(ix86_expand_epilogue): Parse TARGET_APX_PPX to
ix86_emit_restore_reg_using_pop.
* config/i386/i386.h (TARGET_APX_PPX): New.
* config/i386/i386.md (UNSPEC_APX_PPX): New unspec.
(pushp_di): New define_insn.
(popp_di): Likewise.
(push2p_di): Likewise.
(pop2p_di): Likewise.
* config/i386/i386.opt: Add apx_ppx enum.

gcc/testsuite/ChangeLog:

* gcc.target/i386/apx-interrupt-1.c: Adjust option to restrict them
under certain subfeatures.
* gcc.target/i386/apx-push2pop2-1.c: Likewise.
* gcc.target/i386/apx-push2pop2_force_drap-1.c: Likewise.
* gcc.target/i386/apx-push2pop2_interrupt-1.c: Likewise.
* gcc.target/i386/apx-ppx-1.c: New test.

middle-end/112622 - adjust arm testcases

The error message improved, adjust arm specific testcases.

* gcc.target/arm/bfloat16_vector_typecheck_1.c: Adjust.
* gcc.target/arm/bfloat16_vector_typecheck_2.c: Likewise.
* gcc.target/aarch64/bfloat16_vector_typecheck_1.c: Likewise.
* gcc.target/aarch64/bfloat16_vector_typecheck_2.c: Likewise.

tree-optimization/111970 - fix issue with SLP of emulated gather/scatter

There's a missed index adjustment for the SLP vector number when
computing the index/data vectors for emulated gather/scatter with SLP.
The following fixes this.

PR tree-optimization/111970
* tree-vect-stmts.cc (vectorizable_load): Fix offset calculation
for SLP gather load.
(vectorizable_store): Likewise for SLP scatter store.

LoongArch: Fix libgcc build failure when libc is not available

To use int64_t we included <stdint.h> in loongarch-def.h.
Unfortunately, loongarch-def.h is also used by libgcc etc., causing a
build failure when building a "stage1" cross compiler at which the
target libc is not built yet.

As int64_t is used for a C-compatible replacement of HOST_WIDE_INT, it's
not directly or indirectly referred by the target libraries.  So
guard everything requiring stdint.h with #if then they'll not block
target libraries.

gcc/ChangeLog:

* config/loongarch/loongarch-def.h (stdint.h): Guard with #if to
exclude it for target libraries.
(loongarch_isa_base_features): Likewise.
(loongarch_isa): Likewise.
(loongarch_abi): Likewise.
(loongarch_target): Likewise.
(loongarch_cpu_default_isa): Likewise.

RISC-V: Fix reduc_run-9.c test value check bug

The current test value check is incorrect which is exposed on -march=rv64gcv_zvl256b

Confirm on X86 also abort:
[jzzhong@rios-cad121:/work/home/jzzhong/work/insn]$./a.out
------33.000000,4078.000000,45001776.000000,63369904.000000---
Aborted (core dumped)

Adapt the value check according to X86 result.

Pushed as it is obvious.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/reduc/reduc_run-9.c: Fix bug.

Support reduc_{and,ior,xor}_scal_m for V4HI/V8QI/V4QImode

gcc/ChangeLog:

PR target/112325
* config/i386/i386-expand.cc (emit_reduc_half): Hanlde
V8QImode.
* config/i386/mmx.md (reduc_<code>_scal_<mode>): New expander.
(reduc_<code>_scal_v4qi): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/pr112325-mmx-1.c: New test.

Daily bump.

Trivial typo fix in variadic

Fix all occurences of varadic, except for Rust (will be part of another change).

gcc/ChangeLog:

* config/nvptx/nvptx.h (struct machine_function): Fix typo in variadic.
* config/nvptx/nvptx.cc (nvptx_function_arg_advance): Adjust to use fixed name.
(nvptx_declare_function_name): Likewise.
(nvptx_call_args): Likewise.
(nvptx_expand_call): Likewise.

gcc/cp/ChangeLog:

* lambda.cc (compare_lambda_sig): Fix typo in variadic.

libcpp/ChangeLog:

* macro.cc (parse_params): Fix typo in variadic.
(create_iso_definition): Likewise.

Signed-off-by: Marc Poulhiès <dkm@kataplop.net>

gcov: Use unshare_expr() in gen_counter_update()

This fixes issues like this:

  gcc/testsuite/gcc.dg/no_profile_instrument_function-attr-1.c: In function 'main':
  gcc/testsuite/gcc.dg/no_profile_instrument_function-attr-1.c:19:1: error: incorrect sharing of tree nodes
  __gcov0.main[0]
  # .MEM_12 = VDEF <.MEM_9>
  __gcov0.main[0] = PROF_edge_counter_4;
  during IPA pass: profile
  gcc/testsuite/gcc.dg/no_profile_instrument_function-attr-1.c:19:1: internal compiler error: verify_gimple failed

Unshare the counter expression in the second gimple_build_assign() in
gen_counter_update().  This is similar to the original
gimple_gen_edge_profiler() for "ref":

void
gimple_gen_edge_profiler (int edgeno, edge e)
{
  tree one;

  one = build_int_cst (gcov_type_node, 1);

  if (flag_profile_update == PROFILE_UPDATE_ATOMIC)
[...]
  else
    {
      tree ref = tree_coverage_counter_ref (GCOV_COUNTER_ARCS, edgeno);
      tree gcov_type_tmp_var = make_temp_ssa_name (gcov_type_node,
   NULL, "PROF_edge_counter");
      gassign *stmt1 = gimple_build_assign (gcov_type_tmp_var, ref);
      gcov_type_tmp_var = make_temp_ssa_name (gcov_type_node,
      NULL, "PROF_edge_counter");
      gassign *stmt2 = gimple_build_assign (gcov_type_tmp_var, PLUS_EXPR,
    gimple_assign_lhs (stmt1), one);
      gassign *stmt3 = gimple_build_assign (unshare_expr (ref),
    gimple_assign_lhs (stmt2));
      gsi_insert_on_edge (e, stmt1);
      gsi_insert_on_edge (e, stmt2);
      gsi_insert_on_edge (e, stmt3);
    }
}

However, the orignal gimple_gen_time_profiler() did not use unshare_expr() for
the counter expression (tree_time_profiler_counter):

void
gimple_gen_time_profiler (unsigned tag)
{
[...]

  /* Emit: counters[0] = ++__gcov_time_profiler_counter.  */
  if (flag_profile_update == PROFILE_UPDATE_ATOMIC)
[...]
  else
    {
      tree tmp = make_temp_ssa_name (type, NULL, "PROF_time_profile");
      gassign *assign = gimple_build_assign (tmp, tree_time_profiler_counter);
      gsi_insert_before (&gsi, assign, GSI_NEW_STMT);

      tmp = make_temp_ssa_name (type, NULL, "PROF_time_profile");
      assign = gimple_build_assign (tmp, PLUS_EXPR, gimple_assign_lhs (assign),
    one);
      gsi_insert_after (&gsi, assign, GSI_NEW_STMT);
      assign = gimple_build_assign (original_ref, tmp);
      gsi_insert_after (&gsi, assign, GSI_NEW_STMT);
      assign = gimple_build_assign (tree_time_profiler_counter, tmp);
      gsi_insert_after (&gsi, assign, GSI_NEW_STMT);
    }
}

gcc/ChangeLog:

* tree-profile.cc (gen_counter_update): Use unshare_expr() for the
counter expression in the second gimple_build_assign().

inter-procedural value range propagation

implement very basic propapgation of return value ranges from VRP
pass.  This helps std::vector's push_back since we work out value range of
allocated block.  This propagates only within single translation unit.  I hoped
we will also do the propagation at WPA stage, but that needs more work on
ipa-cp side.

I also added code auto-detecting return_nonnull and corresponding -Wsuggest-attribute.

gcc/ChangeLog:

* cgraph.cc (add_detected_attribute_1): New function.
(cgraph_node::add_detected_attribute): Likewise.
* cgraph.h (cgraph_node::add_detected_attribute): Declare.
* common.opt: Add -Wsuggest-attribute=returns_nonnull.
* doc/invoke.texi: Document new flag.
* gimple-range-fold.cc (fold_using_range::range_of_call):
Use known reutrn value ranges.
* ipa-prop.cc (struct ipa_return_value_summary): New type.
(class ipa_return_value_sum_t): New type.
(ipa_return_value_sum): New summary.
(ipa_record_return_value_range): New function.
(ipa_return_value_range): New function.
* ipa-prop.h (ipa_return_value_range): Declare.
(ipa_record_return_value_range): Declare.
* ipa-pure-const.cc (warn_function_returns_nonnull): New funcion.
* ipa-utils.h (warn_function_returns_nonnull): Declare.
* symbol-summary.h: Fix comment.
* tree-vrp.cc (execute_ranger_vrp): Record return values.

gcc/testsuite/ChangeLog:

* g++.dg/ipa/devirt-2.C: Add noipa attribute to prevent ipa-vrp.
* g++.dg/ipa/devirt-7.C: Disable ipa-vrp.
* g++.dg/ipa/ipa-icf-2.C: Disable ipa-vrp.
* g++.dg/ipa/ipa-icf-3.C: Disable ipa-vrp.
* g++.dg/ipa/ivinline-1.C: Disable ipa-vrp.
* g++.dg/ipa/ivinline-3.C: Disable ipa-vrp.
* g++.dg/ipa/ivinline-5.C: Disable ipa-vrp.
* g++.dg/ipa/ivinline-8.C: Disable ipa-vrp.
* g++.dg/ipa/nothrow-1.C: Disable ipa-vrp.
* g++.dg/ipa/pure-const-1.C: Disable ipa-vrp.
* g++.dg/ipa/pure-const-2.C: Disable ipa-vrp.
* g++.dg/lto/inline-crossmodule-1_0.C: Disable ipa-vrp.
* gcc.c-torture/compile/pr106433.c: Add noipa attribute to prevent ipa-vrp.
* gcc.c-torture/execute/frame-address.c: Likewise.
* gcc.dg/vla-1.c: Add noipa attribute to prevent ipa-vrp.
* gcc.dg/ipa/fopt-info-inline-1.c: Disable ipa-vrp.
* gcc.dg/ipa/ipa-icf-25.c: Disable ipa-vrp.
* gcc.dg/ipa/ipa-icf-38.c: Disable ipa-vrp.
* gcc.dg/ipa/pure-const-1.c: Disable ipa-vrp.
* gcc.dg/ipa/remref-0.c: Add noipa attribute to prevent ipa-vrp.
* gcc.dg/tree-prof/time-profiler-1.c: Disable ipa-vrp.
* gcc.dg/tree-prof/time-profiler-2.c: Disable ipa-vrp.
* gcc.dg/tree-ssa/pr110269.c: Disable ipa-vrp.
* gcc.dg/tree-ssa/pr20701.c: Disable ipa-vrp.
* gcc.dg/tree-ssa/vrp05.c: Disable ipa-vrp.
* gcc.dg/tree-ssa/return-value-range-1.c: New test.

tree-optimization/112618 - unused .MASK_CALL

We have to make sure to remove unused .MASK_CALL internal function
calls after vectorization.

PR tree-optimization/112618
* tree-vect-loop.cc (vect_transform_loop_stmt): For not
relevant and unused .MASK_CALL make sure we remove the
scalar stmt.

* gcc.dg/pr112618.c: New testcase.

tree-optimization/112281 - loop distribution and zero dependence distances

The following fixes an omission in dependence testing for loop
distribution.  When the overall dependence distance is not zero but
the dependence direction in the innermost common loop is = there is
a conflict between the partitions and we have to merge them.

PR tree-optimization/112281
* tree-loop-distribution.cc
(loop_distribution::pg_add_dependence_edges): For = in the
innermost common loop record a partition conflict.

* gcc.dg/torture/pr112281-1.c: New testcase.
* gcc.dg/torture/pr112281-2.c: Likewise.

middle-end/112622 - convert and vector-to-float

The following avoids ICEing when trying to convert a vector to
a scalar float.

PR middle-end/112622
* convert.cc (convert_to_real_1): Use element_precision
where a vector type might appear.  Provide specific
diagnostic for unexpected vector argument.

* gcc.dg/pr112622.c: New testcase.
* gcc.dg/simd-2.c: Adjust.
* gcc.target/i386/vect-bfloat16-typecheck_1.c: Likewise.
* gcc.target/i386/vect-bfloat16-typecheck_2.c: Likewise.

RISC-V: Fix intermediate mode on slide1 instruction for SEW64 on RV32

This bug was discovered on PR112597, with -march=rv32gcv_zvl256b --param=riscv-autovec-preference=fixed-vlmax

ICE:
bug.c:10:1: error: unrecognizable insn:
   10 | }
      | ^
(insn 10 9 11 2 (set (reg:V4SI 140)
        (unspec:V4SI [
                (unspec:V4BI [
                        (const_vector:V4BI [
                                (const_int 1 [0x1]) repeated x4
                            ])
                        (const_int 4 [0x4])
                        (const_int 2 [0x2]) repeated x3
                        (reg:SI 66 vl)
                        (reg:SI 67 vtype)
                    ] UNSPEC_VPREDICATE)
                (unspec:V4SI [
                        (reg:SI 0 zero)
                    ] UNSPEC_VUNDEF)
                (subreg:V4SI (reg:V2DI 138 [ v ]) 0)
                (subreg:SI (reg/v:DI 136 [ b ]) 0)
            ] UNSPEC_VSLIDE1DOWN)) "bug.c":8:10 -1
     (nil))

The rootcase is we don't enable V4SImode, instead, we already have RVVMF2SI which is totally same as V4SI
on -march=rv32gcv_zvl256 + --param=riscv-autovec-preference=fixed-vlmax.

The attribute VDEMODE map to V4SI is incorrect, we remove attributes and use get_vector_mode to get
right mode.

PR target/112597

gcc/ChangeLog:

* config/riscv/vector-iterators.md: Remove VDEMOTE and VMDEMOTE.
* config/riscv/vector.md: Fix slide1 intermediate mode bug.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr112597-1.c: New test.

RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv.

We currently allow 64-bit indices/offsets for vector indexed loads and
stores even on rv32 but we should not.

This patch adjusts the iterators as well as the insn conditions to
reflect the RVV spec.

It also fixes an oversight in the VLS modes of the demote iterator that
was found while testing the patch.

gcc/ChangeLog:

* config/riscv/riscv-v.cc (gather_scatter_valid_offset_mode_p):
Add check for XLEN == 32.
* config/riscv/vector-iterators.md: Change VLS part of the
demote iterator to 2x elements modes
* config/riscv/vector.md: Adjust iterators and insn conditions.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-1.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-1.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-10.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-10.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-11.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-11.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-12.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-12.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-2.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-2.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-3.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-3.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-4.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-4.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-5.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-5.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-6.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-6.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-7.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-7.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-8.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-8.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-9.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-9.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-1.c:
Adjust include.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-10.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-11.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-9.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-1.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-1.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-10.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-10.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-11.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-11.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-2.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-2.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-3.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-3.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-4.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-4.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-5.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-5.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-6.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-6.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-7.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-7.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-8.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-8.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-9.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-9.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-1.c:
Adjust include.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-10.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-11.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-9.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-1.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-1.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-10.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-10.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-2.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-2.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-3.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-3.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-4.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-4.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-5.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-5.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-6.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-6.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-7.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-7.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-8.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-8.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-9.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-9.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-1.c:
Adjust include.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-10.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-9.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-1.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-1.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-10.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-10.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-3.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-2.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-4.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-4.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-5.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-5.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-6.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-6.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-7.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-7.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-8.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-8.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-9.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-9.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-2.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-2.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-1.c:
Adjust include.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-10.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-9.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-1.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-10.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-11.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-2.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-3.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-4.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-5.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-6.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-7.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-8.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-9.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-1.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-10.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-11.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-2.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-3.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-4.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-5.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-6.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-7.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-8.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-9.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-1.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-10.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-2.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-3.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-4.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-5.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-6.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-7.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-8.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-9.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-1.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-10.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-3.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-4.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-5.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-6.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-7.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-8.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-9.c: New test.

arm: [MVE intrinsics] rework vldq1 vst1q

Implement vld1q, vst1q using the new MVE builtins framework.

2023-11-16  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/
* config/arm/arm-mve-builtins-base.cc (vld1_impl, vld1q)
(vst1_impl, vst1q): New.
* config/arm/arm-mve-builtins-base.def (vld1q, vst1q): New.
* config/arm/arm-mve-builtins-base.h (vld1q, vst1q): New.
* config/arm/arm_mve.h
(vld1q): Delete.
(vst1q): Delete.
(vld1q_s8): Delete.
(vld1q_s32): Delete.
(vld1q_s16): Delete.
(vld1q_u8): Delete.
(vld1q_u32): Delete.
(vld1q_u16): Delete.
(vld1q_f32): Delete.
(vld1q_f16): Delete.
(vst1q_f32): Delete.
(vst1q_f16): Delete.
(vst1q_s8): Delete.
(vst1q_s32): Delete.
(vst1q_s16): Delete.
(vst1q_u8): Delete.
(vst1q_u32): Delete.
(vst1q_u16): Delete.
(__arm_vld1q_s8): Delete.
(__arm_vld1q_s32): Delete.
(__arm_vld1q_s16): Delete.
(__arm_vld1q_u8): Delete.
(__arm_vld1q_u32): Delete.
(__arm_vld1q_u16): Delete.
(__arm_vst1q_s8): Delete.
(__arm_vst1q_s32): Delete.
(__arm_vst1q_s16): Delete.
(__arm_vst1q_u8): Delete.
(__arm_vst1q_u32): Delete.
(__arm_vst1q_u16): Delete.
(__arm_vld1q_f32): Delete.
(__arm_vld1q_f16): Delete.
(__arm_vst1q_f32): Delete.
(__arm_vst1q_f16): Delete.
(__arm_vld1q): Delete.
(__arm_vst1q): Delete.
* config/arm/mve.md (mve_vld1q_f<mode>): Rename into ...
(@mve_vld1q_f<mode>): ... this.
(mve_vld1q_<supf><mode>): Rename into ...
(@mve_vld1q_<supf><mode>) ... this.
(mve_vst1q_f<mode>): Rename into ...
(@mve_vst1q_f<mode>): ... this.
(mve_vst1q_<supf><mode>): Rename into ...
(@mve_vst1q_<supf><mode>) ... this.

arm: [MVE intrinsics] fix vst1 tests

vst1q intrinsics return void, so we should not do 'return vst1q_f16 (base, value);'

This was OK so far, but will trigger an error/warning with the new
implementation of these intrinsics.

This patch just removes the 'return' keyword.

2023-11-16  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/testsuite/
* gcc.target/arm/mve/intrinsics/vst1q_f16.c: Remove 'return'.
* gcc.target/arm/mve/intrinsics/vst1q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_u8.c: Likewise.

arm: [MVE intrinsics] add load and store shapes

This patch adds the load and store shapes descriptions.

2023-11-16  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (load, store): New.
* config/arm/arm-mve-builtins-shapes.h (load, store): New.

arm: [MVE intrinsics] Add support for contiguous loads and stores

This patch adds base support for load/store intrinsics to the
framework, starting with loads and stores for contiguous memory
elements, without extension nor truncation.

Compared to the aarch64/SVE implementation, there's no support for
gather/scatter loads/stores yet.  This will be added later as needed.

2023-11-16  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/
* config/arm/arm-mve-builtins-functions.h (multi_vector_function)
(full_width_access): New classes.
* config/arm/arm-mve-builtins.cc
(find_type_suffix_for_scalar_type, infer_pointer_type)
(require_pointer_type, get_contiguous_base, add_mem_operand)
(add_fixed_operand, use_contiguous_load_insn)
(use_contiguous_store_insn): New.
* config/arm/arm-mve-builtins.h (memory_vector_mode)
(infer_pointer_type, require_pointer_type, get_contiguous_base)
(add_mem_operand)
(add_fixed_operand, use_contiguous_load_insn)
(use_contiguous_store_insn): New.

arm: [MVE intrinsics] Add support for void and load/store pointers as argument types.

This patch adds support for '_', 'al' and 'as' for void, load pointer
and store pointer argument/return value types in intrinsic signatures.

It also adds a mew memory_scalar_type() helper to function_instance,
which is used by 'al' and 'as'.

2023-11-16  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (build_const_pointer):
New.
(parse_type): Add support for '_', 'al' and 'as'.
* config/arm/arm-mve-builtins.h (function_instance): Add
memory_scalar_type.
(function_base): Likewise.

arm: Fix arm_simd_types and MVE scalar_types

So far we define arm_simd_types and scalar_types using type
definitions like intSI_type_node, etc...

This is causing problems with later patches which re-implement
load/store MVE intrinsics, leading to error messages such as:
  error: passing argument 1 of 'vst1q_s32' from incompatible pointer type
  note: expected 'int *' but argument is of type 'int32_t *' {aka 'long int *'}

This patch uses get_typenode_from_name (INT32_TYPE) instead, which
defines the types as appropriate for the target/C library.

2023-11-16  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/
* config/arm/arm-builtins.cc (arm_init_simd_builtin_types): Fix
initialization of arm_simd_types[].eltype.
* config/arm/arm-mve-builtins.def (DEF_MVE_TYPE): Fix scalar
types.

RISC-V Regression: Remove scalable compile option

Since we already set scalable vectorization by default, this flag is redundant.

Also, we are start to full coverage testing with different compile option.
E.g --param=riscv-autovec-preference=fixed-vlmax.
To avoid compile option confusion. Remove it.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp: Remove scalable compile option.

c, c++: Add new value for vector types for __builtin_classify_type

While filing a clang request to return 18 on _BitInts for
__builtin_classify_type instead of -1 they return currently, I've
noticed that we return -1 for vector types.  Initially I wanted to change
behavior just for __builtin_classify_type (type) form, as that is new in
GCC 14 and we've returned for 20+ years -1 for __builtin_classify_type
on vector expressions, but I was convinved otherwise, so this changes
the behavior even for that and now returns 19.

2023-11-20  Jakub Jelinek  <jakub@redhat.com>

gcc/
* typeclass.h (enum type_class): Add vector_type_class.
* builtins.cc (type_to_class): Return vector_type_class for
VECTOR_TYPE.
* doc/extend.texi (__builtin_classify_type): Mention bit-precise
integer types and vector types.
gcc/testsuite/
* c-c++-common/builtin-classify-type-1.c (main): Add tests for vector
types.

vect: Add bool pattern handling for COND_OPs.

In order to handle masks properly for conditional operations this patch
teaches vect_recog_mask_conversion_pattern to also handle conditional
operations.  Now we convert e.g.

 _mask = *_6;
 _ifc123 = COND_OP (_mask, ...);

into
 _mask = *_6;
 patt200 = (<signed-boolean:1>) _mask;
 patt201 = COND_OP (patt200, ...);

This way the mask will be properly recognized as boolean mask and the
correct vector mask will be generated.

gcc/ChangeLog:

PR middle-end/112406

* tree-vect-patterns.cc (vect_recog_mask_conversion_pattern):
Convert masks for conditional operations as well.

gcc/testsuite/ChangeLog:

* gfortran.dg/pr112406.f90: New test.

tree-ssa-math-opts: popcount (X) == 1 to (X ^ (X - 1)) > (X - 1) optimization for direct optab [PR90693]

On Fri, Nov 17, 2023 at 03:01:04PM +0100, Jakub Jelinek wrote:
> As a follow-up, I'm considering changing in this routine the popcount
> call to IFN_POPCOUNT with 2 arguments and during expansion test costs.

Here is the follow-up which does the rtx costs testing.

2023-11-20  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/90693
* tree-ssa-math-opts.cc (match_single_bit_test): Mark POPCOUNT with
result only used in equality comparison against 1 with direct optab
support as .POPCOUNT call with 2 arguments.
* internal-fn.h (expand_POPCOUNT): Declare.
* internal-fn.def (DEF_INTERNAL_INT_EXT_FN): New macro, document it,
undefine at the end.
(POPCOUNT): Use it instead of DEF_INTERNAL_INT_FN.
* internal-fn.cc (DEF_INTERNAL_INT_EXT_FN): Define to nothing before
inclusion to define expanders.
(expand_POPCOUNT): New function.

tree-ssa-math-opts: popcount (X) == 1 to (X ^ (X - 1)) > (X - 1) optimization [PR90693]

Per the earlier discussions on this PR, the following patch folds
popcount (x) == 1 (and != 1) into (x ^ (x - 1)) > x - 1 (or <=)
if the corresponding popcount optab isn't implemented (I think any
double-word popcount or call will be necessarily slower than the
above cheap 3 op check and even for -Os larger or same size).

I've noticed e.g. C++ aligned new starts with std::has_single_bit
which does popcount (x) == 1.

As a follow-up, I'm considering changing in this routine the popcount
call to IFN_POPCOUNT with 2 arguments and during expansion test costs.

2023-11-20  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/90693
* tree-ssa-math-opts.cc (match_single_bit_test): New function.
(math_opts_dom_walker::after_dom_children): Call it for EQ_EXPR
and NE_EXPR assignments and GIMPLE_CONDs.

* gcc.target/i386/pr90693.c: New test.