Patrick Palka [Wed, 3 Feb 2016 20:14:43 +0000 (20:14 +0000)]
Fix PR c++/69056 (argument pack deduction failure during overload resolution)
gcc/cp/ChangeLog:
PR c++/69056
* pt.c (try_one_overload): Handle comparing argument packs so
that there is no conflict if we deduced more arguments of an
argument pack than were explicitly specified.
re PR target/69461 (ICE in lra_set_insn_recog_data, at lra.c:964)
2016-02-03 Vladimir Makarov <vmakarov@redhat.com>
Alexandre Oliva <aoliva@redhat.com>
PR target/69461
* lra-constraints.c (simplify_operand_subreg): Check additionally
address validity after potential reloading.
(process_address_1): Check insns validity. In case of failure do
nothing.
2016-02-03 Vladimir Makarov <vmakarov@redhat.com>
Alexandre Oliva <aoliva@redhat.com>
Uros Bizjak [Wed, 3 Feb 2016 17:01:01 +0000 (18:01 +0100)]
tsan-dg.exp (tsan_init): Move check if tsan executable works from here ...
* lib/tsan-dg.exp (tsan_init): Move check if tsan executable
works from here ...
(check_effective_target_fsanitize_thread): ... to here. Do not
specify additional compile flags for the test source.
* lib/asan-dg.exp (check_effective_target_fsanitize_address): Do not
specify additional compile flags for the test source.
Wilco Dijkstra [Wed, 3 Feb 2016 12:18:19 +0000 (12:18 +0000)]
Fix the ccmp_1.c test back to use '0' as regular expressions don't work correctly.
Fix the ccmp_1.c test back to use '0' as regular expressions don't work
correctly. '0' is right due to compare with zero now printing as
'CMP w0, 0' rather than 'CMP w0, wzr'.
2016-02-03 Wilco Dijkstra <wdijkstr@arm.com>
gcc/testsuite/
* gcc.target/aarch64/ccmp_1.c: Fix test issue.
re PR fortran/67451 ([F08] ICE with sourced allocation from coarray.)
gcc/testsuite/ChangeLog:
2016-02-03 Andre Vehreschild <vehre@gcc.gnu.org>
PR fortran/67451
PR fortran/69418
* gfortran.dg/coarray_allocate_2.f08: New test.
* gfortran.dg/coarray_allocate_3.f08: New test.
* gfortran.dg/coarray_allocate_4.f08: New test.
gcc/fortran/ChangeLog:
2016-02-03 Andre Vehreschild <vehre@gcc.gnu.org>
PR fortran/67451
PR fortran/69418
* trans-expr.c (gfc_copy_class_to_class): For coarrays just the
pointer is passed. Take it as is without trying to deref the
_data component.
* trans-stmt.c (gfc_trans_allocate): Take care of coarrays as
argument to source=-expression.
Excess errors:
/home/segher/src/gcc/gcc/testsuite/c-c++-common/vector-compare-4.c:31:1: warning: GCC vector returned by reference: non-standard ABI extension with no compatibility guarantee
Fix this as in vector-compare-2.c .
testsuite/
* c-c++-common/vector-compare-4.c: Prune "non-standard ABI extension"
warning.
Improve TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS target hook. It turns out there
is another case where the register allocator uses the union of register classes
without checking that the cost of the resulting register class is lower than
both (see https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01765.html ). This
happens when the cost of the best and alternative class are both lower than the
memory cost. In this case we typically end up with ALL_REGS as the allocno
class, which almost invariably results in bad allocations with many redundant
int<->FP moves (which are expensive on various cores). AArch64 is affected by
this significantly due to supporting many scalar integer operations in SIMD.
Currently the TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook forces the class to
GENERAL_REGS if the allocno class is ALL_REGS and the register has an integer
mode. This is bad if the best class happens to be FP_REGS. To handle this
case as well, an extra argument is needed in the hook to pass the best class.
If the allocno class is ALL_REGS, but the best class isn't, we use the best
class instead (rather than using the mode to force to GENERAL_REGS or FP_REGS).
Previously this might happen:
r79: preferred FP_REGS, alternative GENERAL_REGS, allocno GENERAL_REGS
a1 (r79,l0) best GENERAL_REGS, allocno GENERAL_REGS
The proposed allocno is ALL_REGS (despite having the highest cost!) and is then
forced by the hook to GENERAL_REGS because r79 has integer mode. However
FP_REGS has the lowest cost. After this patch the choice is as follows:
r79: preferred FP_REGS, alternative GENERAL_REGS, allocno FP_REGS
a1 (r79,l0) best FP_REGS, allocno FP_REGS
As a result it is now no longer a requirement to use register move costs that
are larger than the memory move cost. So it will be feasible to use realistic
costs for both without a huge penalty.
2016-02-02 Wilco Dijkstra <wdijkstr@arm.com>
gcc/
* ira-costs.c (find_costs_and_classes): Add extra argument.
* target.def (ira_change_pseudo_allocno_class): Add parameter.
* targhooks.h (ira_change_pseudo_allocno_class): Likewise.
* targhooks.c (ira_change_pseudo_allocno_class): Likewise.
* config/aarch64/aarch64.c (aarch64_ira_change_pseudo_allocno_class)
Add best_class parameter, and return it if not ALL_REGS.
* config/mips/mips.c (mips_ira_change_pseudo_allocno_class):
Add parameter.
* doc/tm.texi (TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS):
Update target hook.
Wilco Dijkstra [Tue, 2 Feb 2016 17:03:05 +0000 (17:03 +0000)]
This patch adds support for the TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook.
When the cost of GENERAL_REGS and FP_REGS is identical, the register allocator
always uses ALL_REGS even when it has a much higher cost. The hook changes the
class to either FP_REGS or GENERAL_REGS depending on the mode of the register.
This results in better register allocation overall, fewer spills and reduced
codesize - particularly in SPEC2006 gamess.
2016-02-02 Wilco Dijkstra <wdijkstr@arm.com>
gcc/
* config/aarch64/aarch64.c
(TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS): New define.
(aarch64_ira_change_pseudo_allocno_class): New function.
gcc/testsuite/
* gcc.target/aarch64/scalar_shift_1.c
(test_corners_sisd_di): Improve force to SIMD register.
(test_corners_sisd_si): Likewise.
* gcc.target/aarch64/vect-ld1r-compile-fp.c:
Remove scan-assembler check for ldr.
Yuri Rumyantsev [Tue, 2 Feb 2016 09:46:26 +0000 (09:46 +0000)]
re PR middle-end/68542 (10% 481.wrf performance regression)
gcc/
2016-02-02 Yuri Rumyantsev <ysrumyan@gmail.com>
PR middle-end/68542
* config/i386/i386.c (ix86_expand_branch): Add support for conditional
branch with vector comparison.
* config/i386/sse.md (VI48_AVX): New mode iterator.
(define_expand "cbranch<mode>4): Add support for conditional branch
with vector comparison.
* tree-vect-loop.c (optimize_mask_stores): New function.
* tree-vect-stmts.c (vectorizable_mask_load_store): Initialize
has_mask_store field of vect_info.
* tree-vectorizer.c (vectorize_loops): Invoke optimaze_mask_stores for
vectorized loops having masked stores after vec_info destroy.
* tree-vectorizer.h (loop_vec_info): Add new has_mask_store field and
correspondent macros.
(optimize_mask_stores): Add prototype.
gcc/testsuite
2016-02-02 Yuri Rumyantsev <ysrumyan@gmail.com>
PR middle-end/68542
* gcc.dg/vect/vect-mask-store-move-1.c: New test.
* gcc.target/i386/avx2-vect-mask-store-move1.c: New test.
Alan Modra [Tue, 2 Feb 2016 00:01:16 +0000 (10:31 +1030)]
[RS6000] ABI_V4 init of toc section
Since 4c4a180d lto has turned off flag_pic when linking a fixed
position executable. So flag_pic is zero in rs6000_file_start.
However, when we get to actually emitting code, flag_pic may be on
again. This results in undefined references to ".LCTOC1".
PR target/68662
* config/rs6000/rs6000.c (need_toc_init): New var, set it
whenever toc_label_name used.
(rs6000_file_start): Don't set up toc section here,
(rs6000_output_function_epilogue): do so here instead,
(rs6000_xcoff_file_start): and here.
* config/rs6000/rs6000.md (load_toc_aix_si): Set need_toc_init.
(load_toc_aix_di): Likewise.
Jakub Jelinek [Mon, 1 Feb 2016 22:39:31 +0000 (23:39 +0100)]
re PR rtl-optimization/69592 (Compile-time and memory-use hog in combine)
PR rtl-optimization/69592
* rtlanal.c (nonzero_bits_binary_arith_p): New inline function.
(cached_nonzero_bits): Use it instead of ARITHMETIC_P.
(num_sign_bit_copies_binary_arith_p): New inline function.
(cached_num_sign_bit_copies): Use it instead of ARITHMETIC_P.
Jeff Law [Mon, 1 Feb 2016 22:03:57 +0000 (15:03 -0700)]
re PR testsuite/68580 (FAIL: c-c++-common/tsan/pr65400-1.c -O0 execution test)
PR tree-optimization/68580
* params.def (FSM_MAXIMUM_PHI_ARGUMENTS): New param.
* tree-ssa-threadbackward.c
(fsm_find_control_statement_thread_paths): Do not try to walk
through large PHI nodes.
Bin Cheng [Mon, 1 Feb 2016 17:17:47 +0000 (17:17 +0000)]
re PR tree-optimization/67921 ("internal compiler error: in build_polynomial_chrec, at tree-chrec.h:147" when using -fsanitize=undefined)
PR tree-optimization/67921
* fold-const.c (split_tree): New parameters. Convert pointer
type variable part to proper type before negating.
(fold_binary_loc): Pass new arguments to split_tree.
gcc/testsuite/ChangeLog
PR tree-optimization/67921
* c-c++-common/ubsan/pr67921.c: New test.
Richard Biener [Mon, 1 Feb 2016 12:39:04 +0000 (12:39 +0000)]
re PR tree-optimization/69579 (gcc ICE at -O3 and __sigsetjmp with “tree check: expected ssa_name, have integer_cst in compute_optimized_partition_bases”)
2016-02-01 Richard Biener <rguenther@suse.de>
PR tree-optimization/69579
* tree-ssa-loop-ivcanon.c (propagate_constants_for_unrolling):
Do not propagate through abnormal PHI results.
Jakub Jelinek [Mon, 1 Feb 2016 08:47:27 +0000 (09:47 +0100)]
re PR rtl-optimization/69570 (if-conversion bug on i?86)
PR rtl-optimization/69570
* ifcvt.c (bb_ok_for_noce_convert_multiple_sets): Return true only
if there is more than one set, not if there is a single set.
Paul Thomas [Sun, 31 Jan 2016 10:22:05 +0000 (10:22 +0000)]
re PR fortran/67564 (Segfault on sourced allocattion statement with class(*) arrays)
2016-01-31 Paul Thomas <pault@gcc.gnu.org>
PR fortran/67564
* trans-expr.c (gfc_conv_procedure_call): For the vtable copy
subroutines, add a string length argument, when the actual
argument is an unlimited polymorphic class object.
2016-01-31 Paul Thomas <pault@gcc.gnu.org>
PR fortran/67564
* gfortran.dg/allocate_with_source_17.f03: New test.
Jakub Jelinek [Sat, 30 Jan 2016 18:04:13 +0000 (19:04 +0100)]
re PR middle-end/69546 (wrong code with -O and simple int128 arithmetics)
PR tree-optimization/69546
* wide-int.cc (wi::divmod_internal): For unsigned division
where both operands fit into uhwi, if o1 is 1 and o0 has
msb set, if divident_prec is larger than bits per hwi,
clear another quotient word and return 2 instead of 1.
Similarly for remainder with msb in HWI set, if dividend_prec
is larger than bits per hwi.
Bill Schmidt [Sat, 30 Jan 2016 01:18:43 +0000 (01:18 +0000)]
re PR target/65546 (FAIL: gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c)
2016-01-29 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR target/65546
* gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c: Correct
condition being checked, and disable it when the target supports
misaligned loads and stores.
Martin Jambor [Fri, 29 Jan 2016 22:53:28 +0000 (23:53 +0100)]
[hsa] Atomic assess memory model fixes
2016-01-29 Martin Jambor <mjambor@suse.cz>
* hsa-gen.c (get_memory_order_name): Mask with MEMMODEL_BASE_MASK.
Use short lowercase names.
(get_memory_order): Mask with MEMMODEL_BASE_MASK. Support
MEMMODEL_CONSUME with acquire semantics and MEMMODEL_SEQ_CST with
acq_rel one. Protect warning agains segfaults if
get_memory_order_name returns NULL.
(gen_hsa_ternary_atomic_for_builtin): Support with MEMMODEL_SEQ_CST
with release semantics. Do not warn if get_memory_order already did.
(gen_hsa_insns_for_call): Support with MEMMODEL_SEQ_CST with acquire
semantics. Fix check for relaxed or acquire semantics. Do not warn
if get_memory_order already did.
Vladimir Makarov [Fri, 29 Jan 2016 18:47:17 +0000 (18:47 +0000)]
re PR target/69299 (-mavx performance degradation with r232088)
2016-01-29 Vladimir Makarov <vmakarov@redhat.com>
PR target/69299
* config/i386/constraints.md (Bm): Describe as special memory
constraint.
* doc/md.texi (DEFINE_SPECIAL_MEMORY_CONSTRAINT): Describe it.
* genoutput.c (main): Process DEFINE_SPECIAL_MEMORY_CONSTRAINT.
* genpreds.c (struct constraint_data): Add is_special_memory.
(have_special_memory_constraints, special_memory_start): New
static vars.
(special_memory_end): Ditto.
(add_constraint): Add new arg is_special_memory. Add code to
process its true value. Update have_special_memory_constraints.
(process_define_constraint): Pass the new arg.
(process_define_register_constraint): Ditto.
(choose_enum_order): Process special memory.
(write_tm_preds_h): Generate enum const CT_SPECIAL_MEMORY and
function insn_extra_special_memory_constraint.
(main): Process DEFINE_SPECIAL_MEMORY_CONSTRAINT.
* gensupport.c (process_rtx): Process
DEFINE_SPECIAL_MEMORY_CONSTRAINT.
* ira-costs.c (record_reg_classes): Process CT_SPECIAL_MEMORY.
* ira-lives.c (single_reg_class): Use
insn_extra_special_memory_constraint.
* ira.c (ira_setup_alts): Process CT_SPECIAL_MEMORY.
* lra-constraints.c (process_alt_operands): Ditto.
(curr_insn_transform): Use insn_extra_special_memory_constraint.
* recog.c (asm_operand_ok, preprocess_constraints): Process
CT_SPECIAL_MEMORY.
* reload.c (find_reloads): Ditto.
* rtl.def (DEFINE_SPECIFAL_MEMORY_CONSTRAINT): New.
* stmt.c (parse_input_constraint): Use
insn_extra_special_memory_constraint.
Jakub Jelinek [Fri, 29 Jan 2016 14:14:56 +0000 (15:14 +0100)]
re PR target/69551 (Wrong code with single element vector insert)
PR target/69551
* config/i386/i386.c (ix86_expand_vector_set) <case V4SImode>: For
SSE1, copy target into the temporary reg first before recursing
on it.
Andrew Bennett [Fri, 29 Jan 2016 13:54:53 +0000 (13:54 +0000)]
p5600-bonding.c (dg-options): Force the test to be always built for p5600.
testsuite/
2016-01-29 Andrew Bennett <andrew.bennett@imgtec.com>
* gcc.target/mips/p5600-bonding.c (dg-options): Force the test to be
always built for p5600.
* gcc.target/mips/mips.exp (mips-dg-options): Add support for the
isa=p5600 dg-option.
Richard Biener [Fri, 29 Jan 2016 11:21:19 +0000 (11:21 +0000)]
re PR middle-end/69547 (no-op array initializer emits an empty loop)
2016-01-29 Richard Biener <rguenther@suse.de>
PR tree-optimization/69547
* tree-ssa-dce.c (mark_aliased_reaching_defs_necessary_1):
Do not mark clobbers necessary.
(mark_all_reaching_defs_necessary_1): Likewise.
Dominik Vogt [Fri, 29 Jan 2016 10:09:13 +0000 (10:09 +0000)]
S/390: Require a hardware vector support for test to succeed.
The test case works on S/390 too, but only with -march=z13 or later
(i.e. if Gcc can make use of hardware vector support). Otherwise the
optimization gets too complex. The attached patch forces Gcc to use
-march=z13 instead of xfail'ing the test on S/390.
gcc/testsuite/ChangeLog
* gcc.dg/tree-ssa/ssa-dom-cse-2.c: Require a hardware vector support for
test to succeed.
Marek Polacek [Fri, 29 Jan 2016 09:25:14 +0000 (09:25 +0000)]
re PR c++/69509 (infinite loop compiling a VLA in a recursive constexpr function)
PR c++/69509
PR c++/69516
* constexpr.c (cxx_eval_array_reference): Give the "array subscript
out of bound" error earlier.
* init.c (build_vec_init): Change NE_EXPR into GT_EXPR. Update the
commentary.
* g++.dg/ext/constexpr-vla2.C: New test.
* g++.dg/ext/constexpr-vla3.C: New test.
* g++.dg/ubsan/vla-1.C: Remove dg-shouldfail.
Patrick Palka [Fri, 29 Jan 2016 01:51:03 +0000 (01:51 +0000)]
Fix cp_binding_level reuse logic
gcc/cp/ChangeLog:
* name-lookup.c (begin_scope): After reusing a cp_binding_level
structure, update free_binding_level before the structure's
level_chain field gets cleared, not after.