Uros Bizjak [Sun, 14 Mar 2021 17:51:14 +0000 (18:51 +0100)]
i386: Some more -mavx512vl -mno-avx512bw fixes [PR99321]
2021-03-14 Uroš Bizjak <ubizjak@gmail.com>
gcc/
* config/i386/sse.md (*vec_extract<mode>): Merge alternative 0 with
alternative 2 and alternative 1 with alternative 3 using
YW register constraint.
(*vec_extract<PEXTR_MODE12:mode>_zext): Merge alternatives
using YW register constraint.
(*vec_extractv16qi_zext): Ditto.
(*vec_extractv4si): Merge alternatives 4 and 5
using Yw register constraint.
(*ssse3_palignr<mode>_perm): Use Yw instead of v for alternative 3.
Paul Thomas [Sat, 13 Mar 2021 11:39:57 +0000 (11:39 +0000)]
Fortran: Fix for class defined operators [PR99125].
2021-03-13 Paul Thomas <pault@gcc.gnu.org>
gcc/fortran
PR fortran/99125
* trans-array.c (gfc_conv_expr_descriptor): For deferred length
length components use the ss_info string length instead of
gfc_get_expr_charlen. Make sure that the deferred string length
is a variable before assigning to it. Otherwise use the expr.
* trans-expr.c (gfc_conv_string_length): Make sure that the
deferred string length is a variable before assigning to it.
gcc/testsuite/
PR fortran/99125
* gfortran.dg/alloc_deferred_comp_1.f90: New test.
Jakub Jelinek [Sat, 13 Mar 2021 07:56:15 +0000 (08:56 +0100)]
match.pd: Don't optimize vector X + (X << C) -> X * (1 + (1 << C)) if there is no mult support [PR99544]
E.g. on aarch64, the target has V2DImode addition and shift by scalar
optabs, but doesn't have V2DImode multiply. The following testcase
ICEs because this simplification is done after last lowering, but
generally, even if it is done before that, turning it into a multiplication
will not be an improvement because that means scalarization, while the former
can be done in vectors.
It would be nice if we added expansion support for vector multiplication
by uniform constants using shifts and additions like we have for scalar
multiplication, but that is something that can be done in stage1.
2021-03-13 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/99544
* match.pd (X + (X << C) -> X * (1 + (1 << C))): Don't simplify
if for vector types multiplication can't be done in type's mode.
Mike Frysinger [Sun, 28 Feb 2021 06:43:21 +0000 (01:43 -0500)]
sim: drop dep on configure-gdb
I'm not entirely sure why this is here since the sim doesn't use
anything from the gdb/ dir directly, and the commit that added it
included a bunch more changes and doesn't seem to call out this
dep specifically.
ChangeLog:
* Makefile.def: Remove all-sim dependency on configure-gdb.
* Makefile.in: Regenerated.
Nathan Sidwell [Fri, 12 Mar 2021 17:02:41 +0000 (09:02 -0800)]
c++: ICE with using-decl [PR 99238]
This ICE was caused by a stray TREE_VISITED marker. The lookup
machinery was leaving it there due to the way I'd arranged for it to
be cleared. That was presuming the name_lookup::value field didn't
change, and that wasn't always true in the using-decl processing. I
took the opportunity to break out a helper, and then call it
immediately after lookups, rather than wait until destructor time.
Added some asserts the module machinery to catch further cases of
this.
Eric Botcazou [Fri, 12 Mar 2021 16:07:20 +0000 (17:07 +0100)]
Fix memory constraint bug in SPARC back-end
It's a bug exposed by the recent LRA changes, whereby the T constraint
fails to behave properly when LRA is enabled (unlike when reload is
enabled). The patch also gets rid of the awkward W constraint, which
is strictly equivalent to m in 64-bit mode and, as a result, renames
the w constraint into W.
gcc/
PR target/99422
* config/sparc/constraints.md (w): Rename to...
(W): ... this and ditch previous implementation.
* config/sparc/sparc.md (*movdi_insn_sp64): Replace W with m.
(*movdf_insn_sp64): Likewise.
(*mov<VM64:mode>_insn_sp64): Likewise.
* config/sparc/sync.md (*atomic_compare_and_swap<mode>_1): Replace
w with W.
(atomic_compare_and_swap_leon3_1): Likewise.
(*atomic_compare_and_swapdi_v8plus): Likewise.
* config/sparc/sparc.c (memory_ok_for_ldd): Remove useless test on
architecture and add missing address validity check during LRA.
Tobias Burnus [Fri, 12 Mar 2021 15:31:32 +0000 (16:31 +0100)]
Fortran: Fix libgfortran I/O race with newunit_free [PR99529]
libgfortran/ChangeLog:
* io/transfer.c (st_read_done_worker, st_write_done_worker):
Call unlock_unit here, add unit_lock lock around newunit_free call.
(st_read_done, st_write_done): Only call unlock_unit when not
calling the worker function.
* io/unit.c (set_internal_unit): Don't reset the unit_number
to the same number as this cause race warnings.
Jakub Jelinek [Fri, 12 Mar 2021 13:34:32 +0000 (14:34 +0100)]
i386: Hopefully last set of -mavx512vl -mno-avx512bw fixes [PR99321]
This is the final patch of the series started with
https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566139.html
and continued with
https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566356.html
This time, I went through all the remaining instructions marked
by gas as requiring both AVX512BW and AVX512VL and for each checked
tmp-mddump.md, figure out if it ever could be a problem (e.g. instructions
that require AVX512BW+AVX512VL, but didn't exist before AVX512F are usually
fine, the patterns have the right conditions, the bugs are typically on
pre-AVX512F patterns where we have just blindly added v while they actually
can't access those unless AVX512BW+AVX512VL), added test where possible
(the test doesn't cover MMX though)and fixed md bugs.
For mmx pextr[bw]/pinsr[bw] patterns it introduces per discussions
a new YW constraint that only requires AVX512BW and not AVX512VL, because
those instructions only require the former and not latter when using EVEX
encoding.
There are some other interesting details, e.g. most of the 8 interleave
patterns (vpunck[hl]{bw,wd}) had correctly
&& <mask_avx512vl_condition> && <mask_avx512bw_condition>
in the conditions because for masking it needs to be always EVEX encoded
and then it needs both VL+BW, but 2 of those 8 had just
&& <mask_avx512vl_condition>
and so again would run into the -mavx512vl -mno-avx512bw problems.
Another problem different from others was mmx eq/gt comparisons, that was
using Yv constraints, so would happily accept %xmm16+ registers for
-mavx512vl, but there actually are no such EVEX encoded instructions,
as AVX512 comparisons work with %k* registers instead.
PR target/99321
* config/i386/constraints.md (YW): New internal constraint.
* config/i386/sse.md (v_Yw): Add V4TI, V2TI, V1TI and TI cases.
(*<sse2_avx2>_<insn><mode>3<mask_name>,
*<sse2_avx2>_uavg<mode>3<mask_name>, *abs<mode>2,
*<s>mul<mode>3_highpart<mask_name>): Use <v_Yw> instead of v in
constraints.
(<sse2_avx2>_psadbw): Use YW instead of v in constraints.
(*avx2_pmaddwd, *sse2_pmaddwd, *<code>v8hi3, *<code>v16qi3,
avx2_pmaddubsw256, ssse3_pmaddubsw128): Merge last two alternatives
into one, use Yw instead of former x,v.
(ashr<mode>3, <insn><mode>3): Use <v_Yw> instead of x in constraints of
the last alternative.
(<sse2_avx2>_packsswb<mask_name>, <sse2_avx2>_packssdw<mask_name>,
<sse2_avx2>_packuswb<mask_name>, <sse4_1_avx2>_packusdw<mask_name>,
*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>, <ssse3_avx2>_palignr<mode>,
<ssse3_avx2>_pshufb<mode>3<mask_name>): Merge last two alternatives
into one, use <v_Yw> instead of former x,v.
(avx2_interleave_highv32qi<mask_name>,
vec_interleave_highv16qi<mask_name>): Use Yw instead of v in
constraints. Add && <mask_avx512bw_condition> to condition.
(avx2_interleave_lowv32qi<mask_name>,
vec_interleave_lowv16qi<mask_name>,
avx2_interleave_highv16hi<mask_name>,
vec_interleave_highv8hi<mask_name>,
avx2_interleave_lowv16hi<mask_name>, vec_interleave_lowv8hi<mask_name>,
avx2_pshuflw_1<mask_name>, sse2_pshuflw_1<mask_name>,
avx2_pshufhw_1<mask_name>, sse2_pshufhw_1<mask_name>,
avx2_<code>v16qiv16hi2<mask_name>, sse4_1_<code>v8qiv8hi2<mask_name>,
*sse4_1_<code>v8qiv8hi2<mask_name>_1, <sse2_avx2>_<insn><mode>3): Use
Yw instead of v in constraints.
* config/i386/mmx.md (Yv_Yw): New define_mode_attr.
(*mmx_<insn><mode>3, mmx_ashr<mode>3, mmx_<insn><mode>3): Use <Yv_Yw>
instead of Yv in constraints.
(*mmx_<insn><mode>3, *mmx_mulv4hi3, *mmx_smulv4hi3_highpart,
*mmx_umulv4hi3_highpart, *mmx_pmaddwd, *mmx_<code>v4hi3,
*mmx_<code>v8qi3, mmx_pack<s_trunsuffix>swb, mmx_packssdw,
mmx_punpckhbw, mmx_punpcklbw, mmx_punpckhwd, mmx_punpcklwd,
*mmx_uavgv8qi3, *mmx_uavgv4hi3, mmx_psadbw): Use Yw instead of Yv in
constraints.
(*mmx_pinsrw, *mmx_pinsrb, *mmx_pextrw, *mmx_pextrw_zext, *mmx_pextrb,
*mmx_pextrb_zext): Use YW instead of Yv in constraints.
(*mmx_eq<mode>3, mmx_gt<mode>3): Use x instead of Yv in constraints.
(mmx_andnot<mode>3, *mmx_<code><mode>3): Split last alternative into
two, one with just x, another isa avx512vl with v.
Jakub Jelinek [Fri, 12 Mar 2021 09:11:24 +0000 (10:11 +0100)]
c++: Fix up calls to immediate functions returning reference [PR99507]
build_cxx_call calls convert_from_reference at the end, so if an immediate
function returns a reference, we were constant evaluating not just that
call, but that call wrapped in an INDIRECT_REF. That unfortunately means
it can constant evaluate to something non-addressable, so if code later
needs to take its address it will fail.
The following patch fixes that by undoing the convert_from_reference
wrapping for the cxx_constant_value evaluation and readdding it ad the end.
2021-03-12 Jakub Jelinek <jakub@redhat.com>
PR c++/99507
* call.c (build_over_call): For immediate evaluation of functions
that return references, undo convert_from_reference effects before
calling cxx_constant_value and call convert_from_reference
afterwards.
Ian Lance Taylor [Thu, 11 Mar 2021 03:38:21 +0000 (19:38 -0800)]
compiler: create temporaries for heap variables
The compiler generally doesn't create a temporary for an expression
that is a variable, because it's normally valid to simply reload the
value from the variable. However, if the variable is in the heap,
then loading the value is a pointer indirection. The process of
creating GCC IR can cause the variable load and the pointer
indirection to be split, such that the second evaluation only does the
pointer indirection. If there are conditionals in between the two
uses, this can cause the second use to load the pointer from an
uninitialized register.
Avoid this by introducing a new Expression method that returns whether
it is safe to evaluate an expression multiple times, and use it
everywhere.
David Malcolm [Thu, 11 Mar 2021 22:46:37 +0000 (17:46 -0500)]
analyzer: new implementation of shortest feasible path [PR96374]
The analyzer builds an exploded graph of (point,state) pairs and when
it finds a problem, records a diagnostic at the relevant exploded node.
Once it has finished exploring the graph, the analyzer needs to generate
the shortest feasible path through the graph to each diagnostic's node.
This is used:
- for rejecting diagnostics that are infeasible (due to impossible sets
of constraints),
- for use in determining which diagnostic to use in each deduplication
set (the one with the shortest path), and
- for building checker_paths for the "winning" diagnostics, giving a
list of events
Prior to this patch the analyzer simply found the shortest path to the
node, and then checked it for feasibility, which could lead to falsely
rejecting diagnostics: "the shortest path, if feasible" is not the same
as "the shortest feasible path" (PR analyzer/96374).
An example is PR analyzer/93355, where this issue causes the analyzer
to fail to emit a leak warning for a missing fclose on an error-handling
path in intl/localealias.c.
This patch implements a new algorithm for finding the shortest feasible
path to an exploded node: instead of simply finding the shortest path,
the new algorithm uses a worklist to iteratively build a tree of path
prefixes, which are feasible paths by construction, until a path to the
target node is found. The worklist is prioritized, so that the first
feasible path discovered is the shortest possible feasible path. The
algorithm continues trying paths until the target node is reached or a
limit is exceeded, in which case the diagnostic is treated as being
infeasible (which could still be a false negative, but is much less
likely to happen than before). Iteratively building a tree of paths
allows for work to be reused, and the tree can be dumped in .dot form
(via a new -fdump-analyzer-feasibility option), making it much easier to
debug compared to other approaches I tried.
Doing so fixes the missing leak warning for PR analyzer/93355 and
various other test cases.
Testing:
- I manually verified that the behavior is determistic using 50 builds
of pr93355-localealias.c. All dumps were identical.
- I manually verified that it still builds with --disable-analyzer.
- Lightly tested with valgrind; no additional issues.
- Lightly performance tested, showing a slight speed regression to the
analyzer relative to before the patch, but correctness for this issue
is more important than the slight performance hit for the analyzer.
gcc/ChangeLog:
PR analyzer/96374
* Makefile.in (ANALYZER_OBJS): Add analyzer/feasible-graph.o and
analyzer/trimmed-graph.o.
* doc/analyzer.texi (Analyzer Paths): Rewrite description of
feasibility checking to reflect new implementation.
* doc/invoke.texi (-fdump-analyzer-feasibility): Document new
option.
* shortest-paths.h (shortest_paths::get_shortest_distance): New.
gcc/analyzer/ChangeLog:
PR analyzer/96374
* analyzer.opt (-param=analyzer-max-infeasible-edges=): New param.
(fdump-analyzer-feasibility): New flag.
* diagnostic-manager.cc: Include "analyzer/trimmed-graph.h" and
"analyzer/feasible-graph.h".
(epath_finder::epath_finder): Convert m_sep to a pointer and
only create it if !flag_analyzer_feasibility.
(epath_finder::~epath_finder): New.
(epath_finder::m_sep): Convert to a pointer.
(epath_finder::get_best_epath): Add param "diag_idx" and use it
when logging. Rather than finding the shortest path and then
checking feasibility, instead use explore_feasible_paths unless
!flag_analyzer_feasibility, in which case simply use the shortest
path, and note if it is infeasible. Update for m_sep becoming a
pointer.
(class feasible_worklist): New.
(epath_finder::explore_feasible_paths): New.
(epath_finder::process_worklist_item): New.
(class dump_eg_with_shortest_path): New.
(epath_finder::dump_trimmed_graph): New.
(epath_finder::dump_feasible_graph): New.
(saved_diagnostic::saved_diagnostic): Add "idx" param, using it
on new field m_idx.
(saved_diagnostic::to_json): Dump m_idx.
(saved_diagnostic::calc_best_epath): Pass m_idx to get_best_epath.
Remove assertion that m_problem was set when m_best_epath is NULL.
(diagnostic_manager::add_diagnostic): Pass an index when created
saved_diagnostic instances.
* diagnostic-manager.h (saved_diagnostic::saved_diagnostic): Add
"idx" param.
(saved_diagnostic::get_index): New accessor.
(saved_diagnostic::m_idx): New field.
* engine.cc (exploded_node::dump_dot): Call args.dump_extra_info.
Move code to...
(exploded_node::dump_processed_stmts): ...this new function and...
(exploded_node::dump_saved_diagnostics): ...this new function.
Add index of each diagnostic.
(exploded_edge::dump_dot): Move bulk of code to...
(exploded_edge::dump_dot_label): ...this new function.
* exploded-graph.h (eg_traits::dump_args_t::dump_extra_info): New
vfunc.
(exploded_node::dump_processed_stmts): New decl.
(exploded_node::dump_saved_diagnostics): New decl.
(exploded_edge::dump_dot_label): New decl.
* feasible-graph.cc: New file.
* feasible-graph.h: New file.
* trimmed-graph.cc: New file.
* trimmed-graph.h: New file.
David Malcolm [Thu, 11 Mar 2021 22:45:10 +0000 (17:45 -0500)]
analyzer: support reverse direction in shortest-paths.h
This patch generalizes shortest-path.h so that it can be used to
find the shortest path from each node to a given target node (on top
of the existing support for finding the shortest path from a given
origin node to each node).
I've marked this as "analyzer" as this is the only code using
shortest-paths.h.
This patch is required by followup work to fix PR analyzer/96374.
gcc/analyzer/ChangeLog:
* diagnostic-manager.cc (epath_finder::epath_finder):
Update shortest_paths init for new param.
gcc/ChangeLog:
* digraph.cc (selftest::test_shortest_paths): Update
shortest_paths init for new param. Add test of
SPS_TO_GIVEN_TARGET.
* shortest-paths.h (enum shortest_path_sense): New.
(shortest_paths::shortest_paths): Add "sense" param.
Update for renamings. Generalize to use "sense" param.
(shortest_paths::get_shortest_path): Rename param.
(shortest_paths::m_sense): New field.
(shortest_paths::m_prev): Rename...
(shortest_paths::m_best_edge): ...to this.
(shortest_paths::get_shortest_path): Update for renamings.
Conditionalize flipping of path on sense of traversal.
David Malcolm [Thu, 11 Mar 2021 22:43:39 +0000 (17:43 -0500)]
analyzer: gracefully handle impossible paths in shortest-paths.h
This bulletproofs the shortest_paths code against unreachable nodes,
gracefully handling them, rather than failing an assertion.
I've marked this as "analyzer" as this is the only code using
shortest-paths.h.
This patch is required by followup work to fix PR analyzer/96374.
gcc/ChangeLog:
* digraph.cc (selftest::test_shortest_paths): Add test coverage
for paths from B and C.
* shortest-paths.h (shortest_paths::shortest_paths): Handle
unreachable nodes, rather than asserting.
Patrick Palka [Thu, 11 Mar 2021 22:02:27 +0000 (17:02 -0500)]
libstdc++: Add a fallback 128-bit integer class type and use it
This implements a minimal integer class type that emulates 128-bit
unsigned arithmetic using a pair of 64-bit integers, which the
floating-point std::to_chars implementation then uses as a drop-in
replacement for unsigned __int128 on targets that lack the latter.
After this patch, we now fully support formatting of large long double
types on such targets.
Since Ryu performs 128-bit division/modulus only by 2, 5 and 10, this
integer class type supports only these divisors rather than general
division/modulus.
libstdc++-v3/ChangeLog:
* src/c++17/floating_to_chars.cc: Simplify the file as if
__SIZEOF_INT128__ is always defined.
[!defined __SIZEOF_INT128__]: Include "uint128_t.h". Define
a base-10 to_chars overload for the uint128_t class type.
* src/c++17/uint128_t.h: New file.
* testsuite/20_util/to_chars/long_double.cc: No longer expect an
execution FAIL on targets that have a large long double type
but lack __int128.
Patrick Palka [Thu, 11 Mar 2021 21:57:49 +0000 (16:57 -0500)]
libstdc++: Factor out uses of __int128 into a type alias
Since Ryu has the alias uint128_t for this same purpose, it seems best
for us to use this name as well, so as to minimize the amount of local
modifications we'd need to make to our copy of Ryu. (In a subsequent
patch, we're going to remove Ryu's aliases so that it uses this one
defined in floating_to_chars.cc.)
libstdc++-v3/ChangeLog:
* src/c++17/floating_to_chars.cc (uint128_t): New conditionally
defined alias of unsigned __int128.
(floating_type_traits_binary128::mantissa_t): Use uint128_t
instead of unsigned __int128.
(floating_type_traits<long double>::mantissa_t)
[LONG_DOUBLE_KIND == LDK_IBM128]: Likewise.
(get_ieee_repr): Likewise. Make casts from uint_t to mantissa_t
and uint32_t explicit. Simplify the extraction of mantissa,
exponent and sign bit.
David Edelsohn [Thu, 11 Mar 2021 16:41:24 +0000 (11:41 -0500)]
aix: Use lcomm for TLS static data.
GCC on AIX generates thread local uninitialized data in the common section,
which could conflict with another module.
This patch changes the code generation to place static uninitialized
thread local data into the local common section specified with .lcomm.
This change also removes the need to create a file-local name for the TBSS
data.
Nathan Sidwell [Thu, 11 Mar 2021 21:06:36 +0000 (13:06 -0800)]
c++: Fix unhiding friend with imports [PR 99248]
This was a simple thinko about which object held the reference to the
binding vector. I also noticed stale code in the tree dumper, as I
recently removed the flags from a lazy number.
PR c++/99248
gcc/cp/
* name-lookup.c (lookup_elaborated_type_1): Access slot not bind
when there's a binding vector.
* ptree.c (cxx_print_xnode): Lazy flags are no longer a thing.
gcc/testsuite/
* g++.dg/modules/pr99248.h: New.
* g++.dg/modules/pr99248_a.H: New.
* g++.dg/modules/pr99248_b.H: New.
Jonathan Wakely [Thu, 11 Mar 2021 16:57:20 +0000 (16:57 +0000)]
libstdc++: Make barrier::arrival_token a move-only class type
The standard only specifies that barrier::arrival_token is a move
constructible and move assignable type. We originally used a scoped enum
type, but that means we do not diagnose non-portable code that makes
copies of arrival tokens (or compares them for equality, or uses them as
keys in map!) This wraps the enum in a move-only class type, so that
users are forced to pass it correctly.
The move constructor and move assignment operator of the new class do
not zero out the moved-from token, as that would add additional
instructions. That means that passing a moved-from token will work with
our implementation, despite being a bug in the user code. We could
consider doing that zeroing out in debug mode.
libstdc++-v3/ChangeLog:
* include/std/barrier (barrier::arrival_token): New move-only
class that encapsulates the underlying token value.
Jonathan Wakely [Thu, 11 Mar 2021 16:48:32 +0000 (16:48 +0000)]
libstdc++: Fix find_type helper to work consistently
The find_type helper function sometimes results in "class X::name" and
lookup for that fails. For more details see "Problem 1" in
https://gcc.gnu.org/pipermail/libstdc++/2021-March/052132.html and the
example at https://sourceware.org/bugzilla/show_bug.cgi?id=27510#c2
This patch replaces typ.unqualified() with typ.tag, which is never
qualified, and will never include the 'class' or 'struct' keywords.
Using the .tag attribute should be safe here because we know we are
looking at a class type and we've already used strip_typedefs().
libstdc++-v3/ChangeLog:
* python/libstdcxx/v6/printers.py (find_type): Use tag attribute
instead of unqualified() method.
Jonathan Wakely [Thu, 11 Mar 2021 16:44:57 +0000 (16:44 +0000)]
libstdc++: Use acq_rel memory ordering [PR 99537]
As Lewis Baker wrote in the PR:
> The 'fetch_sub()' operation in _M_release_ownership() should be using
> memory_order::acq_rel instead of memory_order::release. The use of
> 'release' only is insufficient as it does not synchronise with any
> corresponding 'acquire' operation.
> With the current implementation, it's possible that a prior write to
> one of the _M_value or _M_head data-members by a thread releasing the
> second-to-last reference might not be visible to another thread that
> releases the last reference and frees the memory, resulting in
> potential write to freed memory.
This simply changes the memory order to acq_rel as suggested.
libstdc++-v3/ChangeLog:
PR libstdc++/99537
* include/std/stop_token (_Stop_state_t::_M_release_ownership):
Use acq_rel memory ordering.
Jonathan Wakely [Thu, 11 Mar 2021 16:43:51 +0000 (16:43 +0000)]
libstdc++: Handle EPERM for filesystem access errors on MacOS [PR 99537]
Contrary to what POSIX says, some directory operations on MacOS can fail
with EPERM instead of EACCES, so we need to handle both.
libstdc++-v3/ChangeLog:
PR libstdc++/99537
* src/c++17/fs_dir.cc (recursive_directory_iterator): Use new
helper function to check for permission denied errors.
* src/filesystem/dir.cc (recursive_directory_iterator):
Likewise.
* src/filesystem/dir-common.h (is_permission_denied_error): New
helper function.
This turned out to be an existing problem, which had been hidden by
other bugs. Templated members of templated classes can end up
instantiating the template itself, and we were not handling the
mergeableness of that correctly.
Richard Biener [Thu, 11 Mar 2021 13:11:08 +0000 (14:11 +0100)]
testsuite/97494 - XFAIL gcc.dg/vect/pr97428.c on !vect_hw_misalign
While we could at least vectorize it on targets which support
re-alignment tokens we fail to do this because of imperfections in
alignment analysis. XFAIL when the HW cannot deal with misaligned
vector accesses for now.
2021-03-11 Richard Biener <rguenther@suse.de>
PR testsuite/97494
* gcc.dg/vect/pr97428.c: XFAIL on !vect_hw_misalign.
Richard Biener [Thu, 11 Mar 2021 09:09:43 +0000 (10:09 +0100)]
tree-optimization/99523 - missing SSA decls in dumps
This makes sure to dump SSA names without identifier in the
declaration part of a function dump. While we dump the
anonymous variable decls the SSA names referencing them appear
without a clear reference as to what anonymous variable is used
(_3 vs. D.1234).
2021-03-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/99523
* tree-cfg.c (dump_function_to_file): Dump SSA names
w/o identifier to the decls section as well, not only those
without a VAR_DECL.
Jakub Jelinek [Thu, 11 Mar 2021 09:59:18 +0000 (10:59 +0100)]
icf: Check return type of internal fn calls [PR99517]
The following testcase is miscompiled, because IPA-ICF considers the two
functions identical. They aren't, the types of the .VEC_CONVERT call
lhs is different. But for calls to internal functions, there is no
fntype nor callee with a function type to compare, so all we compare
is just the ifn, arguments and some call flags.
The following patch fixes it by checking the internal fn calls like e.g. gimple
assignments where the type of the lhs is checked too.
2021-03-11 Jakub Jelinek <jakub@redhat.com>
PR ipa/99517
* ipa-icf-gimple.c (func_checker::compare_gimple_call): For internal
function calls with lhs fail if the lhs don't have compatible types.
* gcc.target/i386/avx2-pr99517-1.c: New test.
* gcc.target/i386/avx2-pr99517-2.c: New test.
Beware, tm.texi doesn't tell the whole story: a defined
HARD_FRAME_POINTER_REGNUM (different to FRAME_POINTER_REGNUM) is
supposed to make work easier for reload, being able to easily
tell actual frame-pointer-related addresses from those that
happen to use the same register or something to that effect.
On reasonable code the performance effect is barely measurable.
Looking at libgcc changes for -march=v10, the effect (where
noticeable) is mostly indeterminate churn. Instances where it's
not just insns moved around at no obvious effect: one more insn
for addvdi3, subvdi3; two insns more in floatdisf; three insns
shorter fixunsdfdi. Some of those seem related to pairing r8
with r9. The only effect on coremark is an infinitesimal
positive effect from a three(!) cycles total (from the 15 calls)
faster execution paths in vfprintf_r. Local microbenchmarks
give similar results. With that in mind and not forgetting that
expectations in the register allocator and reload leaning
towards HARD_FRAME_POINTER_REGNUM defined (and different to)
FRAME_POINTER_REGNUM or to wit, "all the kids do it", why not.
Note that the offset at elimination really is 0.
gcc:
* config/cris/cris.h (HARD_FRAME_POINTER_REGNUM): Define.
Change FRAME_POINTER_REGNUM to correspond to a new faked
register faked_fp, part of GENNONACR_REGS like faked_ap.
(CRIS_FAKED_REGS_CONTENTS): New helper macro.
(FIRST_PSEUDO_REGISTER, FIXED_REGISTERS, CALL_USED_REGISTERS):
(REG_ALLOC_ORDER, REG_CLASS_CONTENTS, REGNO_OK_FOR_BASE_P)
(ELIMINABLE_REGS, REGISTER_NAMES): Adjust accordingly.
* config/cris/cris.md (CRIS_FP_REGNUM): Renumber to new faked
register.
(CRIS_REAL_FP_REGNUM): New constant.
* config/cris/cris.c (cris_reg_saved_in_regsave_area): Check
for HARD_FRAME_POINTER_REGNUM instead of FRAME_POINTER_REGNUM.
(cris_initial_elimination_offset): Handle elimination changes
to HARD_FRAME_POINTER_REGNUM instead of FRAME_POINTER_REGNUM
and add one from FRAME_POINTER_REGNUM to
HARD_FRAME_POINTER_REGNUM.
(cris_expand_prologue, cris_expand_epilogue): Emit code for
hard_frame_pointer_rtx instead of frame_pointer_rtx.
David Edelsohn [Tue, 9 Mar 2021 22:52:36 +0000 (17:52 -0500)]
aix: align double complex
AIX word-aligns floating point doubles. This behavior also extends to
double _Complex, which had been overlooked when compiler support for
double _Complex was added.
This patch adds DCmode to the modes whose alignment is adjusted and
adds a testcase to confirm the correct alignment.
Harald Anlauf [Wed, 10 Mar 2021 21:59:50 +0000 (22:59 +0100)]
PR fortran/99205 - Out of memory with undefined character length
A character variable appearing as a data statement object cannot
be automatic, thus it shall have constant length.
gcc/fortran/ChangeLog:
PR fortran/99205
* data.c (gfc_assign_data_value): Reject non-constant character
length for lvalue.
* trans-array.c (gfc_conv_array_initializer): Restrict loop to
elements which are defined to avoid NULL pointer dereference.
gcc/testsuite/ChangeLog:
PR fortran/99205
* gfortran.dg/data_char_4.f90: New test.
* gfortran.dg/data_char_5.f90: New test.
Nathan Sidwell [Wed, 10 Mar 2021 20:07:24 +0000 (12:07 -0800)]
c++: ICE do to GC leakage [PR 99423]
My reworking of pending-entity loading introduced a GC problem. The
post-load processing needs to inhibit GCs (that would otherwise occur
in clone_decl). That wasn't happening on one code path, leading to
dangling pointers in the active call frames.
PR c++/99423
gcc/cp/
* module.cc (post_load_processing): Assert not gcable.
(laxy_load_pendings): Extend no-gc region around
post_load_processing.
gcc/testsuite/
* g++.dg/modules/pr99423_a.H: New.
* g++.dg/modules/pr99423_b.H: New.
David Malcolm [Wed, 10 Mar 2021 17:02:07 +0000 (12:02 -0500)]
analyzer: factor out new class feasibility_state
As preparatory work for a fix to PR analyzer/96374, this patch
moves the core state-update logic from the loop in
exploded_path::feasible_p into a new class feasibility_state.
No functional change intended.
gcc/analyzer/ChangeLog:
PR analyzer/96374
* engine.cc (exploded_path::feasible_p): Move "snodes_visited" and
"model" locals into a new class feasibility_state. Move heart
of per-edge processing into
feasibility_state::maybe_update_for_edge.
(feasibility_state::feasibility_state): New.
(feasibility_state::maybe_update_for_edge): New, based on loop
body in exploded_path::feasible_p.
* exploded-graph.h (class feasibility_state): New.
Jakub Jelinek [Wed, 10 Mar 2021 16:40:25 +0000 (17:40 +0100)]
testsuite: Fix up pr99305.C test on unsigned_char targets [PR99498]
On unsigned_char targets, the cast stmt to unsigned char is obviously
not needed (and shouldn't be there). But it doesn't hurt to test
the rest also on targets where char is unsigned.
2021-03-10 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/99305
PR testsuite/99498
* g++.dg/opt/pr99305.C: Don't expect cast to unsigned char on
unsigned_char effective targets.
Nathan Sidwell [Wed, 10 Mar 2021 15:39:51 +0000 (07:39 -0800)]
c++: Propagate assembler name from local-externs [PR 99508]
This is another place where our one-true-decl representation breaks
down. The fix here propagates the assembly name to the ns-scope
alias. that fixes the reported problem but changes the behaviour when
the user has explicitly declared the entity in its namespace.
However, we didn't handle that case 'correctly' anyway before.
Previously we'd also ignore the explicitly specified assembler name,
now we propagate it. It's not clear to me what the desired semantics
would be in decorating just one of the local extern declarations this
way. I don't think we can really do better without propagating this
aliasing property into the middle end (which is also needed for some
constexpr handling, see PR97306). I tried that before and it turned
into a rat-hole.
PR c++/99508
gcc/cp/
* decl.c (make_rtl_for_nonlocal_decl): Propagate local-extern's
assembler name to the ns alias.
gcc/testsuite/
* g++.dg/ext/pr99508.C: New.
Jonathan Wakely [Wed, 10 Mar 2021 15:27:41 +0000 (15:27 +0000)]
libstdc++: Fix headers that can't be used as header units [PR 99413]
This adds missing includes to internal library headers which get
included from more than one other header, so that they can be compiled
as a stand-alone header unit.
For existing use cases these includes are no-ops because they're already
done by the header that includes these files. For compiling them as a
header unit, this ensures that they include what they use.
libstdc++-v3/ChangeLog:
PR libstdc++/99413
* include/bits/align.h: Include debug/assertions.h.
* include/bits/codecvt.h: Include bits/c++config.h.
* include/bits/enable_special_members.h: Likewise.
* include/bits/erase_if.h: Likewise.
* include/bits/functional_hash.h: Include <type_traits>.
* include/bits/invoke.h: Include bits/move.h.
* include/bits/ostream_insert.h: Include bits/exception_defines.h.
* include/bits/parse_numbers.h: Include <type_traits>.
* include/bits/predefined_ops.h: Include bits/c++config.h.
* include/bits/range_access.h: Include bits/stl_iterator.h.
* include/bits/stl_bvector.h: Do not include bits/stl_vector.h.
* include/bits/stl_iterator.h: Include bits/stl_iterator_base_types.h.
* include/bits/stl_uninitialized.h: Include bits/stl_algobase.h.
* include/bits/uniform_int_dist.h: Include bits/concept_check.h.
* include/bits/unique_lock.h: Include bits/std_mutex.h.
* include/debug/assertions.h: Include bits/c++config.h.
Jonathan Wakely [Wed, 10 Mar 2021 15:27:06 +0000 (15:27 +0000)]
libstdc++: Implement LWG 3530 for concept-constrained comparisons
The proposed resolution for this library issue simplifies the
constraints for compare_three_way, ranges::equal_to, ranges::less etc.
so that they do not work with types which are convertible to pointers
but which fail to meet the usual syntactic requirements for the
comparisons.
This affects the example in PR libstdc++/93628 but doesn't fix the
problem described in that report.
libstdc++-v3/ChangeLog:
* include/bits/ranges_cmp.h (__eq_builtin_ptr_cmp): Remove.
(ranges::equal_to, ranges::not_equal_to): Do not constrain
with __eq_builtin_ptr_cmp.
(ranges::less, ranges::greater, ranges::less_equal)
(ranges::greater_equal): Do not constrain with
__less_builtin_ptr_cmp.
* libsupc++/compare (compare_three_way): Do not constrain with
__3way_builtin_ptr_cmp.
* testsuite/18_support/comparisons/object/builtin-ptr-three-way.cc: Moved to...
* testsuite/18_support/comparisons/object/lwg3530.cc: ...here.
* testsuite/20_util/function_objects/range.cmp/lwg3530.cc: New test.
Joel Hutton [Wed, 10 Mar 2021 12:22:45 +0000 (12:22 +0000)]
[Vect] Fix mask check on Scatter loads/stores
Previously, IFN_MASK_SCATTER_STORE was used if 'loop_masks' was
non-null, but the mask used is 'final_mask'. This caused a bug where
a 'MASK_STORE' was vectorized into a 'SCATTER_STORE' instead of a
'MASK_SCATTER_STORE'. This fixes PR target/99102.
Richard Biener [Wed, 10 Mar 2021 10:57:21 +0000 (11:57 +0100)]
tree-optimization/99510 - fix type reuse of build_aligned_type
The fix for PR94775 added more strict checking for type reuse
to check_aligned_type, specifically matching TYPE_USER_ALIGN.
But then build_aligned_type sets TYPE_USER_ALIGN on the built
variant so if the type we build an aligned variant for does not
have TYPE_USER_ALIGN we'll never re-use the newly created aligned
variant. This results in ~35000 identical variants being created
for polyhedron doduc.
The following instead checks that the candidate has TYPE_USER_ALIGN set.
2021-03-10 Richard Biener <rguenther@suse.de>
PR tree-optimization/99510
* tree.c (check_aligned_type): Check that the candidate
has TYPE_USER_ALIGN set instead of matching with the
original type.
Eric Botcazou [Wed, 10 Mar 2021 11:05:53 +0000 (12:05 +0100)]
Do not assume that __float128 exists
The code in build_round_expr implicitly assumes that __float128 exists,
which is *not* the common case among 64-bit architectures since the
"long double" type is generally already 128-bit for them.
gcc/fortran/
PR fortran/96983
* trans-intrinsic.c (build_round_expr): Do not implicitly assume
that __float128 is the 128-bit floating-point type.
Eric Botcazou [Wed, 10 Mar 2021 11:04:25 +0000 (12:04 +0100)]
Fix ICE on atomic enumeration type with LTO
This is a strange regression whereby an enumeration type declared as
atomic (or volatile) incorrectly triggers the ODR machinery for its
values in LTO mode.
gcc/ada/
* gcc-interface/decl.c (gnat_to_gnu_entity): Build a TYPE_STUB_DECL
for the main variant of an enumeration type declared as volatile.
gcc/testsuite/
* gnat.dg/specs/lto25.ads: New test.
Eric Botcazou [Wed, 10 Mar 2021 11:02:14 +0000 (12:02 +0100)]
Fix miscompilation of Ada runtime on 64-bit SPARC
Returning a REGMODE_NATURAL_SIZE of 4 for DFmode in 64-bit mode is
just asking for trouble because sub-word SUBREGs are always treated
differently than the others, in particular by the register allocator.
gcc/
* config/sparc/sparc.c (sparc_regmode_natural_size): Return 4 for
float and vector integer modes only if the mode is not larger.
When DWARF_FRAME_REGISTERS isn't defined, the default is
FIRST_PSEUDO_REGISTER which means that if you add faked
registers to the port, used for frame-context related
elimination, room is allocated for them in the register
context used for frame-unwinding, which is wasteful because
they're eliminated before the final form of the code that is
emitted.
Stopping after MOF saves two register slots in the unwind
contest, compared to the current default. For regular C
programming this is uninteresting, but defining
DWARF_FRAME_REGISTERS now also avoids the need to remember
to define it later, when twiddling with additional faked
registers (alternatively suffering churn from comparing
differences in unwind context). As expected, no effect on
test-results, coremark or local (C-specific)
microbenchmarks.
The problem was that "gcc/config/rtems.h" was included before the
architecture-specific "gcc/config/*/rtems.h" header file on some
architectures.
gcc/
* config.gcc (aarch64-*-rtems*): Include general rtems.h after
the architecture-specific rtems.h.
(aarch64-*-rtems*): Likewise.
(arm*-*-rtems*): Likewise.
(epiphany-*-rtems*): Likewise.
(riscv*-*-rtems*): Likewise.
Jakub Jelinek [Tue, 9 Mar 2021 18:13:11 +0000 (19:13 +0100)]
phiopt: Fix up conditional_replacement [PR99305]
Before my PR97690 changes, conditional_replacement would not set neg
when the nonzero arg was boolean true.
I've simplified the testing, so that it first finds the zero argument
and then checks the other argument for all the handled cases
(1, -1 and 1 << X, where the last case is what the patch added support for).
But, unfortunately I've placed the integer_all_onesp test first.
For unsigned precision 1 types such as bool integer_all_onesp, integer_onep
and integer_pow2p can all be true and the code set neg to true in that case,
which is undesirable.
The following patch tests integer_pow2p first (which is trivially true
for integer_onep too and tree_log2 in that case gives shift == 0)
and only if that isn't the case, integer_all_onesp.
2021-03-09 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/99305
* tree-ssa-phiopt.c (conditional_replacement): Test integer_pow2p
before integer_all_onesp instead of vice versa.
The previous version returned true for all PowerPC. This is incorrect.
We only support floating point square root instructions if a) we support
floating point instructions at all, and b) we have _ARCH_PPCSQ defined.
Jakub Jelinek [Tue, 9 Mar 2021 15:44:27 +0000 (16:44 +0100)]
c++: Fix coroutines on targetm.cxx.cdtor_return_this targets [PR99459]
The r11-7528 build_co_await changes broke coroutines on arm*-linux-gnuabi,
2780 ^FAIL.*coroutines/ in total.
The problem is that arm is targetm.cxx.cdtor_return_this target where
both ctors and dtors in the ABI return this pointer rather than
void, and build_new_method_call_1 does:
else if (call != error_mark_node
&& DECL_DESTRUCTOR_P (cand->fn)
&& !VOID_TYPE_P (TREE_TYPE (call)))
/* An explicit call of the form "x->~X()" has type
"void". However, on platforms where destructors
return "this" (i.e., those where
targetm.cxx.cdtor_returns_this is true), such calls
will appear to have a return value of pointer type
to the low-level call machinery. We do not want to
change the low-level machinery, since we want to be
able to optimize "delete f()" on such platforms as
"operator delete(~X(f()))" (rather than generating
"t = f(), ~X(t), operator delete (t)"). */
call = build_nop (void_type_node, call);
The new code in build_co_await relies on build_special_member_call
returned expression being a CALL_EXPR, but due to the build_nop
in there it is a NOP_EXPR around the CALL_EXPR. It can't be stripped
with STRIP_NOPS because void has different mode from the pointer mode.
2021-03-09 Jakub Jelinek <jakub@redhat.com>
PR c++/99459
* coroutines.cc (build_co_await): Look through NOP_EXPRs in
build_special_member_call return value to find the CALL_EXPR.
Simplify.
Eric Botcazou [Tue, 9 Mar 2021 15:20:53 +0000 (16:20 +0100)]
Assorted testsuite fixes
First, gcc.dg/array-quals-1.c does not pass if the compiler is configured
with --enable-default-pie because the sections change, so force -fno-pie.
Second, replace *-*-solaris* with sparc*-*-* for gfortran.dg/pr95690.f90
because this depends on the architecture rather than the OS. Third force
SRA to trigger on Aarch64 (like PowerPC) for gnat.dg/opt39.adb.
gcc/testsuite/
* gcc.dg/array-quals-1.c: Pass -fno-pie if supported.
* gcc.dg/loop-9.c: Likewise.
* gfortran.dg/pr95690.f90: Replace *-*-solaris* with sparc*-*-*.
* gnat.dg/opt39.adb: Pass --param option for Aarch64 too.
Eric Botcazou [Tue, 9 Mar 2021 15:12:22 +0000 (16:12 +0100)]
Fix internal error on lambda function
This boils down to the RTL expander trying to take the address of a DECL
whose RTX is a register.
gcc/
PR c++/90448
* calls.c (initialize_argument_information): When the argument
is passed by reference, do not make a copy in a thunk only if
the argument is already in memory. Remove redundant test for
the case of callee copy.
[PR99454] LRA: Process 0..9 constraints in process_address_1
We need to process 0..9 constraints to fetch the right op constraint in
the function. Also 0..9 constraints gives unknown class constraint
class which can result in skipping address normalization for memory in asm.
gcc/ChangeLog:
PR target/99454
* lra-constraints.c (process_address_1): Process 0..9 constraints
in process_address_1.
Jakub Jelinek [Tue, 9 Mar 2021 13:14:09 +0000 (14:14 +0100)]
testsuite: Fix up pr98920.c on non-glibc or old glibc targets [PR98920]
Not all OSes have regex.h and not all OSes that do have REG_STARTEND macro support.
Conditionalize the test on that.
2021-03-09 Jakub Jelinek <jakub@redhat.com>
PR sanitizer/98920
* c-c++-common/asan/pr98920.c: Only include regex.h if the header
exists. If REG_STARTEND macro isn't defined, just return 0 from main
instead of the actual test.
Aaron Sawdey [Sun, 7 Mar 2021 20:47:31 +0000 (14:47 -0600)]
Tighten predicates for p10 ld/cmpi fusion
PR99070 is caused by a fusion pattern matching that the individual
instructions do not match when it is split later. In this case the
ld+cmpi patterns were allowing a d-form load address, which the split
condition would rightly split, however that left us with something that
could not be matched by a ds-form ld instruction, hence the ICE. This
only happened if the target cpu was not power10 -- if we were targeting
power10 then a prefixed pld instruction would get generated because that
can handle d-form. However this is not optimal code either.
So the solution is a new predicate (ds_form_mem_operand) that only
accepts what we can take as for a ds-form load. Then a small
modification of the genfusion.pl script changes the relevant
ld+cmpi patterns to use the new predicate.
gcc/ChangeLog
PR target/99070
* config/rs6000/predicates.md (ds_form_mem_operand) New
predicate.
* config/rs6000/genfusion.pl (gen_ld_cmpi_p10) Use
ds_form_mem_operand in ld/lwa patterns.
* config/rs6000/fusion.md: Regenerate file.
Martin Sebor [Mon, 8 Mar 2021 20:37:21 +0000 (13:37 -0700)]
PR middle-end/98266 - bogus array subscript is partly outside array bounds on virtual inheritance
gcc/ChangeLog:
PR middle-end/98266
* gimple-array-bounds.cc (inbounds_vbase_memaccess_p): New function.
(array_bounds_checker::check_array_bounds): Call it.
gcc/testsuite/ChangeLog:
PR middle-end/98266
* g++.dg/warn/Warray-bounds-15.C: New test.
* g++.dg/warn/Warray-bounds-18.C: New test.
* g++.dg/warn/Warray-bounds-19.C: New test.
* g++.dg/warn/Warray-bounds-20.C: New test.
* g++.dg/warn/Warray-bounds-21.C: New test.
git://gcc.gnu.org / gcc.git / log