Jonathan Wakely [Thu, 3 Mar 2022 12:34:27 +0000 (12:34 +0000)]
libstdc++: Implement std::strong_order for floating-point types [PR96526]
This removes a FIXME in <compare>, defining the total order for
floating-point types. I originally opened PR96526 to request a new
compiler built-in to implement this, but now that we have std::bit_cast
it can be done entirely in the library.
The implementation is based on the glibc definitions of totalorder,
totalorderf, totalorderl etc.
I think this works for all the types that satisfy std::floating_point
today, and should also work for the types expected to be added by P1467
except for std::bfloat16_t. It also supports some additional types that
don't currently satisfy std::floating_point, such as __float80, but we
probably do want that to satisfy the concept for non-strict modes.
libstdc++-v3/ChangeLog:
PR libstdc++/96526
* libsupc++/compare (strong_order): Add missing support for
floating-point types.
* testsuite/18_support/comparisons/algorithms/strong_order_floats.cc:
New test.
openmp, fortran: Check that the type of an event handle in a detach clause is suitable [PR104131]
This rejects variables that are array types, array elements or derived type
members when used as the event handle inside a detach clause (in accordance
with the OpenMP specification). This would previously lead to an ICE.
PR fortran/104131
* openmp.cc (gfc_match_omp_detach): Move check for type of event
handle to...
(resolve_omp_clauses) ...here. Also check that the event handle is
not an array, or an array access or structure element access.
Tom de Vries [Thu, 3 Mar 2022 08:22:42 +0000 (09:22 +0100)]
[nvptx] Build libraries with mptx=3.1
In gcc-5 to gcc-11, the ptx isa version was 3.1.
On trunk, the default is now 6.0, which is also what will be the value in
the libraries.
Consequently, there may be setups with an older driver that worked with
gcc-11, but will become unsupported with gcc-12.
Fix this by building the libraries with mptx=3.1.
After this, setups with an older driver still won't work out of the box
with gcc-12, because the default ptx isa version has changed, but should work
after specifying mptx=3.1.
Tom de Vries [Wed, 2 Mar 2022 11:04:39 +0000 (12:04 +0100)]
[nvptx] Build libraries with misa=sm_30
In gcc-11, when specifying -misa=sm_30, an executable may still contain sm_35
code (due to libraries being built with the default -misa=sm_35), so it won't
run on an sm_30 board.
Fix this by building libraries with sm_30, as was the case in gcc-5 to gcc-10.
Tom de Vries [Thu, 3 Mar 2022 08:21:04 +0000 (09:21 +0100)]
[nvptx] Use --no-verify for sm_30
In PR97348, we ran into the problem that recent CUDA dropped support for
sm_30, which inhibited the build when building with CUDA bin in the path,
because the nvptx-tools assembler uses CUDA's ptxas to do ptx verification.
To fix this, in gcc-11 the default sm_xx was moved from sm_30 to sm_35.
This however broke support for sm_30 boards: an executable build for sm_30
might contain sm_35 code from the libraries, which are build with the default
sm_xx (PR104758).
We want to fix this by going back to having the libraries build with sm_30, as
was the case for gcc-5 to gcc-10. That however reintroduces the problem from
PR97348.
Deal with PR97348 in the simplest way possible: when calling the assembler for
sm_30, specify --no-verify.
This has the unfortunate effect that after fixing PR104758 by building
libraries with sm_30, the libraries are no longer verified. This can be
improved upon by:
- adding a configure test in gcc that tests if CUDA supports sm_30, and
if so disabling this patch
- dealing with this in nvptx-tools somehow, either:
- detect at ptxas execution time that it doesn't support sm_30, or
- detect this at nvptx-tool configure time.
Tom de Vries [Thu, 3 Mar 2022 07:51:33 +0000 (08:51 +0100)]
[nvptx] Add -mptx=_ in gcc.target/nvptx/smxx.c
With target board nvptx-none-run/-mptx=3.1 we run into:
...
cc1: error: PTX version (-mptx) needs to be at least 4.2 to support \
selected -misa (sm_53)^M
compiler exited with status 1
FAIL: gcc.target/nvptx/sm53.c (test for excess errors)
...
Jakub Jelinek [Thu, 3 Mar 2022 08:13:32 +0000 (09:13 +0100)]
openmp: Disable SSA form during gimplification on OMP_SIMD clauses and body [PR104757]
When offloading to nvptx is enabled, scan_omp_simd duplicates the simd
region including its clauses and body using inliner's
copy_gimple_seq_and_replace_locals. That works nicely for decls, remaps
only those that are seen in the nested bind expr vars (i.e. local variables)
and doesn't remap other vars. But for SSA_NAMEs it remaps them always, doesn't
know if their def stmt is outside of the simd (then it better shouldn't be remapped)
or inside of it (then it should) and without cfg/dominators that is pretty hard
to figure out (well, we could walk the region twice, once note SSA_NAMEs defined
by each stmt seen there and once do the remapping of only those visited SSA_NAMEs).
This patch uses a simpler way, disables temporarily into_ssa for the clauses and
body of each simd region; we already disable into_ssa e.g. in parallel/target/task
etc. regions through push_gimplify_context () but for simd we don't push
any gimplification context and appart from into_ssa I think we don't need it.
2022-03-03 Jakub Jelinek <jakub@redhat.com>
PR middle-end/104757
* gimplify.cc (gimplify_omp_loop): Call gimplify_expr rather than
gimplify_omp_for.
(gimplify_expr) <case OMP_SIMD>: Temporarily disable
gimplify_ctxp->into_ssa around call to gimplify_omp_for.
* gfortran.dg/gomp/pr104757.f90: New test.
* gcc.dg/gomp/pr104757.c: New test.
Jakub Jelinek [Thu, 3 Mar 2022 08:11:09 +0000 (09:11 +0100)]
calls: When bypassing emit_push_insn for 0 sized arg, emit at least anti_adjust_stack for alignment pad if needed [PR104558]
The following testcase ICEs on x86_64 when asked to use the pre-GCC 8
ABI where zero sized arguments weren't ignored.
In GCC 7 the emit_push_insn calls in store_one_arg were unconditional,
it is true that they didn't actually push anything because it had zero
size, but because arg->locate.alignment_pad is 8 in this case,
emit_push_insn at the end performs
if (alignment_pad && args_addr == 0)
anti_adjust_stack (alignment_pad);
and an assert larger on is upset if we don't do it.
The following patch keeps the emit_push_insn conditional but calls
the anti_adjust_stack when needed by hand for the zero sized arguments.
For the new x86_64 ABI where zero sized arguments are ignored
arg->locate.alignment_pad is 0 in this case, so nothing changes
- we in that case really do ignore it.
There is another emit_push_insn call earlier in store_one_arg, also made
conditional on non-zero size by Marek in GCC 8, but that one is for
arguments with non-BLKmode and the only way those can be zero size is
if they are TYPE_EMPTY_P aka when they are completely ignored. But
I believe arg->locate.alignment_pad should be 0 in that case, so IMHO
there is no need to do anything in the second spot.
2022-03-03 Jakub Jelinek <jakub@redhat.com>
PR middle-end/104558
* calls.cc (store_one_arg): When not calling emit_push_insn
because size_rtx is const0_rtx, call at least anti_adjust_stack
on arg->locate.alignment_pad if !argblock and the alignment might
be non-zero.
Alexandre Oliva [Wed, 2 Mar 2022 17:13:06 +0000 (14:13 -0300)]
Undo multi-word optional reloads correctly
Unlike e.g. remove_inheritance_pseudos, undo_optional_reloads didn't
deal with subregs, so instead of removing multi-word moves, it
replaced the reload pseudo with the original pseudo. Besides the
redundant move, that retained the clobber of the dest, that starts a
multi-word move. After the remap, the sequence that should have
become a no-op move starts by clobbering the original pseudo and then
moving its pieces onto themselves. The problem is the clobber: it
makes earlier sets of the original pseudo to be regarded as dead: if
the optional reload sequence was an output reload, the insn for which
the output reload was attempted may be regarded as dead and deleted.
I've arranged for undo_optional_reloads to accept SUBREGs and use
get_regno, like remove_inheritance_pseudo, adjusted its insn-removal
loop to tolerate iterating over a removed clobber, and added logic to
catch any left-over reload clobbers that could trigger the problem.
for gcc/ChangeLog
* lra-constraints.cc (undo_optional_reloads): Recognize and
drop insns of multi-word move sequences, tolerate removal
iteration on an already-removed clobber, and refuse to
substitute original pseudos into clobbers.
Qing Zhao [Wed, 2 Mar 2022 16:48:37 +0000 (16:48 +0000)]
Don't emit switch-unreachable warnings for -ftrivial-auto-var-init (PR102276)
At the same time, adding -Wtrivial-auto-var-init and update documentation.
-Wtrivial-auto-var-init and update documentation.
for the following testing case:
1 int g(int *);
2 int f1()
3 {
4 switch (0) {
5 int x;
6 default:
7 return g(&x);
8 }
9 }
compiling with -O -ftrivial-auto-var-init causes spurious warning:
warning: statement will never be executed [-Wswitch-unreachable]
5 | int x;
| ^
This is due to the compiler-generated initialization at the point of
the declaration.
We could avoid the warning to exclude the following cases:
when
flag_auto_var_init > AUTO_INIT_UNINITIALIZED
And
1) call to .DEFERRED_INIT
2) call to __builtin_clear_padding if the 2nd argument is present and non-zero
3) a gimple assign store right after the .DEFERRED_INIT call that has the LHS
as RHS
However, we still need to warn users about the incapability of the option
-ftrivial-auto-var-init by adding a new warning option -Wtrivial-auto-var-init
to report cases when it cannot initialize the auto variable. At the same
time, update documentation for -ftrivial-auto-var-init to connect it with
the new warning option -Wtrivial-auto-var-init, and add documentation
for -Wtrivial-auto-var-init.
gcc/ChangeLog:
PR middle-end/102276
* common.opt (-Wtrivial-auto-var-init): New option.
* doc/invoke.texi (-Wtrivial-auto-var-init): Document new option.
(-ftrivial-auto-var-init): Update option;
* gimplify.cc (emit_warn_switch_unreachable): New function.
(warn_switch_unreachable_r): Rename to ...
(warn_switch_unreachable_and_auto_init_r): This.
(maybe_warn_switch_unreachable): Rename to ...
(maybe_warn_switch_unreachable_and_auto_init): This.
(gimplify_switch_expr): Update calls to renamed function.
gcc/testsuite/ChangeLog:
PR middle-end/102276
* gcc.dg/auto-init-pr102276-1.c: New test.
* gcc.dg/auto-init-pr102276-2.c: New test.
* gcc.dg/auto-init-pr102276-3.c: New test.
* gcc.dg/auto-init-pr102276-4.c: New test.
Richard Biener [Wed, 2 Mar 2022 07:55:58 +0000 (08:55 +0100)]
rtl-optimization/104686 - speedup IRA allocno conflict test
In this PR allocnos_conflict_p takes 90% of the compile-time via
the calls from update_conflict_hard_regno_costs. This is due to
the high number of conflicts recorded in the dense bitvector
representation. Fortunately we can take advantage of the bitvector
representation here and turn the O(n) conflict test into an O(1) one,
greatly speeding up the compile of the testcase from 39s to just 4s
(93% IRA time to 26% IRA time).
While for the testcase in question the first allocno is almost always
the nice one the patch tries a more systematic approach to finding
the allocno to iterate object conflicts over. That does reduce
the actual number of compares for the testcase but it doesn't make
a measurable difference wall-clock wise. That's not guaranteed
though I think so I've kept this systematic way of choosing the
cheapest allocno.
2022-03-02 Richard Biener <rguenther@suse.de>
PR rtl-optimization/104686
* ira-color.cc (object_conflicts_with_allocno_p): New function
using a bitvector test instead of iterating when possible.
(allocnos_conflict_p): Choose the best allocno to iterate over
object conflicts.
(update_conflict_hard_regno_costs): Do allocnos_conflict_p test
last.
Jakub Jelinek [Wed, 2 Mar 2022 10:04:35 +0000 (11:04 +0100)]
testsuite: Fix up pr104637 testcase [PR104637]
This testcase FAILs everywhere for 3 reasons:
1) the testcase can't work on ia32, where sizeof (long double) == 12
and as it is not a power of 2, we disallow creating vectors with such
elements, -mx32 and -m64 are fine
2) the testcase emits a lot of -Wdiv-by-zero warnings, I've just added
-Wno-div-by-zero to dg-options
3) my fault, when tweaking the testcase I've missed 33 initializers of
a 32 element vector which didn't change anything on the ICE, but is
still reported
This patch fixes all of it, tested with
RUNTESTFLAGS='--target_board=unix\{-m32,-m64\} i386.exp=pr104637.c'
both without the LRA fix where it ICEs and with it where it passes
everywhere.
2022-03-02 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/104637
* gcc.target/i386/pr104637.c: Don't run on ia32. Add -Wno-div-by-zero
to dg-options.
(foo): Remove extraneous initializer.
Jakub Jelinek [Wed, 2 Mar 2022 09:48:55 +0000 (10:48 +0100)]
cfg: Dump goto_locus if -fdump-*-*-blocks-details
When debugging the PR104589 issue, I've run into a problem that
goto_locus doesn't show up in the logs, so it wasn't clear if
the bug hasn't been introduced far earlier just by divergence
in goto_locus of some edge.
2022-03-02 Jakub Jelinek <jakub@redhat.com>
* cfg.cc (dump_edge_info): Dump goto_locus if present.
Jakub Jelinek [Wed, 2 Mar 2022 09:48:14 +0000 (10:48 +0100)]
cfgrtl: Fix up -g vs. -g0 code generation -flto differences in fixup_reorder_chain [PR104589]
This is similar to PR104237 and similarly to that, no testcase included
for the testsuite, as we don't have a framework to compile/link with
-g -flto and -g0 -flto and compare -fdump-final-insns= results from
the lto1 compilations.
With -flto, whether two location_t compare equal or not and just
express the same location is a lottery.
2022-03-02 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/104589
* cfgrtl.cc (fixup_reorder_chain): Use loc_equal instead of direct
INSN_LOCATION comparison with goto_locus.
Jakub Jelinek [Wed, 2 Mar 2022 09:38:39 +0000 (10:38 +0100)]
testsuite: Add testcases for already fixed PR [PR100541]
These testcases started failing with r12-630 and one of them
got fixed with r12-4531 (aka PR102764 fix and r12-4616 further
improved the fix) and the other went latent in r12-2591 (i.e. threader
changes) and I believe was fixed for real by the PR102764 fix too.
2022-03-02 Jakub Jelinek <jakub@redhat.com>
PR debug/100541
* g++.dg/opt/pr100541-1.C: New test.
* g++.dg/opt/pr100541-2.C: New test.
Hongyu Wang [Tue, 1 Mar 2022 09:49:52 +0000 (17:49 +0800)]
AVX512FP16: Fix vcvt[u]si2sh runtime tests for Solaris
Use standard C type instead of __int64_t which doesn't work on Solaris.
gcc/testsuite/ChangeLog:
PR target/104724
* gcc.target/i386/avx512fp16-vcvtsi2sh-1b.c: Use long long
instead of __int64_t.
* gcc.target/i386/avx512fp16-vcvtsi2sh64-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtusi2sh-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtusi2sh64-1b.c: Ditto.
Jakub Jelinek [Tue, 1 Mar 2022 20:05:31 +0000 (21:05 +0100)]
warn-access: Fix up check_pointer_uses [PR104715]
The following testcase emits bogus -Wdangling-pointer warnings.
The bug is that when it sees that ptr immediate use is a call that
returns one of its arguments, it will assume that the return value
is based on ptr, but that is the case only if ptr is passed to the
argument that is actually returned (so e.g. for memcpy the first argument,
etc.). When the builtins guarantee e.g. that the result is based on the
first argument (either ERF_RETURNS_ARG 0 in which case it will always
just returns the first argument as is, or when it is something like
strstr or strpbrk or mempcpy that it returns some pointer based on the
first argument), it means the result is not based on second or following
argument if any. The second hunk fixes this.
The first hunk just removes an unnecessary TREE_CODE check, the code only
pushes SSA_NAMEs into the pointers vector and if it didn't, it uses
FOR_EACH_IMM_USE_FAST (use_p, iter, ptr)
a few lines below this, which of course requires that ptr is a SSA_NAME.
Tree checking on SSA_NAME_VERSION will already ensure that if it wasn't
a SSA_NAME, we'd ICE.
2022-03-01 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/104715
* gimple-ssa-warn-access.cc (pass_waccess::check_pointer_uses): Don't
unnecessarily test if ptr is a SSA_NAME, it has to be. Only push lhs
of a call if gimple_call_return_arg is equal to ptr, not just when it
is non-NULL.
Jakub Jelinek [Tue, 1 Mar 2022 18:43:04 +0000 (19:43 +0100)]
warn-access: Comment spelling fixes
I've noticed various spelling bugs in comments in this file.
There is one spot I haven't fixed:
"Otherwise, VAR is the auto variable
(including an unnamed temporary such as a compound literal) whose
lifetime's rended it dangling."
I'm afraid I don't know what it wanted to say, "lifetime rendered it"
or something else?
Richard Biener [Tue, 1 Mar 2022 08:24:26 +0000 (09:24 +0100)]
tree-optimization/104716 - check if we can copy loop in loop distribution
The following checks whether we can copy the loop before attempting
to do so in loop distribution. In the testcase there's a computed
goto and thus abnormal edges which we cannot redirect.
2022-03-01 Richard Biener <rguenther@suse.de>
PR tree-optimization/104716
* tree-loop-distribution.cc (find_seed_stmts_for_distribution):
Check if we can copy the loop.
introduced currently_expanding_gimple_stmt, which was set and cleared in
expand_gimple_basic_block when expanding gimple statement to RTL. But it
isn't cleared when expand_gimple_basic_block returns inside the loop.
PR middle-end/104721
* cfgexpand.cc (expand_gimple_basic_block): Clear
currently_expanding_gimple_stmt when returning inside the loop.
Martin Liska [Mon, 28 Feb 2022 12:27:22 +0000 (13:27 +0100)]
ipa: Improve error handling for target_clone single value
PR ipa/104533
gcc/c-family/ChangeLog:
* c-attribs.cc (handle_target_clones_attribute): Use
get_target_clone_attr_len and report warning soon.
gcc/ChangeLog:
* multiple_target.cc (get_attr_len): Move to tree.c.
(expand_target_clones): Remove single value checking.
* tree.cc (get_target_clone_attr_len): New fn.
* tree.h (get_target_clone_attr_len): Likewise.
Tom de Vries [Fri, 25 Feb 2022 10:49:01 +0000 (11:49 +0100)]
[nvptx] Add nvptx-gen.h and nvptx-gen.opt
Use nvptx-sm.def to generate new files nvptx-gen.h and nvptx-gen.opt, and:
- include nvptx-gen.h in nvptx.h, and
- add nvptx-gen.opt to extra_options (before nvptx.opt, in case that matters).
Tested on nvptx.
gcc/ChangeLog:
2022-02-25 Tom de Vries <tdevries@suse.de>
* config.gcc (nvptx*-*-*): Add nvptx/nvptx-gen.opt to extra_options.
* config/nvptx/gen-copyright.sh: New file.
* config/nvptx/gen-h.sh: New file.
* config/nvptx/gen-opt.sh: New file.
* config/nvptx/nvptx.h (TARGET_SM35, TARGET_SM53, TARGET_SM70)
(TARGET_SM75, TARGET_SM80): Move ...
* config/nvptx/nvptx-gen.h: ... here. New file, generate.
* config/nvptx/nvptx.opt (Enum ptx_isa): Move ...
* config/nvptx/nvptx-gen.opt: ... here. New file, generate.
* config/nvptx/t-nvptx ($(srcdir)/config/nvptx/nvptx-gen.h)
($(srcdir)/config/nvptx/nvptx-gen.opt): New make target.
Tom de Vries [Fri, 25 Feb 2022 10:47:12 +0000 (11:47 +0100)]
[nvptx] Add nvptx-sm.def
Add a file gcc/config/nvptx/nvptx-sm.def that lists all sm_xx versions used in
the port, like so:
...
NVPTX_SM(30, NVPTX_SM_SEP)
NVPTX_SM(35, NVPTX_SM_SEP)
NVPTX_SM(53, NVPTX_SM_SEP)
NVPTX_SM(70, NVPTX_SM_SEP)
NVPTX_SM(75, NVPTX_SM_SEP)
NVPTX_SM(80,)
...
and use it in various places using a pattern:
...
#define NVPTX_SM(XX, SEP) { ... }
#include "nvptx-sm.def"
#undef NVPTX_SM
...
Tested on nvptx.
gcc/ChangeLog:
2022-02-25 Tom de Vries <tdevries@suse.de>
* config/nvptx/nvptx-sm.def: New file.
* config/nvptx/nvptx-c.cc (nvptx_cpu_cpp_builtins): Use nvptx-sm.def.
* config/nvptx/nvptx-opts.h (enum ptx_isa): Same.
* config/nvptx/nvptx.cc (sm_version_to_string)
(nvptx_omp_device_kind_arch_isa): Same.
Tom de Vries [Fri, 25 Feb 2022 10:43:55 +0000 (11:43 +0100)]
[nvptx, testsuite] Add gcc.target/nvptx/sm*.c
Add a few test-cases that test passing each -misa=sm_xx version and verify that
the proper __PTX_SM__ is defined.
Tested on nvptx.
gcc/testsuite/ChangeLog:
2022-02-25 Tom de Vries <tdevries@suse.de>
* gcc.target/nvptx/sm30.c: New test.
* gcc.target/nvptx/sm35.c: New test.
* gcc.target/nvptx/sm53.c: New test.
* gcc.target/nvptx/sm70.c: New test.
* gcc.target/nvptx/sm75.c: New test.
* gcc.target/nvptx/sm80.c: New test.
Robin Dapp [Mon, 7 Feb 2022 07:39:41 +0000 (08:39 +0100)]
arc: Fix for new ifcvt behavior [PR104154]
ifcvt now passes a CC-mode "comparison" to backends. This patch
simply returns from gen_compare_reg () in that case since nothing
needs to be prepared anymore.
Roger Sayle [Mon, 28 Feb 2022 22:30:27 +0000 (22:30 +0000)]
PR tree-optimization/91384: peephole2 to eliminate testl after negl.
This patch is my proposed solution to PR tree-optimization/91384 which is
a missed-optimization/code quality regression on x86_64. The problematic
idiom is "if (r = -a)" which is equivalent to both "r = -a; if (r != 0)"
and alternatively "r = -a; if (a != 0)". In this particular case, on
x86_64, we prefer to use the condition codes from the negation, rather
than require an explicit testl instruction.
Unfortunately, combine can't help, as it doesn't attempt to merge pairs
of instructions that share the same operand(s), only pairs/triples of
instructions where the result of each instruction feeds the next. But
I doubt there's sufficient benefit to attempt this kind of "combination"
(that wouldn't already be caught by the tree-ssa passes).
Fortunately, it's relatively easy to fix this up (addressing the
regression) during peephole2 to eliminate the unnecessary testl in:
movl %edi, %ebx
negl %ebx
testl %edi, %edi
je .L2
2022-02-28 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
PR tree-optimization/91384
* config/i386/i386.md (peephole2): Eliminate final testl insn
from the sequence *movsi_internal, *negsi_1, *cmpsi_ccno_1 by
transforming using *negsi_2 for the negation.
gcc/testsuite/ChangeLog
PR tree-optimization/91384
* gcc.target/i386/pr91384.c: New test case.
Roger Sayle [Mon, 28 Feb 2022 22:26:43 +0000 (22:26 +0000)]
PR middle-end/80270: ICE in extract_bit_field_1
This patch fixes PR middle-end/80270, an ICE-on-valid regression, where
performing a bitfield extraction on a variable explicitly stored in a
hard register by the user causes a segmentation fault during RTL
expansion. Nearly identical source code without the "asm" qualifier
compiles fine. The point of divergence is in simplify_gen_subreg
which tries to avoid creating non-trivial SUBREGs of hard registers,
to avoid problems during register allocation. This suggests the
simple solution proposed here, to copy hard registers to a new pseudo
in extract_integral_bit_field, just before calling simplify_gen_subreg.
2022-02-28 Roger Sayle <roger@nextmovesoftware.com>
Eric Botcazou <ebotcazou@adacore.com>
gcc/ChangeLog
PR middle-end/80270
* expmed.cc (extract_integral_bit_field): If OP0 is a hard
register, copy it to a pseudo before calling simplify_gen_subreg.
gcc/testsuite/ChangeLog
* gcc.target/i386/pr80270.c: New test case.
[PR104637] LRA: Split hard regs as many as possible on one subpass
LRA hard reg split subpass is a small subpass used as the last
resort for LRA when it can not assign a hard reg to a reload
pseudo by other ways (e.g. by spilling non-reload pseudos). For
simplicity the subpass works on one split base (as each split
changes pseudo live range info). In this case it results in
reaching maximal possible number of subpasses. The patch
implements as many non-overlapping hard reg splits
splits as possible on each subpass.
gcc/ChangeLog:
PR rtl-optimization/104637
* lra-assigns.cc (lra_split_hard_reg_for): Split hard regs as many
as possible on one subpass.
- Import dmd v2.099.0-rc.1.
- The `main' can now return type `noreturn' and supports return
inference.
D Runtime changes:
- Import druntime v2.099.0-rc.1.
- C bindings for stat_t on powerpc-linux has been fixed.
Phobos changes:
- Import phobos v2.099.0-rc.1.
gcc/d/ChangeLog:
* d-target.cc (Target::_init): Initialize C type size fields.
* dmd/MERGE: Merge upstream dmd cf63dd8e5.
* dmd/VERSION: Update version to v2.099.0-rc.1.
Marek Polacek [Fri, 25 Feb 2022 19:56:13 +0000 (14:56 -0500)]
c++: Lost deprecated/unavailable attr in class tmpl [PR104682]
When looking into the other PR I noticed that we fail to give a warning
for a deprecated enumerator when the enum is in a class template. This
only happens when the attribute doesn't have an argument. The reason is
that when we tsubst_enum, we create a new enumerator:
but DECL_ATTRIBUTES (decl) is null when the attribute was provided
without an argument -- in that case it simply melts into a tree flag.
handle_deprecated_attribute has:
if (!args)
*no_add_attrs = true;
so the attribute isn't retained and we lose it when tsubsting. Same
thing when the attribute is on the enum itself.
Attribute unavailable is a similar case, but it's different in that
it can be a late attribute whereas "deprecated" can't:
is_late_template_attribute has
/* But some attributes specifically apply to templates. */
&& !is_attribute_p ("abi_tag", name)
&& !is_attribute_p ("deprecated", name)
&& !is_attribute_p ("visibility", name))
return true;
else
return false;
which looks strange, but attr-unavailable-9.C tests that we don't error when
the attribute is applied on a template.
PR c++/104682
gcc/cp/ChangeLog:
* cp-tree.h (build_enumerator): Adjust.
* decl.cc (finish_enum): Make it return the new decl.
* pt.cc (tsubst_enum): Propagate TREE_DEPRECATED and TREE_UNAVAILABLE.
gcc/testsuite/ChangeLog:
* g++.dg/ext/attr-unavailable-10.C: New test.
* g++.dg/ext/attr-unavailable-11.C: New test.
* g++.dg/warn/deprecated-17.C: New test.
* g++.dg/warn/deprecated-18.C: New test.
Marek Polacek [Thu, 24 Feb 2022 21:41:53 +0000 (16:41 -0500)]
c++: ICE with attribute on enumerator [PR104667]
When processing a template, the enumerators we build don't have a type
yet. But is_late_template_attribute is not prepared to see a _DECL
without a type, so we crash on
enum tree_code code = TREE_CODE (type);
(I found that we don't give the "is deprecated" warning for the enumerator
'f' in the test. Reported as PR104682.)
PR c++/104667
gcc/cp/ChangeLog:
* decl2.cc (is_late_template_attribute): Cope with a decl without
a type.
Qing Zhao [Mon, 28 Feb 2022 15:58:43 +0000 (15:58 +0000)]
Suppress uninitialized warnings for new created uses from __builtin_clear_padding folding [PR104550]
__builtin_clear_padding(&object) will clear all the padding bits of the object.
actually, it doesn't involve any use of an user variable. Therefore, users do
not expect any uninitialized warning from it. It's reasonable to suppress
uninitialized warnings for all new created uses from __builtin_clear_padding
folding.
PR middle-end/104550
gcc/ChangeLog:
* gimple-fold.cc (clear_padding_flush): Suppress warnings for new
created uses.
gcc/testsuite/ChangeLog:
* gcc.dg/auto-init-pr104550-1.c: New test.
* gcc.dg/auto-init-pr104550-2.c: New test.
* gcc.dg/auto-init-pr104550-3.c: New test.
Richard Biener [Mon, 28 Feb 2022 11:21:19 +0000 (12:21 +0100)]
Simplify PRE fix
The following reverts a part of the PR103037 fix which is no longer necessary
after the fix for PR104700. That makes the possible cummulative backport
smaller.
2022-02-28 Richard Biener <rguenther@suse.de>
* tree-ssa-pre.cc (compute_avail): Revert part of last change.
Richard Biener [Mon, 28 Feb 2022 07:36:25 +0000 (08:36 +0100)]
tree-optimization/104700 - adjust constant handling in PRE
The following refactors find_or_generate_expression to more properly
handle constant valued SSA names thereby simplifying the code and
avoiding ICEing after the last change to NARY processing.
2022-02-28 Richard Biener <rguenther@suse.de>
PR tree-optimization/104700
* tree-ssa-pre.cc (get_or_alloc_expr_for): Remove and inline
into ...
(find_or_generate_expression): ... here, simplifying code.
* gcc.dg/pr104700-2.c: New testcase.
* gcc.dg/torture/pr104700-1.c: Likewise.
Tom de Vries [Fri, 25 Feb 2022 16:01:34 +0000 (17:01 +0100)]
[libgomp, testsuite, nvptx] Add -mptx=_ in declare-variant-3-sm*.c
When running with target board unix/-foffload=-mptx=3.1, we run into:
...
lto1: error: PTX version (-mptx) needs to be at least 4.2 to support \
selected -misa (sm_53)^M
mkoffload: fatal error: x86_64-pc-linux-gnu-accel-nvptx-none-gcc returned \
1 exit status^M
compilation terminated.^M
...
FAIL: libgomp.c/declare-variant-3-sm53.c (test for excess errors)
...
Fix this by adding -foffload=-mptx=_ in the libgomp.c/declare-variant-3-sm*.c
test-cases.
Tom de Vries [Fri, 25 Feb 2022 15:37:59 +0000 (16:37 +0100)]
[nvptx, testsuite] Add -mptx=_ in nvptx.exp test-cases
When running with target board nvptx-none-run/-mptx=3.1, I run into:
...
cc1: error: PTX version (-mptx) needs to be at least 4.2 to support selected \
-misa (sm_53)^M
compiler exited with status 1
FAIL: gcc.target/nvptx/atomic-store-1.c (test for excess errors)
...
Fix this and similar cases by adding an explicit -mptx=_ setting.
Tom de Vries [Fri, 25 Feb 2022 15:21:46 +0000 (16:21 +0100)]
[nvptx, testsuite] Add -misa=sm_30 in nvptx/uniform-simt-2.c
When running with target board nvptx-none-run/-misa=sm_53 we run into:
...
cc1: error: PTX version (-mptx) needs to be at least 4.2 to support selected \
-misa (sm_53)^M
compiler exited with status 1
FAIL: gcc.target/nvptx/uniform-simt-2.c (test for excess errors)
...
Fix this by adding an explicit -misa=sm_30 in the test-case.
Richard Biener [Fri, 25 Feb 2022 13:19:44 +0000 (14:19 +0100)]
rtl-optimization/104686 - speed up conflict iteration
The following replaces
/* Skip bits that are zero. */
for (; (word & 1) == 0; word >>= 1)
bit_num++;
idioms in ira-int.h in the attempt to speedup update_conflict_hard_regno_costs
which we're bound on in PR104686. The trick is to use ctz_hwi here
which should pay off even with dense bitmaps on architectures that
have HW support for this.
For the PR in question this speeds up compile-time from 31s to 24s for
me.
2022-02-25 Richard Biener <rguenther@suse.de>
PR rtl-optimization/104686
* ira-int.h (minmax_set_iter_cond): Use ctz_hwi to elide loop
skipping bits that are zero.
(ira_object_conflict_iter_cond): Likewise.
Hongyu Wang [Fri, 25 Feb 2022 07:09:03 +0000 (15:09 +0800)]
AVX512F: Add helper enumeration for ternary logic intrinsics.
Sync with llvm change in https://reviews.llvm.org/D120307 to
add enumeration and truncate imm to unsigned char, so users could
use ~ on immediates.
gcc/ChangeLog:
* config/i386/avx512fintrin.h (_MM_TERNLOG_ENUM): New enum.
(_mm512_ternarylogic_epi64): Truncate imm to unsigned
char to avoid error when using ~enum as parameter.
(_mm512_mask_ternarylogic_epi64): Likewise.
(_mm512_maskz_ternarylogic_epi64): Likewise.
(_mm512_ternarylogic_epi32): Likewise.
(_mm512_mask_ternarylogic_epi32): Likewise.
(_mm512_maskz_ternarylogic_epi32): Likewise.
* config/i386/avx512vlintrin.h (_mm256_ternarylogic_epi64):
Adjust imm param type to unsigned char.
(_mm256_mask_ternarylogic_epi64): Likewise.
(_mm256_maskz_ternarylogic_epi64): Likewise.
(_mm256_ternarylogic_epi32): Likewise.
(_mm256_mask_ternarylogic_epi32): Likewise.
(_mm256_maskz_ternarylogic_epi32): Likewise.
(_mm_ternarylogic_epi64): Likewise.
(_mm_mask_ternarylogic_epi64): Likewise.
(_mm_maskz_ternarylogic_epi64): Likewise.
(_mm_ternarylogic_epi32): Likewise.
(_mm_mask_ternarylogic_epi32): Likewise.
(_mm_maskz_ternarylogic_epi32): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx512f-vpternlogd-1.c: Use new enum.
* gcc.target/i386/avx512f-vpternlogq-1.c: Likewise.
* gcc.target/i386/avx512vl-vpternlogd-1.c: Likewise.
* gcc.target/i386/avx512vl-vpternlogq-1.c: Likewise.
* gcc.target/i386/testimm-10.c: Remove imm check for vpternlog
insns since the imm has been truncated in intrinsic.
Jakub Jelinek [Fri, 25 Feb 2022 20:25:12 +0000 (21:25 +0100)]
match.pd: Further complex simplification fixes [PR104675]
Mark mentioned in the PR further 2 simplifications that also ICE
with complex types.
For these, eventually (but IMO GCC 13 materials) we could support it
for vector types if it would be uniform vector constants.
Currently integer_pow2p is true only for INTEGER_CSTs and COMPLEX_CSTs
and we can't use bit_and etc. for complex type.
2022-02-25 Jakub Jelinek <jakub@redhat.com>
Marc Glisse <marc.glisse@inria.fr>
PR tree-optimization/104675
* match.pd (t * 2U / 2 -> t & (~0 / 2), t / 2U * 2 -> t & ~1):
Restrict simplifications to INTEGRAL_TYPE_P.
Jakub Jelinek [Fri, 25 Feb 2022 17:58:48 +0000 (18:58 +0100)]
rs6000: Use rs6000_emit_move in movmisalign<mode> expander [PR104681]
The following testcase ICEs, because for some strange reason it decides to use
movmisaligntf during expansion where the destination is MEM and source is
CONST_DOUBLE. For normal mov<mode> expanders the rs6000 backend uses
rs6000_emit_move to ensure that if one operand is a MEM, the other is a REG
and a few other things, but for movmisalign<mode> nothing enforced this.
The middle-end documents that movmisalign<mode> shouldn't fail, so we can't
force that through predicates or condition on the expander.
2022-02-25 Jakub Jelinek <jakub@redhat.com>
PR target/104681
* config/rs6000/vector.md (movmisalign<mode>): Use rs6000_emit_move.
If the movcc comparison is not valid it triggers an assert in the
current implementation. This behavior is not needed as we can FAIL
the movcc expand pattern.
gcc/
* config/arc/arc.cc (gen_compare_reg): Return NULL_RTX if the
comparison is not valid.
* config/arc/arc.md (movsicc): Fail if comparison is not valid.
(movdicc): Likewise.
(movsfcc): Likewise.
(movdfcc): Likewise.
Richard Biener [Thu, 24 Feb 2022 12:04:29 +0000 (13:04 +0100)]
tree-optimization/103037 - PRE simplifying valueized expressions
This fixes a long-standing issue in PRE where we track valueized
expressions in our expression sets that we use for PHI translation,
code insertion but also feed into match-and-simplify via
vn_nary_simplify. But that's not what is expected from vn_nary_simplify
or match-and-simplify which assume we are simplifying with operands
available at the point of the expression so they can use contextual
information on the SSA names like ranges. While the VN side was
updated to ensure this with the rewrite to RPO VN, thereby removing
all workarounds that nullified such contextual info on all SSA names,
the PRE side still suffers from this.
The following patch tries to apply minimal surgery at this point
and makes PRE track un-valueized expressions in the expression sets
but only for the NARY kind (both NAME and CONSTANT do not suffer
from this issue), leaving the REFERENCE kind alone. The REFERENCE
kind is important when trying to remove the workarounds still in
place in compute_avail for code hoisting, but that's a separate issue
and we have a working workaround in place.
Doing this comes at the cost of duplicating the VN IL on the PRE side
for NARY and eventually some extra overhead for translated expressions
that is difficult to assess.
2022-02-25 Richard Biener <rguenther@suse.de>
PR tree-optimization/103037
* tree-ssa-sccvn.h (alloc_vn_nary_op_noinit): Declare.
(vn_nary_length_from_stmt): Likewise.
(init_vn_nary_op_from_stmt): Likewise.
(vn_nary_op_compute_hash): Likewise.
* tree-ssa-sccvn.cc (alloc_vn_nary_op_noinit): Export.
(vn_nary_length_from_stmt): Likewise.
(init_vn_nary_op_from_stmt): Likewise.
(vn_nary_op_compute_hash): Likewise.
* tree-ssa-pre.cc (pre_expr_obstack): New obstack.
(get_or_alloc_expr_for_nary): Pass in the value-id to use,
(re-)compute the hash value and if the expression is not
found allocate it from pre_expr_obstack.
(phi_translate_1): Do not insert the NARY found in the
VN tables but build a PRE expression from the valueized
NARY with the value-id we eventually found.
(find_or_generate_expression): Assert we have an entry
for constant values.
(compute_avail): Insert not valueized expressions into
EXP_GEN using the value-id from the VN tables.
(init_pre): Allocate pre_expr_obstack.
(fini_pre): Free pre_expr_obstack.
Jakub Jelinek [Fri, 25 Feb 2022 11:06:52 +0000 (12:06 +0100)]
i386: Use a new temp slot kind for splitter to floatdi<mode>2_i387_with_xmm [PR104674]
As mentioned in the PR, the following testcase is miscompiled for similar
reasons as the already fixed PR78791 - we use SLOT_TEMP slots in various
places during expansion and during expansion we can guarantee that the
lifetime of those temporary slot doesn't overlap. But the following
splitter uses SLOT_TEMP too and in between expansion and split1 there is
a possibility that something extends the lifetime of SLOT_TEMP created
slots across an instruction that will be split by this splitter.
The following patch fixes it by using a new temp slot kind to make sure
it doesn't reuse a SLOT_TEMP that could be live across the instruction.
2022-02-25 Jakub Jelinek <jakub@redhat.com>
PR target/104674
* config/i386/i386.h (enum ix86_stack_slot): Add SLOT_FLOATxFDI_387.
* config/i386/i386.md (splitter to floatdi<mode>2_i387_with_xmm): Use
SLOT_FLOATxFDI_387 rather than SLOT_TEMP.
Jakub Jelinek [Fri, 25 Feb 2022 09:56:46 +0000 (10:56 +0100)]
internal-fn: Call do_pending_stack_adjust in expand_SPACESHIP [PR104679]
The following testcase is miscompiled on ia32 at -O2, because
when expand_SPACESHIP is called, we have pending stack adjustment
from the foo call right before it.
Now, ix86_expand_fp_spaceship uses emit_jump_insn several times
but then emit_jump also several times. While emit_jump_insn doesn't
do do_pending_stack_adjust (), emit_jump does, so we end up with:
...
8: call [`_Z3foodl'] argc:0x10
REG_CALL_DECL `_Z3foodl'
9: r88:DF=[`a']
10: r89:HI=unspec[cmp(r88:DF,0.0)] 25
11: flags:CC=unspec[r89:HI] 26
12: pc={(unordered(flags:CCFP,0))?L27:pc}
REG_BR_PROB 536868
66: NOTE_INSN_BASIC_BLOCK 4
13: pc={(uneq(flags:CCFP,0))?L19:pc}
REG_BR_PROB 214748364
67: NOTE_INSN_BASIC_BLOCK 5
14: pc={(flags:CCFP>0)?L23:pc}
REG_BR_PROB 536870916
68: NOTE_INSN_BASIC_BLOCK 6
15: r86:SI=0xffffffffffffffff
16: {sp:SI=sp:SI+0x10;clobber flags:CC;}
REG_ARGS_SIZE 0
17: pc=L29
18: barrier
19: L19:
69: NOTE_INSN_BASIC_BLOCK 7
...
The sp += 16 pending stuck adjust was emitted in the middle of the
sequence and is effective only for the single case of the 4 possibilities
where .SPACESHIP returns -1, in all other cases the stack isn't adjusted
and so we ICE during dwarf2cfi.
Now, we could either call do_pending_stack_adjust in
ix86_expand_fp_spaceship, or use there calls that actually don't call
do_pending_stack_adjust (but having the stack adjustment across branches is
generally undesirable), or we can call it in expand_SPACESHIP for all
targets (note, just i386 currently implements it).
I chose the generic code because e.g. expand_{addsub,neg,mul}_overflow
in the same file also call do_pending_stack_adjust in internal-fn.cc for the
same reasons, that it is expected that most if not all targets will expand
those through jumps and we don't want all of the targets to need to deal
with that.
Jakub Jelinek [Fri, 25 Feb 2022 09:55:17 +0000 (10:55 +0100)]
match.pd: Don't create BIT_NOT_EXPRs for COMPLEX_TYPE [PR104675]
We don't support BIT_{AND,IOR,XOR,NOT}_EXPR on complex types,
&/|/^ are just rejected for them, and ~ is parsed as CONJ_EXPR.
So, we should avoid simplifications which turn valid complex type
expressions into something that will ICE during expansion.
2022-02-25 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/104675
* match.pd (-A - 1 -> ~A, -1 - A -> ~A): Don't simplify for
COMPLEX_TYPE.
* gcc.dg/pr104675-1.c: New test.
* gcc.dg/pr104675-2.c: New test.
Alexandre Oliva [Fri, 25 Feb 2022 01:03:38 +0000 (22:03 -0300)]
Add testcase from PR103845
This problem was already fixed as part of PR104263: the abnormal edge
that remained from before inlining didn't make sense after inlining.
So this patch adds only the testcase.
Alexandre Oliva [Fri, 25 Feb 2022 01:03:34 +0000 (22:03 -0300)]
Cope with NULL dw_cfi_cfa_loc
In def_cfa_0, we may set the 2nd operand's dw_cfi_cfa_loc to NULL, but
then cfi_oprnd_equal_p calls cfa_equal_p with a NULL dw_cfa_location*.
This patch aranges for us to tolerate NULL dw_cfi_cfa_loc.
for gcc/ChangeLog
PR middle-end/104540
* dwarf2cfi.cc (cfi_oprnd_equal_p): Cope with NULL
dw_cfi_cfa_loc.
Alexandre Oliva [Fri, 25 Feb 2022 01:03:32 +0000 (22:03 -0300)]
Copy EH phi args for throwing hardened compares
When we duplicate a throwing compare for hardening, the EH edge from
the original compare gets duplicated for the inverted compare, but we
failed to adjust any PHI nodes in the EH block. This patch adds the
needed adjustment, copying the PHI args from those of the preexisting
edge.
for gcc/ChangeLog
PR tree-optimization/103856
* gimple-harden-conditionals.cc (non_eh_succ_edge): Enable the
eh edge to be requested through an extra parameter.
(pass_harden_compares::execute): Copy PHI args in the EH dest
block for the new EH edge added for the inverted compare.
Jonathan Wakely [Thu, 24 Feb 2022 21:33:44 +0000 (21:33 +0000)]
libstdc++: Fix cast in source_location::current() [PR104602]
This fixes a problem for Clang, which is going to return a non-void
pointer from __builtin_source_location(). The current definition of
std::source_location::current() converts that to void* and then has to
cast it back again in the body (which makes it invalid in a constant
expression). By using the actual type of the returned pointer, we avoid
the problematic cast for Clang.
libstdc++-v3/ChangeLog:
PR libstdc++/104602
* include/std/source_location (source_location::current): Use
deduced type of __builtin_source_location().
Harald Anlauf [Wed, 23 Feb 2022 22:08:29 +0000 (23:08 +0100)]
Fortran: frontend code for F2018 QUIET specifier to STOP and ERROR STOP
Fortran 2018 allows for a QUIET specifier to the STOP and ERROR STOP
statements. Whilst the gfortran library code provides support for this
specifier for quite some time, the frontend implementation was missing.
gcc/fortran/ChangeLog:
PR fortran/84519
* dump-parse-tree.cc (show_code_node): Dump QUIET specifier when
present.
* match.cc (gfc_match_stopcode): Implement parsing of F2018 QUIET
specifier. F2018 stopcodes may have non-default integer kind.
* resolve.cc (gfc_resolve_code): Add checks for QUIET argument.
* trans-stmt.cc (gfc_trans_stop): Pass QUIET specifier to call of
library function.
gcc/testsuite/ChangeLog:
PR fortran/84519
* gfortran.dg/stop_1.f90: New test.
* gfortran.dg/stop_2.f: New test.
* gfortran.dg/stop_3.f90: New test.
* gfortran.dg/stop_4.f90: New test.
Palmer Dabbelt [Fri, 14 Jan 2022 02:10:19 +0000 (18:10 -0800)]
RISC-V: Document the degree of position independence that medany affords
The code generated by -mcmodel=medany is defined to be
position-independent, but is not guaranteed to function correctly when
linked into position-independent executables or libraries. See the
recent discussion at the psABI specification [1] for more details.
It would be better to reject these invalid sequences when linking, but
as pointed out in a recent LD bug [2] there may be some compatibility
issues related to the PCREL_HI20 relocations used to initialize GP.
Given the complexity here it's unlikely we'll be able to reject these
sequences any time soon, so instead just document that these may not
work.
Xi Ruoyao [Thu, 24 Feb 2022 17:45:57 +0000 (01:45 +0800)]
libgcc: fix a warning calling find_fde_tail
The third parameter of find_fde_tail is an _Unwind_Ptr (which is an
integer type instead of a pointer), but we are passing NULL to it. This
causes a -Wint-conversion warning.
libgcc/
* unwind-dw2-fde-dip.c (_Unwind_Find_FDE): Call find_fde_tail
with 0 instead of NULL.
Jose E. Marchesi [Wed, 23 Feb 2022 19:48:30 +0000 (20:48 +0100)]
bpf: do not --enable-gcov for bpf-*-* targets
This patch changes the build machinery in order to disable the build
of GCOV (both compiler and libgcc) in bpf-*-* targets. The reason for
this change is that BPF is (currently) too restricted in order to
support the coverage instrumentalization.
Tested in bpf-unknown-none and x86_64-linux-gnu targets.
2022-02-23 Jose E. Marchesi <jose.marchesi@oracle.com>
Jakub Jelinek [Thu, 24 Feb 2022 14:29:02 +0000 (15:29 +0100)]
sccvn: Fix visit_reference_op_call value numbering of vdefs [PR104601]
The following testcase is miscompiled, because -fipa-pure-const discovers
that bar is const, but when sccvn during fre3 sees
# .MEM_140 = VDEF <.MEM_96>
*__pred$__d_43 = _50 (_49);
where _50 value numbers to &bar, it value numbers .MEM_140 to
vuse_ssa_val (gimple_vuse (stmt)). For const/pure calls that return
a SSA_NAME (or don't have lhs) that is fine, those calls don't store
anything, but if the lhs is present and not an SSA_NAME, value numbering
the vdef to anything but itself means that e.g. walk_non_aliased_vuses
won't consider the call, but the call acts as a store to its lhs.
When it is ignored, sccvn will return whatever has been stored to the
lhs earlier.
I've bootstrapped/regtested an earlier version of this patch, which did the
if (!lhs && gimple_call_lhs (stmt))
changed |= set_ssa_val_to (vdef, vdef);
part before else if (vnresult->result_vdef), and that regressed
+FAIL: gcc.dg/pr51879-16.c scan-tree-dump-times pre "foo \\\\(" 1
+FAIL: gcc.dg/pr51879-16.c scan-tree-dump-times pre "foo2 \\\\(" 1
so this updated patch uses result_vdef there as before and only otherwise
(which I think must be the const/pure case) decides based on whether the
lhs is non-SSA_NAME.
2022-02-24 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/104601
* tree-ssa-sccvn.cc (visit_reference_op_call): For calls with
non-SSA_NAME lhs value number vdef to itself instead of e.g. the
vuse value number.
Add openmp test-cases that test the omp declare variant construct:
...
#pragma omp declare variant (f30) match (device={isa("sm_30")})
...
using the available nvptx isas.
Only the one for sm_30 is a dg-do run test-case, the other ones are dg-do
link.
Tested on x86_64 with nvptx accelerator.
libgomp/ChangeLog:
2022-02-24 Tom de Vries <tdevries@suse.de>
* testsuite/libgomp.c/declare-variant-3-sm30.c: New test.
* testsuite/libgomp.c/declare-variant-3-sm35.c: New test.
* testsuite/libgomp.c/declare-variant-3-sm53.c: New test.
* testsuite/libgomp.c/declare-variant-3-sm70.c: New test.
* testsuite/libgomp.c/declare-variant-3-sm75.c: New test.
* testsuite/libgomp.c/declare-variant-3-sm80.c: New test.
* testsuite/libgomp.c/declare-variant-3.h: New header file.
Tom de Vries [Wed, 23 Feb 2022 14:58:59 +0000 (15:58 +0100)]
[nvptx] Add missing t-omp-device isas
In t-omp-device we list isas that can be used in omp declare variant like so:
...
#pragma omp declare variant (f30) match (device={isa("sm_30")})
...
and in nvptx_omp_device_kind_arch_isa we handle them.
Update both to reflect the current list of isas.
Tested on x86_64-linux with nvptx accelerator.
gcc/ChangeLog:
2022-02-23 Tom de Vries <tdevries@suse.de>
* config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Handle
sm_70, sm_75 and sm_80.
* config/nvptx/t-omp-device: Add sm_53, sm_70, sm_75 and sm_80.
git://gcc.gnu.org / gcc.git / log