Uros Bizjak [Mon, 25 Mar 2013 18:09:36 +0000 (19:09 +0100)]
i386.md (*zero_extendsidi2): Merge with *zero_extendsidi2_rex64.
* config/i386/i386.md (*zero_extendsidi2): Merge with
*zero_extendsidi2_rex64. Use x64 and nox64 isa attributes.
* config/i386/predicates.md (x86_64_zext_operand): Rename from
x86_64_zext_general_operand. Use nonimmediate_operand on 32bit
targets. Clarify comment.
Martin Jambor [Mon, 25 Mar 2013 16:50:02 +0000 (17:50 +0100)]
ipa-prop.c (ipa_write_jump_function): Stream simple and aritmetic pass-through jump functions differently.
2013-03-25 Martin Jambor <mjambor@suse.cz>
* ipa-prop.c (ipa_write_jump_function): Stream simple and aritmetic
pass-through jump functions differently.
(ipa_read_jump_function): Likewise. Also use setter functions to set
up jump functions.
Martin Jambor [Mon, 25 Mar 2013 16:42:41 +0000 (17:42 +0100)]
ipa-cp.c (ipa_get_indirect_edge_target): Renamed to ipa_get_indirect_edge_target_1...
2013-03-25 Martin Jambor <mjambor@suse.cz>
* ipa-cp.c (ipa_get_indirect_edge_target): Renamed to
ipa_get_indirect_edge_target_1, added parameter agg_reps and ability to
process it.
(ipa_get_indirect_edge_target): New function.
(devirtualization_time_bonus): New parameter known_aggs, pass it to
ipa_get_indirect_edge_target. Update all callers.
(ipcp_discover_new_direct_edges): New parameter aggvals. Pass it to
ipa_get_indirect_edge_target_1 instead of calling
ipa_get_indirect_edge_target.
(create_specialized_node): Pass aggvlas to
ipcp_discover_new_direct_edges.
Kyrylo Tkachov [Mon, 25 Mar 2013 14:55:05 +0000 (14:55 +0000)]
Fix ChangeLog formatting.
gcc/
Fix ChangeLog formatting.
gcc/testsuite
2013-03-25 Kyrylo Tkachov <kyrylo.tkachov at arm.com>
* gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Move test
body from here...
* gcc.target/aarch64/atomic-comp-swap-release-acquire.x: ... to here.
* gcc.target/aarch64/atomic-op-acq_rel.c: Move test body from here...
* gcc.target/aarch64/atomic-op-acq_rel.x: ... to here.
* gcc.target/aarch64/atomic-op-acquire.c: Move test body from here...
* gcc.target/aarch64/atomic-op-acquire.x: ... to here.
* gcc.target/aarch64/atomic-op-char.c: Move test body from here...
* gcc.target/aarch64/atomic-op-char.x: ... to here.
* gcc.target/aarch64/atomic-op-consume.c: Move test body from here...
* gcc.target/aarch64/atomic-op-consume.x: ... to here.
* gcc.target/aarch64/atomic-op-int.c: Move test body from here...
* gcc.target/aarch64/atomic-op-int.x: ... to here.
* gcc.target/aarch64/atomic-op-relaxed.c: Move test body from here...
* gcc.target/aarch64/atomic-op-relaxed.x: ... to here.
* gcc.target/aarch64/atomic-op-release.c: Move test body from here...
* gcc.target/aarch64/atomic-op-release.x: ... to here.
* gcc.target/aarch64/atomic-op-seq_cst.c: Move test body from here...
* gcc.target/aarch64/atomic-op-seq_cst.x: ... to here.
* gcc.target/aarch64/atomic-op-short.c: Move test body from here...
* gcc.target/aarch64/atomic-op-short.x: ... to here.
* gcc.target/arm/atomic-comp-swap-release-acquire.c: New test.
* gcc.target/arm/atomic-op-acq_rel.c: Likewise.
* gcc.target/arm/atomic-op-acquire.c: Likewise.
* gcc.target/arm/atomic-op-char.c: Likewise.
* gcc.target/arm/atomic-op-consume.c: Likewise.
* gcc.target/arm/atomic-op-int.c: Likewise.
* gcc.target/arm/atomic-op-relaxed.c: Likewise.
* gcc.target/arm/atomic-op-release.c: Likewise.
* gcc.target/arm/atomic-op-seq_cst.c: Likewise.
* gcc.target/arm/atomic-op-short.c: Likewise.
Uros Bizjak [Sun, 24 Mar 2013 18:26:48 +0000 (19:26 +0100)]
sse.md (mov<mode>): Merge with movv2sf expander using MMXMODE mode iterator.
* config/i386/sse.md (mov<mode>): Merge with movv2sf expander
using MMXMODE mode iterator.
(*move<mode>_internal): Merge with *movv2sf_internal and
*movv2sf_internal_rex64 using MMXMODE mode iterator.
Andi Kleen [Sun, 24 Mar 2013 00:23:10 +0000 (00:23 +0000)]
Avoid non constant memory model uses in libatomic
x86 ends up using non constant memory models for some of the libatomic
functions. These all end up as __ATOMIC_SEQ_CST. Just use this
directly. This avoids a new warning for non constant memory
models, which broke the bootstrap with -Werror
Passed bootstrap and test on x86_64-linux.
libatomic/:
2013-03-23 Andi Kleen <ak@linux.intel.com>
* gcas.c: (EXACT_INLINE): Use __ATOMIC_SEQ_CST.
* gexch.c: (EXACT_INLINE): Use __ATOMIC_SEQ_CST.
* gload.c: (EXACT_INLINE): Use __ATOMIC_SEQ_CST.
* gstore.c: (EXACT_INLINE): Use __ATOMIC_SEQ_CST.
Steven Bosscher [Sat, 23 Mar 2013 21:40:20 +0000 (21:40 +0000)]
df-core.c (rest_of_handle_df_initialize): Use XCNEWVEC instead of XNEWVEC followed by memset.
* df-core.c (rest_of_handle_df_initialize): Use XCNEWVEC instead
of XNEWVEC followed by memset.
(df_worklist_dataflow): Use XNEWVEC instead of xmalloc with a cast.
Eric Botcazou [Sat, 23 Mar 2013 11:06:21 +0000 (11:06 +0000)]
combine.c (try_combine): Adjust comment.
* combine.c (try_combine): Adjust comment. Do not add the set of
insn #0 if the destination indirectly is set or dies in insn #2.
Tidy up code to distribute a new note.
Uros Bizjak [Fri, 22 Mar 2013 18:40:13 +0000 (19:40 +0100)]
sse.md (*mov<mode>_internal): Merge with *mov<mode>_internal_rex64.
* config/i386/sse.md (*mov<mode>_internal): Merge with
*mov<mode>_internal_rex64. Use x64 and nox64 isa attributes.
Emit insn template depending on type attribute. Use
HAVE_AS_IX86_INTERUNIT_MOVQ to handle broken assemblers that require
movd instead of movq mnemonic for interunit moves. Rewrite mode
attribute calculation. Remove unit attribute calculation.
Set prefix attribute to maybe_vex for sselog1 and ssemov types.
Set prefix_data16 attribute for DImode ssemov types.
Use Ym instead of y for SSE-MMX conversion alternatives.
Reorder operand constraints.
Steven Bosscher [Fri, 22 Mar 2013 16:37:24 +0000 (16:37 +0000)]
df.h (df_insn_delete): Adjust prototype.
* df.h (df_insn_delete): Adjust prototype.
* emit-rtl.c (remove_insn): Pass a basic block to df_insn_delete
and let it decide whether mark the basic block dirty.
(set_insn_deleted): Only pass INSN_P insns to df_insn_delete.
* df-scan.c (df_insn_info_delete): New helper function, split
off from df_insn_delete.
(df_scan_free_bb_info): Use it.
(df_insn_rescan, df_insn_rescan_all, df_process_deferred_rescans):
Likewise.
(df_insn_delete): Likewise. Take insn rtx as argument. Verify
that the insn is actually an insn and it has a non-NULL basic block.
Do not mark basic block dirty if only deleting a DEBUG_INSN.
Steven Bosscher [Fri, 22 Mar 2013 16:37:00 +0000 (16:37 +0000)]
df.h (df_insn_delete): Adjust prototype.
* df.h (df_insn_delete): Adjust prototype.
* emit-rtl.c (remove_insn): Pass a basic block to df_insn_delete
and let it decide whether mark the basic block dirty.
(set_insn_deleted): Only pass INSN_P insns to df_insn_delete.
* df-scan.c (df_insn_info_delete): New helper function, split
off from df_insn_delete.
(df_scan_free_bb_info): Use it.
(df_insn_rescan, df_insn_rescan_all, df_process_deferred_rescans):
Likewise.
(df_insn_delete): Likewise. Take insn rtx as argument. Verify
that the insn is actually an insn and it has a non-NULL basic block.
Do not mark basic block dirty if only deleting a DEBUG_INSN.
Richard Biener [Fri, 22 Mar 2013 13:07:20 +0000 (13:07 +0000)]
tree-ssa-loop-im.c (struct mem_ref): Remove indep_ref and dep_ref members.
2013-03-22 Richard Biener <rguenther@suse.de>
* tree-ssa-loop-im.c (struct mem_ref): Remove indep_ref and
dep_ref members.
(mem_ref_alloc): Do not allocate them.
(refs_independent_p): Do not query or maintain a cache.
Richard Biener [Fri, 22 Mar 2013 13:06:33 +0000 (13:06 +0000)]
tree-ssa-loop-im.c (memory_references): Drop all_refs_in_loop.
2013-03-22 Richard Biener <rguenther@suse.de>
* tree-ssa-loop-im.c (memory_references): Drop all_refs_in_loop.
(gather_mem_refs_in_loops): Do not compute it.
(analyze_memory_references): Do not allocate it.
(tree_ssa_lim_finalize): Do not free it.
(for_all_locs_in_loop): Do not query all_refs_in_loop.
* tree-ssa-loop-im.c (memory_references): Add refs_stored_in_loop
bitmaps.
(gather_mem_refs_in_loops): Perform store accumulation here.
(create_vop_ref_mapping_loop): Remove.
(create_vop_ref_mapping): Likewise.
(analyze_memory_references): Initialize refs_stored_in_loop.
(LOOP_DEP_BIT): New define to map to bits in (in)dep_loop
bitmaps.
(record_indep_loop): Remove.
(record_dep_loop): New function.
(ref_indep_loop_p_1): Adjust to only walk over references
in the loop, not its subloops.
(ref_indep_loop_p): Rename to ...
(ref_indep_loop_p_2): ... this and recurse over the loop tree,
maintaining a more fine-grained cache.
(ref_indep_loop_p): Wrap ref_indep_loop_p_2.
(tree_ssa_lim_finalize): Free refs_stored_in_loop.
Richard Biener [Fri, 22 Mar 2013 09:12:46 +0000 (09:12 +0000)]
tree-ssa-loop-im.c (struct mem_ref_locs): Remove.
2013-03-22 Richard Biener <rguenther@suse.de>
* tree-ssa-loop-im.c (struct mem_ref_locs): Remove.
(struct mem_ref): Make accesses_in_loop a vec of a vec of
aggregate mem_ref_loc.
(free_mem_ref_locs): Inline into ...
(memref_free): ... this and adjust.
(mem_ref_alloc): Adjust.
(mem_ref_locs_alloc): Remove.
(record_mem_ref_loc): Adjust.
(get_all_locs_in_loop): Rewrite into ...
(for_all_locs_in_loop): ... this iterator.
(rewrite_mem_ref_loc): New functor.
(rewrite_mem_refs): Use for_all_locs_in_loop.
(sm_set_flag_if_changed): New functor.
(execute_sm_if_changed_flag_set): Use for_all_locs_in_loop.
(ref_always_accessed): New functor.
(ref_always_accessed_p): Use for_all_locs_in_loop.
Jakub Jelinek [Thu, 21 Mar 2013 17:36:47 +0000 (18:36 +0100)]
re PR middle-end/48087 (-Wall -Werror adds warnings over and above those generated by -Wall)
PR middle-end/48087
* diagnostic.def (DK_WERROR): New kind.
* diagnostic.h (werrorcount): Define.
* diagnostic.c (diagnostic_report_diagnostic): For DK_WARNING
promoted to DK_ERROR, increment DK_WERROR counter instead of
DK_ERROR counter.
* toplev.c (toplev_main): Call print_ignored_options even if
just werrorcount is non-zero. Exit with FATAL_EXIT_CODE
even if just werrorcount is non-zero.
Jakub Jelinek [Thu, 21 Mar 2013 17:35:39 +0000 (18:35 +0100)]
re PR debug/55608 (Debug info quality regressions with file scope vars)
PR debug/55608
* dwarf2out.c (tree_add_const_value_attribute): Call ggc_free (array)
on failure.
(resolve_one_addr): Fail if referenced STRING_CST hasn't been written.
(string_cst_pool_decl): New function.
(optimize_one_addr_into_implicit_ptr): New function.
(resolve_addr_in_expr): Optimize DWARF location expression
DW_OP_addr DW_OP_stack_value where DW_OP_addr refers to some variable
which doesn't live in memory, but has DW_AT_location or
DW_AT_const_value, or refers to a string literal, into
DW_OP_GNU_implicit_pointer.
(optimize_location_into_implicit_ptr): New function.
(resolve_addr): If removing DW_AT_location of a variable because
it was DW_OP_addr of address of the variable, but the variable doesn't
live in memory, try to emit const value attribute for the initializer.
Marc Glisse [Thu, 21 Mar 2013 16:33:33 +0000 (17:33 +0100)]
tree.h (VECTOR_TYPE_P): New macro.
2013-03-21 Marc Glisse <marc.glisse@inria.fr>
gcc/
* tree.h (VECTOR_TYPE_P): New macro.
(VECTOR_INTEGER_TYPE_P, VECTOR_FLOAT_TYPE_P, FLOAT_TYPE_P,
TYPE_MODE): Use it.
* fold-const.c (fold_cond_expr_with_comparison): Use build_zero_cst.
VEC_COND_EXPR cannot be lvalues.
(fold_ternary_loc) <VEC_COND_EXPR>: Merge with the COND_EXPR case.
Richard Biener [Thu, 21 Mar 2013 14:45:36 +0000 (14:45 +0000)]
re PR middle-end/39326 (Segmentation fault with -O1, out of memory with -O2)
2013-03-21 Richard Biener <rguenther@suse.de>
PR tree-optimization/39326
* tree-ssa-loop-im.c (UNANALYZABLE_MEM_ID): New define.
(MEM_ANALYZABLE): Adjust.
(record_mem_ref_loc): Move bitmap ops ...
(gather_mem_refs_stmt): ... here. Use the shared mem-ref for
unanalyzable refs, do not record locations for it.
(analyze_memory_references): Allocate ref zero as shared
unanalyzable ref.
(refs_independent_p): Do not test for unanalyzed mems here.
(ref_indep_loop_p_1): Special-case disambiguation against
the unanalyzed ref.
(ref_indep_loop_p): Assert we are not queried for the
unanalyzed mem.
Richard Biener [Thu, 21 Mar 2013 13:53:01 +0000 (13:53 +0000)]
re PR middle-end/39326 (Segmentation fault with -O1, out of memory with -O2)
2013-03-21 Richard Biener <rguenther@suse.de>
PR tree-optimization/39326
* tree-ssa-loop-im.c (bb_loop_postorder): New global static.
(sort_bbs_in_loop_postorder_cmp): New function.
(gather_mem_refs_in_loops): Assign mem-ref IDs in loop
postorder.
* tree-vect-data-refs.c (vect_update_interleaving_chain): Remove.
(vect_insert_into_interleaving_chain): Likewise.
(vect_drs_dependent_in_basic_block): Inline ...
(vect_slp_analyze_data_ref_dependence): ... here. New function,
split out from ...
(vect_analyze_data_ref_dependence): ... here. Simplify.
(vect_check_interleaving): Simplify.
(vect_analyze_data_ref_dependences): Likewise. Split out ...
(vect_slp_analyze_data_ref_dependences): ... this new function.
(dr_group_sort_cmp): New function.
(vect_analyze_data_ref_accesses): Compute data-reference groups
here instead of in vect_analyze_data_ref_dependence. Use
a more efficient algorithm.
* tree-vect-slp.c (vect_slp_analyze_bb_1): Use
vect_slp_analyze_data_ref_dependences. Call
vect_analyze_data_ref_accesses earlier.
* tree-vect-loop.c (vect_analyze_loop_2): Likewise.
* tree-vectorizer.h (vect_analyze_data_ref_dependences): Adjust.
(vect_slp_analyze_data_ref_dependences): New prototype.
Richard Biener [Thu, 21 Mar 2013 12:35:03 +0000 (12:35 +0000)]
tree-ssa-loop-im.c (can_sm_ref_p): Do not test whether ref is stored in the loop.
2013-03-21 Richard Biener <rguenther@suse.de>
* tree-ssa-loop-im.c (can_sm_ref_p): Do not test whether
ref is stored in the loop.
(find_refs_for_sm): Walk only over all stores.
(store_motion_loop): Allocate from lim_bitmap_obstack.
(store_motion): Likewise.
Richard Biener [Thu, 21 Mar 2013 11:54:27 +0000 (11:54 +0000)]
tree-cfg.c (verify_expr_no_block): New function.
2013-03-21 Richard Biener <rguenther@suse.de>
* tree-cfg.c (verify_expr_no_block): New function.
(verify_expr_location_1): Verify that neither DECL_DEBUG_EXPR
nor DECL_VALUE_EXPR have locations with associated blocks.
* tree-ssa-live.c (clear_unused_block_pointer_1): Remove.
(clear_unused_block_pointer): Remove code dealing with
blocks in DECL_DEBUG_EXPR locations.
* gcc.target/aarch64/vect.c: Test and result vector added
for sabd and saba instructions.
* gcc.target/aarch64/vect-compile.c: Check for sabd and saba
instructions in assembly.
* gcc.target/aarch64/vect.x: Add sabd and saba test functions.
* gcc.target/aarch64/vect-fp.c: Test and result vector added
for fabd instruction.
* gcc.target/aarch64/vect-fp-compile.c: Check for fabd
instruction in assembly.
* gcc.target/aarch64/vect-fp.x: Add fabd test function.
* config/aarch64/aarch64-elf.h (REGISTER_PREFIX): Remove.
* config/aarch64/aarch64.c (aarch64_print_operand): Remove all
occurrence of REGISTER_PREFIX as its empty string.
Jeff Law [Thu, 21 Mar 2013 04:42:40 +0000 (22:42 -0600)]
tree-ssa-dom.c (record_equivalences_from_incoming_edge): Record addititional equivalences for equality comparisons between an SSA_NAME...
* tree-ssa-dom.c (record_equivalences_from_incoming_edge): Record
addititional equivalences for equality comparisons between an SSA_NAME
and a constant where the SSA_NAME was set from a widening conversion.
Jason Merrill [Thu, 21 Mar 2013 03:25:35 +0000 (23:25 -0400)]
re PR c++/54532 ([C++0x][constexpr] internal error when initializing static constexpr with pointer to non-static member variable)
PR c++/54532
* expr.c (cplus_expand_constant): Do nothing if the class is
incomplete.
* semantics.c (reduced_constant_expression_p): Allow PTRMEM_CST.
* typeck2.c (store_init_value): Use reduced_constant_expression_p.
* decl.c (maybe_register_incomplete_var): Handle PTRMEM_CST.
(complete_vars): Likewise.
Uros Bizjak [Wed, 20 Mar 2013 16:49:06 +0000 (17:49 +0100)]
i386.md (*movti_internal): Set prefix attribute to maybe_vex for sselog1 and ssemov types.
* config/i386/i386.md (*movti_internal): Set prefix attribute to
maybe_vex for sselog1 and ssemov types.
(*movdi_internal): Reorder operand constraints.
(*movsi_internal): Ditto. Set prefix attribute to
maybe_vex for sselog1 and ssemov types.
(*movtf_internal): Set prefix attribute to maybe_vex
for sselog1 and ssemov types.
(*movdf_internal): Ditto. Set prefix_data16 attribute for
DImode ssemov types. Reorder operand constraints.
(*movsf_internal): Set type of alternatives 3,4 to imov. Set prefix
attribute to maybe_vex for sselog1 and ssemov types. Set prefix_data16
attribute for SImode ssemov types. Reorder operand constraints.
2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vector.md (VEC_R): Add 32-bit integer, binary
floating point, and decimal floating point to reload iterator.
* config/rs6000/constraints.md (wl constraint): New constraints to
return FLOAT_REGS if certain options are used to reduce the number
of separate patterns that exist in the file.
(wx constraint): Likewise.
(wz constraint): Likewise.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): If
-mdebug=reg, print wg, wl, wx, and wz constraints.
(rs6000_init_hard_regno_mode_ok): Initialize new constraints.
Initialize the reload functions for 64-bit binary/decimal floating
point types.
(reg_offset_addressing_ok_p): If we are on a power7 or later, use
LFIWZX and STFIWX to load/store 32-bit decimal types, and don't
create the buffer on the stack to overcome not having a 32-bit
load and store.
(rs6000_emit_move): Likewise.
(rs6000_secondary_memory_needed_rtx): Likewise.
(rs6000_alloc_sdmode_stack_slot): Likewise.
(rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f
via xxlxor, just like DFmode 0.0.
* config/rs6000/rs6000.h (TARGET_NO_SDMODE_STACK): New macro,
define as 1 if we are running on a power7 or newer.
(enum r6000_reg_class_enum): Add new constraints.
* config/rs6000/dfp.md (movsd): Delete, combine with binary
floating point moves in rs6000.md. Combine power6x (mfpgpr) moves
with other moves by using conditional constraits (wg). Use LFIWZX
and STFIWX for loading SDmode on power7. Use xxlxor to create
0.0f.
(movsd splitter): Likewise.
(movsd_hardfloat): Likewise.
(movsd_softfloat): Likewise.
* config/rs6000/rs6000.md (FMOVE32): New iterators to combine
binary and decimal floating point moves.
(fmove_ok): New attributes to combine binary and decimal floating
point moves, and to combine power6x (mfpgpr) moves along normal
floating moves.
(real_value_to_target): Likewise.
(f32_lr): Likewise.
(f32_lm): Likewise.
(f32_li): Likewise.
(f32_sr): Likewise.
(f32_sm): Likewise.
(f32_si): Likewise.
(movsf): Combine binary and decimal floating point moves. Combine
power6x (mfpgpr) moves with other moves by using conditional
constraits (wg). Use LFIWZX and STFIWX for loading SDmode on
power7.
(mov<mode> for SFmode/SDmode); Likewise.
(SFmode/SDmode splitters): Likewise.
(movsf_hardfloat): Likewise.
(mov<mode>_hardfloat for SFmode/SDmode): Likewise.
(movsf_softfloat): Likewise.
(mov<mode>_softfloat for SFmode/SDmode): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document wl,
wx and wz constraints.
* config/rs6000/constraints.md (wg constraint): New constraint to
return FLOAT_REGS if -mmfpgpr (power6x) was used.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wg
constraint.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): If
-mdebug=reg, print wg, wl, wx, and wz constraints.
(rs6000_init_hard_regno_mode_ok): Initialize new constraints.
Initialize the reload functions for 64-bit binary/decimal floating
point types.
(reg_offset_addressing_ok_p): If we are on a power7 or later, use
LFIWZX and STFIWX to load/store 32-bit decimal types, and don't
create the buffer on the stack to overcome not having a 32-bit
load and store.
(rs6000_emit_move): Likewise.
(rs6000_secondary_memory_needed_rtx): Likewise.
(rs6000_alloc_sdmode_stack_slot): Likewise.
(rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f
via xxlxor, just like DFmode 0.0.
* config/rs6000/dfp.md (movdd): Delete, combine with binary
floating point moves in rs6000.md. Combine power6x (mfpgpr) moves
with other moves by using conditional constraits (wg). Use LFIWZX
and STFIWX for loading SDmode on power7.
(movdd splitters): Likewise.
(movdd_hardfloat32): Likewise.
(movdd_softfloat32): Likewise.
(movdd_hardfloat64_mfpgpr): Likewise.
(movdd_hardfloat64): Likewise.
(movdd_softfloat64): Likewise.
* config/rs6000/rs6000.md (FMOVE64): New iterators to combine
64-bit binary and decimal floating point moves.
(FMOVE64X): Likewise.
(movdf): Combine 64-bit binary and decimal floating point moves.
Combine power6x (mfpgpr) moves with other moves by using
conditional constraits (wg).
(mov<mode> for DFmode/DDmode): Likewise.
(DFmode/DDmode splitters): Likewise.
(movdf_hardfloat32): Likewise.
(mov<mode>_hardfloat32 for DFmode/DDmode): Likewise.
(movdf_softfloat32): Likewise.
(movdf_hardfloat64_mfpgpr): Likewise.
(movdf_hardfloat64): Likewise.
(mov<mode>_hardfloat64 for DFmode/DDmode): Likewise.
(movdf_softfloat64): Likewise.
(mov<mode>_softfloat64 for DFmode/DDmode): Likewise.
(reload_<mode>_load): Move to later in the file so they aren't in
the middle of the floating point move insns.
(reload_<mode>_store): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document wg
constraint.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Print out wg
constraint if -mdebug=reg.
(rs6000_initi_hard_regno_mode_ok): Enable wg constraint if
-mfpgpr. Enable using dd reload support if needed.
* config/rs6000/dfp.md (movtd): Delete, combine with 128-bit
binary and decimal floating point moves in rs6000.md.
(movtd_internal): Likewise.
* config/rs6000/rs6000.md (movdi_mfpgpr): Delete, combine with
movdi_internal64, using wg constraint for move direct operations.
(movdi_internal64): Likewise.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Print
MODES_TIEABLE_P for selected modes. Print the numerical value of
the various virtual registers. Use GPR/FPR first/last values,
instead of hard coding the register numbers. Print which modes
have reload functions registered.
(rs6000_option_override_internal): If -mdebug=reg, trace the
options settings before/after setting cpu, target and subtarget
settings.
(rs6000_secondary_reload_trace): Improve the RTL dump for
-mdebug=addr and for secondary reload failures in
rs6000_secondary_reload_inner.
(rs6000_secondary_reload_fail): Likewise.
(rs6000_secondary_reload_inner): Likewise.
* config/rs6000/rs6000.md (FIRST_GPR_REGNO): Add convenience
macros for first/last GPR and FPR registers.
(LAST_GPR_REGNO): Likewise.
(FIRST_FPR_REGNO): Likewise.
(LAST_FPR_REGNO): Likewise.
* config/rs6000/vector.md (mul<mode>3): Use the combined macro
VECTOR_UNIT_ALTIVEC_OR_VSX_P instead of separate calls to
VECTOR_UNIT_ALTIVEC_P and VECTOR_UNIT_VSX_P.
(vcond<mode><mode>): Likewise.
(vcondu<mode><mode>): Likewise.
(vector_gtu<mode>): Likewise.
(vector_gte<mode>): Likewise.
(xor<mode>3): Don't allow logical operations on TImode in 32-bit
to prevent the compiler from converting DImode operations to
TImode.
(ior<mode>3): Likewise.
(and<mode>3): Likewise.
(one_cmpl<mode>2): Likewise.
(nor<mode>3): Likewise.
(andc<mode>3): Likewise.
* config/rs6000/constraints.md (wt constraint): New constraint
that returns VSX_REGS if TImode is allowed in VSX registers.
* config/rs6000/predicates.md (easy_fp_constant): 0.0f is an easy
constant under VSX.
* config/rs6000/rs6000-modes.def (PTImode): Define, PTImode is
similar to TImode, but it is restricted to being in the GPRs.
* config/rs6000/rs6000.opt (-mvsx-timode): New switch to allow
TImode to occupy a single VSX register.
* config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Default to
-mvsx-timode for power7/power8.
(power7 cpu): Likewise.
(power8 cpu): Likewise.
* config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Make
sure that TFmode/TDmode take up two registers if they are ever
allowed in the upper VSX registers.
(rs6000_hard_regno_mode_ok): If -mvsx-timode, allow TImode in VSX
registers.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_debug_reg_global): Add debugging for PTImode and wt
constraint. Print if LRA is turned on.
(rs6000_option_override_internal): Give an error if -mvsx-timode
and VSX is not enabled.
(invalid_e500_subreg): Handle PTImode, restricting it to GPRs. If
-mvsx-timode, restrict TImode to reg+reg addressing, and PTImode
to reg+offset addressing. Use PTImode when checking offset
addresses for validity.
(reg_offset_addressing_ok_p): Likewise.
(rs6000_legitimate_offset_address_p): Likewise.
(rs6000_legitimize_address): Likewise.
(rs6000_legitimize_reload_address): Likewise.
(rs6000_legitimate_address_p): Likewise.
(rs6000_eliminate_indexed_memrefs): Likewise.
(rs6000_emit_move): Likewise.
(rs6000_secondary_reload): Likewise.
(rs6000_secondary_reload_inner): Handle PTImode. Allow 64-bit
reloads to fpr registers to continue to use reg+offset addressing,
but 64-bit reloads to altivec registers need reg+reg addressing.
Drop test for PRE_MODIFY, since VSX loads/stores no longer support
it. Treat LO_SUM like a PLUS operation.
(rs6000_secondary_reload_class): If type is 64-bit, prefer to use
FLOAT_REGS instead of VSX_RGS to allow use of reg+offset
addressing.
(rs6000_cannot_change_mode_class): Do not allow TImode in VSX
registers to share a register with a smaller sized type, since VSX
puts scalars in the upper 64-bits.
(print_operand): Add support for PTImode.
(rs6000_register_move_cost): Use VECTOR_MEM_VSX_P instead of
VECTOR_UNIT_VSX_P to catch types that can be loaded in VSX
registers, but don't have arithmetic support.
(rs6000_memory_move_cost): Add test for VSX.
(rs6000_opt_masks): Add -mvsx-timode.
* config/rs6000/vsx.md (VSm): Change to use 64-bit aligned moves
for TImode.
(VSs): Likewise.
(VSr): Use wt constraint for TImode.
(VSv): Drop TImode support.
(vsx_movti): Delete, replace with versions for 32-bit and 64-bit.
(vsx_movti_64bit): Likewise.
(vsx_movti_32bit): Likewise.
(vec_store_<mode>): Use VSX iterator instead of vector iterator.
(vsx_and<mode>3): Delete use of '?' constraint on inputs, just put
one '?' on the appropriate output constraint. Do not allow TImode
logical operations on 32-bit systems.
(vsx_ior<mode>3): Likewise.
(vsx_xor<mode>3): Likewise.
(vsx_one_cmpl<mode>2): Likewise.
(vsx_nor<mode>3): Likewise.
(vsx_andc<mode>3): Likewise.
(vsx_concat_<mode>): Likewise.
(vsx_xxpermdi_<mode>): Fix thinko for non V2DF/V2DI modes.
* config/rs6000/rs6000.h (MASK_VSX_TIMODE): Map from
OPTION_MASK_VSX_TIMODE.
(enum rs6000_reg_class_enum): Add RS6000_CONSTRAINT_wt.
(STACK_SAVEAREA_MODE): Use PTImode instead of TImode.
* config/rs6000/rs6000.md (INT mode attribute): Add PTImode.
(TI2 iterator): New iterator for TImode, PTImode.
(wd mode attribute): Add values for vector types.
(movti_string): Replace TI move operations with operations for
TImode and PTImode. Add support for TImode being allowed in VSX
registers.
(mov<mode>_string, TImode/PTImode): Likewise.
(movti_ppc64): Likewise.
(mov<mode>_ppc64, TImode/PTImode): Likewise.
(TI mode splitters): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document wt
constraint.
[gcc/testsuite]
2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com>
Catherine Moore [Wed, 20 Mar 2013 14:37:52 +0000 (10:37 -0400)]
extend.texi: (micromips, nomicromips, nocompression): Document new function attributes.
gcc/
2013-03-20 Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
Tom de Vries <tom@codesourcery.com>
Nathan Sidwell <nathan@codesourcery.com>
Iain Sandoe <iain@codesourcery.com>
Nathan Froyd <froydnj@codesourcery.com>
Chao-ying Fu <fu@mips.com>
* doc/extend.texi: (micromips, nomicromips, nocompression):
Document new function attributes.
* doc/invoke.texi (minterlink-compressed, mmicromips,
m14k, m14ke, m14kec): Document new options.
(minterlink-mips16): Update documentation.
* doc/md.texi (ZC, ZD): Document new constraints.
* configure.ac (gcc_cv_as_micromips): Check if linker
supports the .set micromips directive.
* configure: Regenerate.
* config.in: Regenerate.
* config/mips/mips-tables.opt: Regenerate.
* config/mips/micromips.md: New file.
* constraints.md (ZC, ZD): New constraints.
* config/mips/predicates.md (movep_src_register): New predicate.
(movep_src_operand): New predicate.
(non_volatile_mem_operand): New predicate.
* config/mips/mips.md (multimem): New type.
(length): Differentiate between 17-bit and 18-bit branch offsets.
(MOVEP1, MOVEP2): New mode iterator.
(mov_<load>l): Use ZC constraint.
(mov_<load>r): Likewise.
(mov_<store>l): Likewise.
(mov_<store>r): Likewise.
(*branch_equality<mode>_inverted): Add microMIPS support.
(*branch_equality<mode>): Likewise.
(*jump_absolute): Likewise.
(indirect_jump_<mode>): Likewise.
(tablejump_<mode>): Likewise.
(<optab>_internal): Likewise.
(sibcall_internal): Likewise.
(sibcall_value_internal): Likewise.
(prefetch): Use constraint ZD.
* config/mips/mips.opt (minterlink-compressed): New option.
(minterlink-mips16): Now an alias for minterlink-compressed.
(mmicromips): New option.
* config/mips/sync.md (sync_compare_and_swap<mode>): Use ZR constraint.
(compare_and_swap_12): Likewise.
(sync_add<mode>): Likewise.
(sync_<optab>_12): Likewise.
(sync_old_<optab>_12): Likewise.
(sync_new_<optab>_12): Likewise.
(sync_nand_12): Likewise.
(sync_old_nand_12): Likewise.
(sync_new_nand_12): Likewise.
(sync_sub<mode>): Likewise.
(sync_old_add<mode>): Likewise.
(sync_old_sub<mode>): Likewise.
(sync_new_add<mode>): Likewise.
(sync_new_sub<mode>): Likewise.
(sync_<optab><mode>): Likewise.
(sync_old_<optab><mode>): Likewise.
(sync_new_<optab><mode>): Likewise.
(sync_nand<mode>): Likewise.
(sync_old_nand<mode>): Likewise.
(sync_new_nand<mode>): Likewise.
(sync_lock_test_and_set<mode>): Likewise.
(test_and_set_12): Likewise.
(atomic_compare_and_swap<mode>): Likewise.
(atomic_exchange<mode>_llsc): Likewise.
(atomic_fetch_add<mode>_llsc): Likewise.
* config/mips/mips-cpus.def (m14kc, m14k): New processors.
* config/mips/mips-protos.h (umips_output_save_restore): New prototype.
(umips_save_restore_pattern_p): Likewise.
(umips_load_store_pair_p): Likewise.
(umips_output_load_store_pair): Likewise.
(umips_movep_target_p): Likewise.
(umips_12bit_offset_address_p): Likewise.
* config/mips/mips.c (MIPS_MAX_FIRST_STEP): Update for microMIPS.
(mips_base_mips16): Rename this...
(mips_base_compression_flags): ...to this. Update all uses.
(mips_attribute_table): Add micromips, nomicromips and nocompression.
(mips_mips16_decl_p): Delete.
(mips_nomips16_decl_p): Delete.
(mips_get_compress_on_flags): New function.
(mips_get_compress_off_flags): New function.
(mips_get_compress_mode): New function.
(mips_get_compress_on_name): New function.
(mips_get_compress_off_name): New function.
(mips_insert_attributes): Support multiple compression types.
(mips_merge_decl_attributes): Likewise.
(umips_12bit_offset_address_p): New function.
(mips_start_function_definition): Emit .set micromips directive.
(mips_call_may_need_jalx_p): New function.
(mips_function_ok_for_sibcall): Add microMIPS support.
(mips_print_operand_punctuation): Support short delay slots and
compact jumps.
(umips_swm_mask, umips_swm_encoding): New.
(umips_build_save_restore): New function.
(mips_for_each_saved_gpr_and_fpr): Add microMIPS support.
(was_mips16_p): Remove.
(old_compression_mode): New.
(mips_set_compression_mode): New function.
(mips_set_current_function): Add microMIPS support.
(mips_option_override): Likewise.
(umips_save_restore_pattern_p): New function.
(umips_output_save_restore): New function.
(umips_load_store_pair_p_1): New function.
(umips_load_store_pair_p): New function.
(umips_output_load_store_pair_1): New function.
(umips_output_load_store_pair): New function.
(umips_movep_target_p) New function.
(mips_prepare_pch_save): Add microMIPS support.
* config/mips/mips.h (TARGET_COMPRESSION): New.
(TARGET_CPU_CPP_BUILTINS): Update macro
to use new compression flags and to support microMIPS.
(MIPS_ISA_LEVEL_SPEC): Add m14k processors.
(MIPS_ARCH_FLOAT_SPEC): Likewise.
(ISA_HAS_LWXS): Include TARGET_MICROMIPS.
(ISA_HAS_LOAD_DELAY): Exclude TARGET_MICROMIPS.
(ASM_SPEC): Support mmicromips and mno-micromips.
(M16STORE_REG_P): New macro.
(MIPS_CALL): Support TARGET_MICROMIPS.
(MICROMIPS_J): New macro.
(mips_base_mips16): Rename this...
(mips_base_compression_flags): ...to this.
(UMIPS_12BIT_OFFSET_P): New macro.
* config/mips/t-sde: (MULTILIB_OPTIONS): Add microMIPS.
(MULTILIB_DIRNAMES): Likewise.
libgcc/
2013-03-20 Catherine Moore <clm@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Chao-ying Fu <fu@mips.com>
* config/mips/mips16.S: Don't build for microMIPS.
* config/mips/linux-unwind.h: Handle microMIPS frame.
* config/mips/crtn.S (fini, init): New labels.
gcc/testsuite/
2013-03-20 Catherine Moore <clm@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>
* gcc.target/mips/mips.exp: Add microMIPS support.
* gcc.target/mips/umips-movep-2.c: New test.
* gcc.target/mips/umips-lwp-2.c: New test.
* gcc.target/mips/umips-swp-5.c: New test.
* gcc.target/mips/umips-constraints-1.c: New test.
* gcc.target/mips/umips-lwp-3.c: New test.
* gcc.target/mips/umips-swp-6.c: New test.
* gcc.target/mips/umips-constraints-2.c: New test.
* gcc.target/mips/umips-save-restore-1.c: New test.
* gcc.target/mips/umips-lwp-4.c: New test.
* gcc.target/mips/umips-swp-7.c: New test.
* gcc.target/mips/umips-save-restore-2.c: New test.
* gcc.target/mips/umips-lwp-swp-volatile.c: New test.
* gcc.target/mips/umips-lwp-5.c: New test.
* gcc.target/mips/umips-save-restore-3.c: New test.
* gcc.target/mips/umips-lwp-6.c: New test.
* gcc.target/mips/umips-swp-1.c: New test.
* gcc.target/mips/umips-lwp-7.c: New test.
* gcc.target/mips/umips-swp-2.c: New test.
* gcc.target/mips/umips-lwp-8.c: New test.
* gcc.target/mips/umips-swp-3.c: New test.
* gcc.target/mips/umips-movep-1.c: New test.
* gcc.target/mips/umips-lwp-1.c: New test.
* gcc.target/mips/umips-swp-4.c: New test.
Co-Authored-By: Chao-ying Fu <fu@mips.com> Co-Authored-By: Iain Sandoe <iain@codesourcery.com> Co-Authored-By: Joseph Myers <joseph@codesourcery.com> Co-Authored-By: Maciej W. Rozycki <macro@codesourcery.com> Co-Authored-By: Nathan Froyd <froydnj@codesourcery.com> Co-Authored-By: Nathan Sidwell <nathan@codesourcery.com> Co-Authored-By: Richard Sandiford <rdsandiford@googlemail.com> Co-Authored-By: Tom de Vries <tom@codesourcery.com>
From-SVN: r196828