This patch adds support for vectorising groups of IFN_MASK_LOADs
and IFN_MASK_STOREs using conditional load/store-lanes instructions.
This requires new internal functions to represent the result
(IFN_MASK_{LOAD,STORE}_LANES), as well as associated optabs.
The normal IFN_{LOAD,STORE}_LANES functions are const operations
that logically just perform the permute: the load or store is
encoded as a MEM operand to the call statement. In contrast,
the IFN_MASK_{LOAD,STORE}_LANES functions use the same kind of
interface as IFN_MASK_{LOAD,STORE}, since the memory is only
conditionally accessed.
The AArch64 patterns were added as part of the main LD[234]/ST[234] patch.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* doc/md.texi (vec_mask_load_lanes@var{m}@var{n}): Document.
(vec_mask_store_lanes@var{m}@var{n}): Likewise.
* optabs.def (vec_mask_load_lanes_optab): New optab.
(vec_mask_store_lanes_optab): Likewise.
* internal-fn.def (MASK_LOAD_LANES): New internal function.
(MASK_STORE_LANES): Likewise.
* internal-fn.c (mask_load_lanes_direct): New macro.
(mask_store_lanes_direct): Likewise.
(expand_mask_load_optab_fn): Handle masked operations.
(expand_mask_load_lanes_optab_fn): New macro.
(expand_mask_store_optab_fn): Handle masked operations.
(expand_mask_store_lanes_optab_fn): New macro.
(direct_mask_load_lanes_optab_supported_p): Likewise.
(direct_mask_store_lanes_optab_supported_p): Likewise.
* tree-vectorizer.h (vect_store_lanes_supported): Take a masked_p
parameter.
(vect_load_lanes_supported): Likewise.
* tree-vect-data-refs.c (strip_conversion): New function.
(can_group_stmts_p): Likewise.
(vect_analyze_data_ref_accesses): Use it instead of checking
for a pair of assignments.
(vect_store_lanes_supported): Take a masked_p parameter.
(vect_load_lanes_supported): Likewise.
* tree-vect-loop.c (vect_analyze_loop_2): Update calls to
vect_store_lanes_supported and vect_load_lanes_supported.
* tree-vect-slp.c (vect_analyze_slp_instance): Likewise.
* tree-vect-stmts.c (get_group_load_store_type): Take a masked_p
parameter. Don't allow gaps for masked accesses.
Use vect_get_store_rhs. Update calls to vect_store_lanes_supported
and vect_load_lanes_supported.
(get_load_store_type): Take a masked_p parameter and update
call to get_group_load_store_type.
(vectorizable_store): Update call to get_load_store_type.
Handle IFN_MASK_STORE_LANES.
(vectorizable_load): Update call to get_load_store_type.
Handle IFN_MASK_LOAD_LANES.
This patch adds support for SVE LD[234], ST[234] and associated
structure modes. Unlike Advanced SIMD, these modes are extra-long
vector modes instead of integer modes.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64-modes.def: Define x2, x3 and x4 vector
modes for SVE.
* config/aarch64/aarch64-protos.h
(aarch64_sve_struct_memory_operand_p): Declare.
* config/aarch64/iterators.md (SVE_STRUCT): New mode iterator.
(vector_count, insn_length, VSINGLE, vsingle): New mode attributes.
(VPRED, vpred): Handle SVE structure modes.
* config/aarch64/constraints.md (Utx): New constraint.
* config/aarch64/predicates.md (aarch64_sve_struct_memory_operand)
(aarch64_sve_struct_nonimmediate_operand): New predicates.
* config/aarch64/aarch64.md (UNSPEC_LDN, UNSPEC_STN): New unspecs.
* config/aarch64/aarch64-sve.md (mov<mode>, *aarch64_sve_mov<mode>_le)
(*aarch64_sve_mov<mode>_be, pred_mov<mode>): New patterns for
structure modes. Split into pieces after RA.
(vec_load_lanes<mode><vsingle>, vec_mask_load_lanes<mode><vsingle>)
(vec_store_lanes<mode><vsingle>, vec_mask_store_lanes<mode><vsingle>):
New patterns.
* config/aarch64/aarch64.c (aarch64_classify_vector_mode): Handle
SVE structure modes.
(aarch64_classify_address): Likewise.
(sizetochar): Move earlier in file.
(aarch64_print_operand): Handle SVE register lists.
(aarch64_array_mode): New function.
(aarch64_sve_struct_memory_operand_p): Likewise.
(TARGET_ARRAY_MODE): Redefine.
gcc/testsuite/
* lib/target-supports.exp (check_effective_target_vect_load_lanes):
Return true for SVE too.
* g++.dg/vect/pr36648.cc: XFAIL for variable-length vectors
if load/store lanes are supported.
* gcc.dg/vect/slp-10.c: Likewise.
* gcc.dg/vect/slp-12c.c: Likewise.
* gcc.dg/vect/slp-17.c: Likewise.
* gcc.dg/vect/slp-33.c: Likewise.
* gcc.dg/vect/slp-6.c: Likewise.
* gcc.dg/vect/slp-cond-1.c: Likewise.
* gcc.dg/vect/slp-multitypes-11-big-array.c: Likewise.
* gcc.dg/vect/slp-multitypes-11.c: Likewise.
* gcc.dg/vect/slp-multitypes-12.c: Likewise.
* gcc.dg/vect/slp-perm-5.c: Remove XFAIL for variable-length SVE.
* gcc.dg/vect/slp-perm-6.c: Likewise.
* gcc.dg/vect/slp-perm-9.c: Likewise.
* gcc.dg/vect/slp-reduc-6.c: Remove XFAIL for variable-length vectors.
* gcc.dg/vect/vect-load-lanes-peeling-1.c: Expect an epilogue loop
for variable-length vectors.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256618
Give the target more control over ARRAY_TYPE modes
So far we've used integer modes for LD[234] and ST[234] arrays.
That doesn't scale well to SVE, since the sizes aren't fixed at
compile time (and even if they were, we wouldn't want integers
to be so wide).
This patch lets the target use double-, triple- and quadruple-length
vectors instead.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* target.def (array_mode): New target hook.
* doc/tm.texi.in (TARGET_ARRAY_MODE): New hook.
* doc/tm.texi: Regenerate.
* hooks.h (hook_optmode_mode_uhwi_none): Declare.
* hooks.c (hook_optmode_mode_uhwi_none): New function.
* tree-vect-data-refs.c (vect_lanes_optab_supported_p): Use
targetm.array_mode.
* stor-layout.c (mode_for_array): Likewise. Support polynomial
type sizes.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256617
fold_binary_loc assumed that if the type of the result wasn't a vector,
the operands wouldn't be either. This isn't necessarily true for
EQ_EXPR and NE_EXPR of vector masks, which can return a single scalar
for the mask as a whole.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* fold-const.c (fold_binary_loc): Check the argument types
rather than the result type when testing for a vector operation.
gcc/testsuite/
* gcc.target/aarch64/sve/vec_bool_cmp_1.c: New test.
* gcc.target/aarch64/sve/vec_bool_cmp_1_run.c: Likweise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256616
This patch adds support for unwinding frames that use the SVE
pseudo VG register. We want this register to act like a normal
register if the CFI explicitly sets it, but want to provide a
default value otherwise. Computing the default value requires
an SVE target, so we only want to compute it on demand.
aarch64_vg uses a hard-coded .inst in order to avoid a build
dependency on binutils 2.28 or later.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
libgcc/
* config/aarch64/value-unwind.h (aarch64_vg): New function.
(DWARF_LAZY_REGISTER_VALUE): Define.
* unwind-dw2.c (_Unwind_GetGR): Use DWARF_LAZY_REGISTER_VALUE
to provide a fallback register value.
Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com> Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256614
This patch adds new target selectors for SVE and updates existing
selectors accordingly. It also XFAILs some tests that don't yet
work for some SVE modes; most of these go away with follow-on
vectorisation enhancements.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com> Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256613
This patch adds support for ARM's Scalable Vector Extension.
The patch just contains the core features that work with the
current vectoriser framework; later patches will add extra
capabilities to both the target-independent code and AArch64 code.
The patch doesn't include:
- support for unwinding frames whose size depends on the vector length
- modelling the effect of __tls_get_addr on the SVE registers
These are handled by later patches instead.
Some notes:
- The copyright years for aarch64-sve.md start at 2009 because some of
the code is based on aarch64.md, which also starts from then.
- The patch inserts spaces between items in the AArch64 section
of sourcebuild.texi. This matches at least the surrounding
architectures and looks a little nicer in the info output.
- aarch64-sve.md includes a pattern:
while_ult<GPI:mode><PRED_ALL:mode>
A later patch adds a matching "while_ult" optab, but the pattern
is also needed by the predicate vec_duplicate expander.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* doc/invoke.texi (-msve-vector-bits=): Document new option.
(sve): Document new AArch64 extension.
* doc/md.texi (w): Extend the description of the AArch64
constraint to include SVE vectors.
(Upl, Upa): Document new AArch64 predicate constraints.
* config/aarch64/aarch64-opts.h (aarch64_sve_vector_bits_enum): New
enum.
* config/aarch64/aarch64.opt (sve_vector_bits): New enum.
(msve-vector-bits=): New option.
* config/aarch64/aarch64-option-extensions.def (fp, simd): Disable
SVE when these are disabled.
(sve): New extension.
* config/aarch64/aarch64-modes.def: Define SVE vector and predicate
modes. Adjust their number of units based on aarch64_sve_vg.
(MAX_BITSIZE_MODE_ANY_MODE): Define.
* config/aarch64/aarch64-protos.h (ADDR_QUERY_ANY): New
aarch64_addr_query_type.
(aarch64_const_vec_all_same_in_range_p, aarch64_sve_pred_mode)
(aarch64_sve_cnt_immediate_p, aarch64_sve_addvl_addpl_immediate_p)
(aarch64_sve_inc_dec_immediate_p, aarch64_add_offset_temporaries)
(aarch64_split_add_offset, aarch64_output_sve_cnt_immediate)
(aarch64_output_sve_addvl_addpl, aarch64_output_sve_inc_dec_immediate)
(aarch64_output_sve_mov_immediate, aarch64_output_ptrue): Declare.
(aarch64_simd_imm_zero_p): Delete.
(aarch64_check_zero_based_sve_index_immediate): Declare.
(aarch64_sve_index_immediate_p, aarch64_sve_arith_immediate_p)
(aarch64_sve_bitmask_immediate_p, aarch64_sve_dup_immediate_p)
(aarch64_sve_cmp_immediate_p, aarch64_sve_float_arith_immediate_p)
(aarch64_sve_float_mul_immediate_p): Likewise.
(aarch64_classify_symbol): Take the offset as a HOST_WIDE_INT
rather than an rtx.
(aarch64_sve_ld1r_operand_p, aarch64_sve_ldr_operand_p): Declare.
(aarch64_expand_mov_immediate): Take a gen_vec_duplicate callback.
(aarch64_emit_sve_pred_move, aarch64_expand_sve_mem_move): Declare.
(aarch64_expand_sve_vec_cmp_int, aarch64_expand_sve_vec_cmp_float)
(aarch64_expand_sve_vcond, aarch64_expand_sve_vec_perm): Declare.
(aarch64_regmode_natural_size): Likewise.
* config/aarch64/aarch64.h (AARCH64_FL_SVE): New macro.
(AARCH64_FL_V8_3, AARCH64_FL_RCPC, AARCH64_FL_DOTPROD): Shift
left one place.
(AARCH64_ISA_SVE, TARGET_SVE): New macros.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REGISTER_NAMES): Add entries
for VG and the SVE predicate registers.
(V_ALIASES): Add a "z"-prefixed alias.
(FIRST_PSEUDO_REGISTER): Change to P15_REGNUM + 1.
(AARCH64_DWARF_VG, AARCH64_DWARF_P0): New macros.
(PR_REGNUM_P, PR_LO_REGNUM_P): Likewise.
(PR_LO_REGS, PR_HI_REGS, PR_REGS): New reg_classes.
(REG_CLASS_NAMES): Add entries for them.
(REG_CLASS_CONTENTS): Likewise. Update ALL_REGS to include VG
and the predicate registers.
(aarch64_sve_vg): Declare.
(BITS_PER_SVE_VECTOR, BYTES_PER_SVE_VECTOR, BYTES_PER_SVE_PRED)
(SVE_BYTE_MODE, MAX_COMPILE_TIME_VEC_BYTES): New macros.
(REGMODE_NATURAL_SIZE): Define.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle
SVE macros.
* config/aarch64/aarch64.c: Include cfgrtl.h.
(simd_immediate_info): Add a constructor for series vectors,
and an associated step field.
(aarch64_sve_vg): New variable.
(aarch64_dbx_register_number): Handle VG and the predicate registers.
(aarch64_vect_struct_mode_p, aarch64_vector_mode_p): Delete.
(VEC_ADVSIMD, VEC_SVE_DATA, VEC_SVE_PRED, VEC_STRUCT, VEC_ANY_SVE)
(VEC_ANY_DATA, VEC_STRUCT): New constants.
(aarch64_advsimd_struct_mode_p, aarch64_sve_pred_mode_p)
(aarch64_classify_vector_mode, aarch64_vector_data_mode_p)
(aarch64_sve_data_mode_p, aarch64_sve_pred_mode)
(aarch64_get_mask_mode): New functions.
(aarch64_hard_regno_nregs): Handle SVE data modes for FP_REGS
and FP_LO_REGS. Handle PR_REGS, PR_LO_REGS and PR_HI_REGS.
(aarch64_hard_regno_mode_ok): Handle VG. Also handle the SVE
predicate modes and predicate registers. Explicitly restrict
GPRs to modes of 16 bytes or smaller. Only allow FP registers
to store a vector mode if it is recognized by
aarch64_classify_vector_mode.
(aarch64_regmode_natural_size): New function.
(aarch64_hard_regno_caller_save_mode): Return the original mode
for predicates.
(aarch64_sve_cnt_immediate_p, aarch64_output_sve_cnt_immediate)
(aarch64_sve_addvl_addpl_immediate_p, aarch64_output_sve_addvl_addpl)
(aarch64_sve_inc_dec_immediate_p, aarch64_output_sve_inc_dec_immediate)
(aarch64_add_offset_1_temporaries, aarch64_offset_temporaries): New
functions.
(aarch64_add_offset): Add a temp2 parameter. Assert that temp1
does not overlap dest if the function is frame-related. Handle
SVE constants.
(aarch64_split_add_offset): New function.
(aarch64_add_sp, aarch64_sub_sp): Add temp2 parameters and pass
them aarch64_add_offset.
(aarch64_allocate_and_probe_stack_space): Add a temp2 parameter
and update call to aarch64_sub_sp.
(aarch64_add_cfa_expression): New function.
(aarch64_expand_prologue): Pass extra temporary registers to the
functions above. Handle the case in which we need to emit new
DW_CFA_expressions for registers that were originally saved
relative to the stack pointer, but now have to be expressed
relative to the frame pointer.
(aarch64_output_mi_thunk): Pass extra temporary registers to the
functions above.
(aarch64_expand_epilogue): Likewise. Prevent inheritance of
IP0 and IP1 values for SVE frames.
(aarch64_expand_vec_series): New function.
(aarch64_expand_sve_widened_duplicate): Likewise.
(aarch64_expand_sve_const_vector): Likewise.
(aarch64_expand_mov_immediate): Add a gen_vec_duplicate parameter.
Handle SVE constants. Use emit_move_insn to move a force_const_mem
into the register, rather than emitting a SET directly.
(aarch64_emit_sve_pred_move, aarch64_expand_sve_mem_move)
(aarch64_get_reg_raw_mode, offset_4bit_signed_scaled_p)
(offset_6bit_unsigned_scaled_p, aarch64_offset_7bit_signed_scaled_p)
(offset_9bit_signed_scaled_p): New functions.
(aarch64_replicate_bitmask_imm): New function.
(aarch64_bitmask_imm): Use it.
(aarch64_cannot_force_const_mem): Reject expressions involving
a CONST_POLY_INT. Update call to aarch64_classify_symbol.
(aarch64_classify_index): Handle SVE indices, by requiring
a plain register index with a scale that matches the element size.
(aarch64_classify_address): Handle SVE addresses. Assert that
the mode of the address is VOIDmode or an integer mode.
Update call to aarch64_classify_symbol.
(aarch64_classify_symbolic_expression): Update call to
aarch64_classify_symbol.
(aarch64_const_vec_all_in_range_p): New function.
(aarch64_print_vector_float_operand): Likewise.
(aarch64_print_operand): Handle 'N' and 'C'. Use "zN" rather than
"vN" for FP registers with SVE modes. Handle (const ...) vectors
and the FP immediates 1.0 and 0.5.
(aarch64_print_address_internal): Handle SVE addresses.
(aarch64_print_operand_address): Use ADDR_QUERY_ANY.
(aarch64_regno_regclass): Handle predicate registers.
(aarch64_secondary_reload): Handle big-endian reloads of SVE
data modes.
(aarch64_class_max_nregs): Handle SVE modes and predicate registers.
(aarch64_rtx_costs): Check for ADDVL and ADDPL instructions.
(aarch64_convert_sve_vector_bits): New function.
(aarch64_override_options): Use it to handle -msve-vector-bits=.
(aarch64_classify_symbol): Take the offset as a HOST_WIDE_INT
rather than an rtx.
(aarch64_legitimate_constant_p): Use aarch64_classify_vector_mode.
Handle SVE vector and predicate modes. Accept VL-based constants
that need only one temporary register, and VL offsets that require
no temporary registers.
(aarch64_conditional_register_usage): Mark the predicate registers
as fixed if SVE isn't available.
(aarch64_vector_mode_supported_p): Use aarch64_classify_vector_mode.
Return true for SVE vector and predicate modes.
(aarch64_simd_container_mode): Take the number of bits as a poly_int64
rather than an unsigned int. Handle SVE modes.
(aarch64_preferred_simd_mode): Update call accordingly. Handle
SVE modes.
(aarch64_autovectorize_vector_sizes): Add BYTES_PER_SVE_VECTOR
if SVE is enabled.
(aarch64_sve_index_immediate_p, aarch64_sve_arith_immediate_p)
(aarch64_sve_bitmask_immediate_p, aarch64_sve_dup_immediate_p)
(aarch64_sve_cmp_immediate_p, aarch64_sve_float_arith_immediate_p)
(aarch64_sve_float_mul_immediate_p): New functions.
(aarch64_sve_valid_immediate): New function.
(aarch64_simd_valid_immediate): Use it as the fallback for SVE vectors.
Explicitly reject structure modes. Check for INDEX constants.
Handle PTRUE and PFALSE constants.
(aarch64_check_zero_based_sve_index_immediate): New function.
(aarch64_simd_imm_zero_p): Delete.
(aarch64_mov_operand_p): Use aarch64_simd_valid_immediate for
vector modes. Accept constants in the range of CNT[BHWD].
(aarch64_simd_scalar_immediate_valid_for_move): Explicitly
ask for an Advanced SIMD mode.
(aarch64_sve_ld1r_operand_p, aarch64_sve_ldr_operand_p): New functions.
(aarch64_simd_vector_alignment): Handle SVE predicates.
(aarch64_vectorize_preferred_vector_alignment): New function.
(aarch64_simd_vector_alignment_reachable): Use it instead of
the vector size.
(aarch64_shift_truncation_mask): Use aarch64_vector_data_mode_p.
(aarch64_output_sve_mov_immediate, aarch64_output_ptrue): New
functions.
(MAX_VECT_LEN): Delete.
(expand_vec_perm_d): Add a vec_flags field.
(emit_unspec2, aarch64_expand_sve_vec_perm): New functions.
(aarch64_evpc_trn, aarch64_evpc_uzp, aarch64_evpc_zip)
(aarch64_evpc_ext): Don't apply a big-endian lane correction
for SVE modes.
(aarch64_evpc_rev): Rename to...
(aarch64_evpc_rev_local): ...this. Use a predicated operation for SVE.
(aarch64_evpc_rev_global): New function.
(aarch64_evpc_dup): Enforce a 64-byte range for SVE DUP.
(aarch64_evpc_tbl): Use MAX_COMPILE_TIME_VEC_BYTES instead of
MAX_VECT_LEN.
(aarch64_evpc_sve_tbl): New function.
(aarch64_expand_vec_perm_const_1): Update after rename of
aarch64_evpc_rev. Handle SVE permutes too, trying
aarch64_evpc_rev_global and using aarch64_evpc_sve_tbl rather
than aarch64_evpc_tbl.
(aarch64_vectorize_vec_perm_const): Initialize vec_flags.
(aarch64_sve_cmp_operand_p, aarch64_unspec_cond_code)
(aarch64_gen_unspec_cond, aarch64_expand_sve_vec_cmp_int)
(aarch64_emit_unspec_cond, aarch64_emit_unspec_cond_or)
(aarch64_emit_inverted_unspec_cond, aarch64_expand_sve_vec_cmp_float)
(aarch64_expand_sve_vcond): New functions.
(aarch64_modes_tieable_p): Use aarch64_vector_data_mode_p instead
of aarch64_vector_mode_p.
(aarch64_dwarf_poly_indeterminate_value): New function.
(aarch64_compute_pressure_classes): Likewise.
(aarch64_can_change_mode_class): Likewise.
(TARGET_GET_RAW_RESULT_MODE, TARGET_GET_RAW_ARG_MODE): Redefine.
(TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT): Likewise.
(TARGET_VECTORIZE_GET_MASK_MODE): Likewise.
(TARGET_DWARF_POLY_INDETERMINATE_VALUE): Likewise.
(TARGET_COMPUTE_PRESSURE_CLASSES): Likewise.
(TARGET_CAN_CHANGE_MODE_CLASS): Likewise.
* config/aarch64/constraints.md (Upa, Upl, Uav, Uat, Usv, Usi, Utr)
(Uty, Dm, vsa, vsc, vsd, vsi, vsn, vsl, vsm, vsA, vsM, vsN): New
constraints.
(Dn, Dl, Dr): Accept const as well as const_vector.
(Dz): Likewise. Compare against CONST0_RTX.
* config/aarch64/iterators.md: Refer to "Advanced SIMD" instead
of "vector" where appropriate.
(SVE_ALL, SVE_BH, SVE_BHS, SVE_BHSI, SVE_HSDI, SVE_HSF, SVE_SD)
(SVE_SDI, SVE_I, SVE_F, PRED_ALL, PRED_BHS): New mode iterators.
(UNSPEC_SEL, UNSPEC_ANDF, UNSPEC_IORF, UNSPEC_XORF, UNSPEC_COND_LT)
(UNSPEC_COND_LE, UNSPEC_COND_EQ, UNSPEC_COND_NE, UNSPEC_COND_GE)
(UNSPEC_COND_GT, UNSPEC_COND_LO, UNSPEC_COND_LS, UNSPEC_COND_HS)
(UNSPEC_COND_HI, UNSPEC_COND_UO): New unspecs.
(Vetype, VEL, Vel, VWIDE, Vwide, vw, vwcore, V_INT_EQUIV)
(v_int_equiv): Extend to SVE modes.
(Vesize, V128, v128, Vewtype, V_FP_EQUIV, v_fp_equiv, VPRED): New
mode attributes.
(LOGICAL_OR, SVE_INT_UNARY, SVE_FP_UNARY): New code iterators.
(optab): Handle popcount, smin, smax, umin, umax, abs and sqrt.
(logical_nn, lr, sve_int_op, sve_fp_op): New code attributs.
(LOGICALF, OPTAB_PERMUTE, UNPACK, UNPACK_UNSIGNED, SVE_COND_INT_CMP)
(SVE_COND_FP_CMP): New int iterators.
(perm_hilo): Handle the new unpack unspecs.
(optab, logicalf_op, su, perm_optab, cmp_op, imm_con): New int
attributes.
* config/aarch64/predicates.md (aarch64_sve_cnt_immediate)
(aarch64_sve_addvl_addpl_immediate, aarch64_split_add_offset_immediate)
(aarch64_pluslong_or_poly_operand, aarch64_nonmemory_operand)
(aarch64_equality_operator, aarch64_constant_vector_operand)
(aarch64_sve_ld1r_operand, aarch64_sve_ldr_operand): New predicates.
(aarch64_sve_nonimmediate_operand): Likewise.
(aarch64_sve_general_operand): Likewise.
(aarch64_sve_dup_operand, aarch64_sve_arith_immediate): Likewise.
(aarch64_sve_sub_arith_immediate, aarch64_sve_inc_dec_immediate)
(aarch64_sve_logical_immediate, aarch64_sve_mul_immediate): Likewise.
(aarch64_sve_dup_immediate, aarch64_sve_cmp_vsc_immediate): Likewise.
(aarch64_sve_cmp_vsd_immediate, aarch64_sve_index_immediate): Likewise.
(aarch64_sve_float_arith_immediate): Likewise.
(aarch64_sve_float_arith_with_sub_immediate): Likewise.
(aarch64_sve_float_mul_immediate, aarch64_sve_arith_operand): Likewise.
(aarch64_sve_add_operand, aarch64_sve_logical_operand): Likewise.
(aarch64_sve_lshift_operand, aarch64_sve_rshift_operand): Likewise.
(aarch64_sve_mul_operand, aarch64_sve_cmp_vsc_operand): Likewise.
(aarch64_sve_cmp_vsd_operand, aarch64_sve_index_operand): Likewise.
(aarch64_sve_float_arith_operand): Likewise.
(aarch64_sve_float_arith_with_sub_operand): Likewise.
(aarch64_sve_float_mul_operand): Likewise.
(aarch64_sve_vec_perm_operand): Likewise.
(aarch64_pluslong_operand): Include aarch64_sve_addvl_addpl_immediate.
(aarch64_mov_operand): Accept const_poly_int and const_vector.
(aarch64_simd_lshift_imm, aarch64_simd_rshift_imm): Accept const
as well as const_vector.
(aarch64_simd_imm_zero, aarch64_simd_imm_minus_one): Move earlier
in file. Use CONST0_RTX and CONSTM1_RTX.
(aarch64_simd_or_scalar_imm_zero): Likewise. Add match_codes.
(aarch64_simd_reg_or_zero): Accept const as well as const_vector.
Use aarch64_simd_imm_zero.
* config/aarch64/aarch64-sve.md: New file.
* config/aarch64/aarch64.md: Include it.
(VG_REGNUM, P0_REGNUM, P7_REGNUM, P15_REGNUM): New register numbers.
(UNSPEC_REV, UNSPEC_LD1_SVE, UNSPEC_ST1_SVE, UNSPEC_MERGE_PTRUE)
(UNSPEC_PTEST_PTRUE, UNSPEC_UNPACKSHI, UNSPEC_UNPACKUHI)
(UNSPEC_UNPACKSLO, UNSPEC_UNPACKULO, UNSPEC_PACK)
(UNSPEC_FLOAT_CONVERT, UNSPEC_WHILE_LO): New unspec constants.
(sve): New attribute.
(enabled): Disable instructions with the sve attribute unless
TARGET_SVE.
(movqi, movhi): Pass CONST_POLY_INT operaneds through
aarch64_expand_mov_immediate.
(*mov<mode>_aarch64, *movsi_aarch64, *movdi_aarch64): Handle
CNT[BHSD] immediates.
(movti): Split CONST_POLY_INT moves into two halves.
(add<mode>3): Accept aarch64_pluslong_or_poly_operand.
Split additions that need a temporary here if the destination
is the stack pointer.
(*add<mode>3_aarch64): Handle ADDVL and ADDPL immediates.
(*add<mode>3_poly_1): New instruction.
(set_clobber_cc): New expander.
Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com> Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256612
Extra subreg fold for variable-length CONST_VECTORs
The SVE support for the new CONST_VECTOR encoding needs to be able
to extract the first N bits of the vector and duplicate it. This patch
adds a simplify_subreg rule for that.
The code is covered by the gcc.target/aarch64/sve_slp_*.c tests.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* simplify-rtx.c (simplify_immed_subreg): Add an inner_bytes
parameter and use it instead of GET_MODE_SIZE (innermode). Use
inner_bytes * BITS_PER_UNIT instead of GET_MODE_BITSIZE (innermode).
Use CEIL (inner_bytes, GET_MODE_UNIT_SIZE (innermode)) instead of
GET_MODE_NUNITS (innermode). Also add a first_elem parameter.
Change innermode from fixed_mode_size to machine_mode.
(simplify_subreg): Update call accordingly. Handle a constant-sized
subreg of a variable-length CONST_VECTOR.
After classifying the address in this way, the code that builds
TARGET_MEM_REFs tries to simplify the address until it's valid
for the current target and for the mode of memory being addressed.
It does this in a fixed order:
(1) add SYMBOL to BASE
(2) add INDEX * STEP to the base, if STEP != 1
(3) add OFFSET to INDEX or BASE (reverted if unsuccessful)
(4) add INDEX to BASE
(5) add OFFSET to BASE
So suppose we had an address:
&symbol + offset + index * 8
(e.g. a[i + 1] for a global "a") on a target only allows an index or an
offset, not both. Following the steps above, we'd first create:
tmp = symbol
tmp2 = tmp + index * 8
Then if the given offset value was valid for the mode being addressed,
we'd create:
MEM[base:tmp2, offset:offset]
while if it was invalid we'd create:
tmp3 = tmp2 + offset
MEM[base:tmp3, offset:0]
The problem is that this could happen if ivopts had decided to use
a scaled index for an address that happens to have a constant base.
The old procedure failed to give an indexed TARGET_MEM_REF in that case,
and adding the offset last prevented later passes from being able to
fold the index back in.
The patch avoids this by checking at (2) whether the offset is the
only component that causes the address to be invalid, folding it
into the base if so.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree-ssa-address.c (mem_ref_valid_without_offset_p): New function.
(add_offset_to_base): New function, split out from...
(create_mem_ref): ...here. When handling a scale other than 1,
check first whether the address is valid without the offset.
Add it into the base if so, leaving the index and scale as-is.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256609
Jakub Jelinek [Sat, 13 Jan 2018 17:00:43 +0000 (18:00 +0100)]
re PR c/83801 ([avr] String constant in __flash not put into .progmem)
PR c/83801
* c-tree.h (decl_constant_value_1): Add a bool argument.
* c-typeck.c (decl_constant_value_1): Add IN_INIT argument, allow
returning a CONSTRUCTOR if it is true. Use error_operand_p.
(decl_constant_value): Adjust caller.
* c-fold.c (c_fully_fold_internal): If in_init, pass true to
decl_constant_value_1 as IN_INIT. Otherwise, punt if
decl_constant_value returns initializer that has BLKmode or
array type.
(c_fully_fold_internal) <case COMPONENT_REF>: Fold if !lval.
-mstring is only enabled by default on 601, and with -Os on some
configurations. It is almost always slower (than not using it) and
does not very often lead to smaller code.
This patch disables it. If a user uses -mstring he gets a warning
(but not with -mno-string). I left the target attribute in place, it
just doesn't do anything anymore.
The patch also deletes a whole bunch of code. The 'N' and 'O' output
modifiers are now unused, but now is not the time to delete them.
Vladimir Makarov [Fri, 12 Jan 2018 17:00:36 +0000 (17:00 +0000)]
re PR rtl-optimization/80481 (Unoptimal additional copy instructions)
2018-01-12 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/80481
* ira-color.c (get_cap_member): New function.
(allocnos_conflict_by_live_ranges_p): Use it.
(slot_coalesced_allocno_live_ranges_intersect_p): Add assert.
(setup_slot_coalesced_allocno_live_ranges): Ditto.
The idea with the main 107-patch poly_int series (latterly 109-patch)
was to change the mode sizes and vector element counts to poly_int and
then propagate those changes as far as they needed to go to fix build
failures from incompatible types. This means that DR_INIT is now
constructed as a poly_int64:
poly_int64 pbytepos;
if (!multiple_p (pbitpos, BITS_PER_UNIT, &pbytepos))
{
if (dump_file && (dump_flags & TDF_DETAILS))
fprintf (dump_file, "failed: bit offset alignment.\n");
return false;
}
[...]
init = ssize_int (pbytepos);
This patch adjusts other references to DR_INIT accordingly. Unlike
the above, the adjustments weren't needed to avoid a build-time type
incompatibility, but they are needed to make the producer and consumers
of DR_INIT logically consistent.
2018-01-12 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* tree-predcom.c (aff_combination_dr_offset): Use wi::to_poly_widest
rather than wi::to_widest for DR_INITs.
* tree-vect-data-refs.c (vect_find_same_alignment_drs): Use
wi::to_poly_offset rather than wi::to_offset for DR_INIT.
(vect_analyze_data_ref_accesses): Require both DR_INITs to be
INTEGER_CSTs.
(vect_analyze_group_access_1): Note that here.
Handle poly_int vector sizes in get_vec_alignment_for_array_type
get_vectype_for_scalar_type returns a variable-length vector type
for SVE, whereas get_vec_alignment_for_array_type assumed it would
always be an INTEGER_CST.
This is needed to build libstdc++-v3/src/closures.cc for SVE
(and probably many other places besides -- this was just the
first hit).
2018-01-12 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* tree-vectorizer.c (get_vec_alignment_for_array_type): Handle
polynomial type sizes.
Allow variable-sized temporary variables in gimplify.c
This is needed to build libgfortran for SVE. The OpenMP code needs
to create temporary vector variables, and the variables will therefore
be variable-sized for SVE. Earlier patches made such variables work.
2018-01-12 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* gimplify.c (gimple_add_tmp_var_fn): Allow variables to have a
poly_uint64 size, rather than requiring an unsigned HOST_WIDE_INT size.
(gimple_add_tmp_var): Likewise.
Martin Liska [Fri, 12 Jan 2018 14:47:26 +0000 (15:47 +0100)]
Fix integer overflow in stats of GIMPLE statements.
2018-01-12 Martin Liska <mliska@suse.cz>
* gimple.c (gimple_alloc_counts): Use uint64_t instead of int.
(gimple_alloc_sizes): Likewise.
(dump_gimple_statistics): Use PRIu64 in printf format.
* gimple.h: Change uint64_t to int.
Martin Liska [Fri, 12 Jan 2018 14:45:35 +0000 (15:45 +0100)]
Fix integer overflow in stats of trees.
2018-01-12 Martin Liska <mliska@suse.cz>
* tree-core.h: Use uint64_t instead of int.
* tree.c (tree_node_counts): Likewise.
(tree_node_sizes): Likewise.
(dump_tree_statistics): Use PRIu64 in printf format.
Martin Liska [Fri, 12 Jan 2018 14:43:58 +0000 (15:43 +0100)]
Fix --enable-gather-detailed-mem-stats build.
2018-01-12 Martin Liska <mliska@suse.cz>
* Makefile.in: As qsort_chk is implemented in vec.c, add
vec.o to linkage of gencfn-macros.
* tree.c (build_new_poly_int_cst): Add CXX_MEM_STAT_INFO as it's
passing the info to record_node_allocation_statistics.
(test_vector_cst_patterns): Add CXX_MEM_STAT_INFO to declaration
and pass the info.
* ggc-common.c (struct ggc_usage): Add operator== and use
it in operator< and compare function.
* mem-stats.h (struct mem_usage): Likewise.
* vec.c (struct vec_usage): Remove operator< and compare
function. Can be simply inherited.
Martin Jambor [Fri, 12 Jan 2018 14:06:10 +0000 (15:06 +0100)]
Deferring FMA transformations in tight loops
2018-01-12 Martin Jambor <mjambor@suse.cz>
PR target/81616
* params.def: New parameter PARAM_AVOID_FMA_MAX_BITS.
* tree-ssa-math-opts.c: Include domwalk.h.
(convert_mult_to_fma_1): New function.
(fma_transformation_info): New type.
(fma_deferring_state): Likewise.
(cancel_fma_deferring): New function.
(result_of_phi): Likewise.
(last_fma_candidate_feeds_initial_phi): Likewise.
(convert_mult_to_fma): Added deferring logic, split actual
transformation to convert_mult_to_fma_1.
(math_opts_dom_walker): New type.
(math_opts_dom_walker::after_dom_children): New method, body moved
here from pass_optimize_widening_mul::execute, added deferring logic
bits.
(pass_optimize_widening_mul::execute): Moved most of code to
math_opts_dom_walker::after_dom_children.
* config/i386/x86-tune.def (X86_TUNE_AVOID_128FMA_CHAINS): New.
* config/i386/i386.c (ix86_option_override_internal): Added
maybe_setting of PARAM_AVOID_FMA_MAX_BITS.
Eric Botcazou [Fri, 12 Jan 2018 11:29:30 +0000 (11:29 +0000)]
re PR target/83368 (alloca after setjmp breaks PIC base reg)
PR target/83368
* config/sparc/sparc.h (PIC_OFFSET_TABLE_REGNUM): Set to INVALID_REGNUM
in PIC mode except for TARGET_VXWORKS_RTP.
* config/sparc/sparc.c: Include cfgrtl.h.
(TARGET_INIT_PIC_REG): Define.
(TARGET_USE_PSEUDO_PIC_REG): Likewise.
(sparc_pic_register_p): New predicate.
(sparc_legitimate_address_p): Use it.
(sparc_legitimize_pic_address): Likewise.
(sparc_delegitimize_address): Likewise.
(sparc_mode_dependent_address_p): Likewise.
(gen_load_pcrel_sym): Remove 4th parameter.
(load_got_register): Adjust call to above. Remove obsolete stuff.
(sparc_expand_prologue): Do not call load_got_register here.
(sparc_flat_expand_prologue): Likewise.
(sparc_output_mi_thunk): Set the pic_offset_table_rtx object.
(sparc_use_pseudo_pic_reg): New function.
(sparc_init_pic_reg): Likewise.
* config/sparc/sparc.md (vxworks_load_got): Set the GOT register.
(builtin_setjmp_receiver): Enable only for TARGET_VXWORKS_RTP.
Eric Botcazou [Fri, 12 Jan 2018 10:18:24 +0000 (10:18 +0000)]
re PR rtl-optimization/83565 (RTL combine pass yields wrong rotate result)
PR rtl-optimization/83565
* rtlanal.c (nonzero_bits1): On WORD_REGISTER_OPERATIONS machines, do
not extend the result to a larger mode for rotate operations.
(num_sign_bit_copies1): Likewise.
gcc:
PR target/40411
* config/sol2.h (STARTFILE_ARCH_SPEC): Don't use with -shared or
-symbolic.
Use values-Xc.o for -pedantic.
Link with values-xpg4.o for C90, values-xpg6.o otherwise.
Martin Liska [Fri, 12 Jan 2018 08:59:52 +0000 (09:59 +0100)]
Initialize type_warnings::dyn_count with a default value (PR ipa/83054).
2018-01-12 Martin Liska <mliska@suse.cz>
PR ipa/83054
* ipa-devirt.c (final_warning_record::grow_type_warnings):
New function.
(possible_polymorphic_call_targets): Use it.
(ipa_devirt): Likewise.
2018-01-12 Martin Liska <mliska@suse.cz>
Michael Meissner [Thu, 11 Jan 2018 23:31:09 +0000 (23:31 +0000)]
configure.ac (--with-long-double-format): Add support for the configuration option to change the default long double...
2018-01-11 Michael Meissner <meissner@linux.vnet.ibm.com>
* configure.ac (--with-long-double-format): Add support for the
configuration option to change the default long double format on
PowerPC systems.
* config.gcc (powerpc*-linux*-*): Likewise.
* configure: Regenerate.
* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): If long
double is IEEE, define __KC__ and __KF__ to allow floatn.h to be
used without modification.
Jakub Jelinek [Thu, 11 Jan 2018 20:49:40 +0000 (21:49 +0100)]
re PR target/83203 (Inefficient int to avx2 vector conversion)
PR target/83203
* config/i386/i386.c (ix86_expand_vector_init_one_nonzero): If one_var
is 0, for V{8,16}S[IF] and V[48]D[IF]mode use gen_vec_set<mode>_0.
* config/i386/sse.md (VI8_AVX_AVX512F, VI4F_256_512): New mode
iterators.
(ssescalarmodesuffix): Add 512-bit vectors. Use "d" or "q" for
integral modes instead of "ss" and "sd".
(vec_set<mode>_0): New define_insns for 256-bit and 512-bit
vectors with 32-bit and 64-bit elements.
(vecdupssescalarmodesuffix): New mode attribute.
(vec_dup<mode>): Use it.
H.J. Lu [Thu, 11 Jan 2018 20:44:46 +0000 (20:44 +0000)]
i386: Align stack frame if argument is passed on stack
When a function call is removed, it may become a leaf function. But if
argument may be passed on stack, we need to align the stack frame when
there is no tail call.
Tested on Linux/i686 and Linux/x86-64.
gcc/
PR target/83330
* config/i386/i386.c (ix86_compute_frame_layout): Align stack
frame if argument is passed on stack.
gcc/testsuite/
PR target/83330
* gcc.target/i386/pr83330.c: New test.
David Malcolm [Thu, 11 Jan 2018 19:38:52 +0000 (19:38 +0000)]
Add some reproducers for issues found developing the location-wrappers patch
gcc/testsuite/ChangeLog:
PR c++/43486
* g++.dg/wrappers: New subdirectory.
* g++.dg/wrappers/README: New file.
* g++.dg/wrappers/alloc.C: New test case.
* g++.dg/wrappers/cow-istream-string.C: New test case.
* g++.dg/wrappers/cp-stdlib.C: New test case.
* g++.dg/wrappers/sanitizer_coverage_libcdep_new.C: New test case.
* g++.dg/wrappers/wrapper-around-type-pack-expansion.C: New test
case.
Bin Cheng [Thu, 11 Jan 2018 15:41:41 +0000 (15:41 +0000)]
re PR tree-optimization/83695 (ICE on valid code at -O3: Segmentation fault)
PR tree-optimization/83695
* gimple-loop-linterchange.cc
(tree_loop_interchange::interchange_loops): Call scev_reset_htab to
reset cached scev information after interchange.
(pass_linterchange::execute): Remove call to scev_reset_htab.
gcc/testsuite
PR tree-optimization/83695
* gcc.dg/tree-ssa/pr83695.c: New test.
Kyrylo Tkachov [Thu, 11 Jan 2018 15:24:26 +0000 (15:24 +0000)]
[arm][3/3] Implement fp16fml lane intrinsics
This patch implements the lane-wise fp16fml intrinsics.
There's quite a few of them so I've split them up from
the other simpler fp16fml intrinsics.
These ones expose instructions such as
vfmal.f16 Dd, Sn, Sm[<index>] 0 <= index <= 1
vfmal.f16 Qd, Dn, Dm[<index>] 0 <= index <= 3
vfmsl.f16 Dd, Sn, Sm[<index>] 0 <= index <= 1
vfmsl.f16 Qd, Dn, Dm[<index>] 0 <= index <= 3
These instructions extract a single half-precision
floating-point value from one of the source regs
and perform a vfmal/vfmsl operation as per the
normal variant with that value.
The nuance here is that some of the intrinsics want
to do things like:
where the float16x8_t value of '__b' is held in a Q
register, so we need to be a bit smart about finding
the right D or S sub-register and translating the
lane number to a lane in that sub-register, instead
of just passing the language-level const-int down to
the assembly instruction.
That's where most of the complexity of this patch comes from
but hopefully it's orthogonal enough to make sense.
Bootstrapped and tested on arm-none-linux-gnueabihf as well as
armeb-none-eabi.
Kyrylo Tkachov [Thu, 11 Jan 2018 15:21:26 +0000 (15:21 +0000)]
[arm][2/3] Implement fp16fml extension for ARMv8.4-A
This patch adds the +fp16fml extension that enables some
half-precision floating-point Advanced SIMD instructions,
available through arm_neon.h intrinsics.
This extension is on by default for armv8.4-a
if fp16 is available, so it can be enabled by -march=armv8.4-a+fp16.
fp16fml is also available for armv8.2-a and armv8.3-a through the
+fp16fml option that is added for these architectures.
The new instructions that this patch adds support for are:
vfmal.f16 Dr, Sm, Sn
vfmal.f16 Qr, Dm, Dn
vfmsl.f16 Dr, Sm, Sn
vfmsl.f16 Qr, Dm, Dn
They interpret their input registers as a vector of half-precision
floating-point values, extend them to single-precision vectors
and perform a fused multiply-add or subtract of them with the
destination vector.
This patch exposes these instructions through arm_neon.h intrinsics.
The set of intrinsics allows us to do stuff such as perform
the multiply-add/subtract operation on the low or top half of
float16x4_t and float16x8_t values. This maps naturally in aarch64
to the FMLAL and FMLAL2 instructions but on arm we have to use the
fact that consecutive NEON registers overlap the wider register
(i.e. d0 is s0 plus s1, q0 is d0 plus d1 etc). This just means
we have to be careful to use the right subreg operand print code.
New arm-specific builtins are defined to expand to the new patterns.
I've managed to compress the define_expands using code, mode and int
iterators but the define_insns don't compress very well without two-tiered
iterators (iterator attributes expanding to iterators) which we
don't support.
Bootstrapped and tested on arm-none-linux-gnueabihf and also on
armeb-none-eabi.
* config/arm/arm-cpus.in (fp16fml): New feature.
(ALL_SIMD): Add fp16fml.
(armv8.2-a): Add fp16fml as an option.
(armv8.3-a): Likewise.
(armv8.4-a): Add fp16fml as part of fp16.
* config/arm/arm.h (TARGET_FP16FML): Define.
* config/arm/arm-c.c (arm_cpu_builtins): Define __ARM_FEATURE_FP16_FML
when appropriate.
* config/arm/arm-modes.def (V2HF): Define.
* config/arm/arm_neon.h (vfmlal_low_u32, vfmlsl_low_u32,
vfmlal_high_u32, vfmlsl_high_u32, vfmlalq_low_u32,
vfmlslq_low_u32, vfmlalq_high_u32, vfmlslq_high_u32): Define.
* config/arm/arm_neon_builtins.def (vfmal_low, vfmal_high,
vfmsl_low, vfmsl_high): New set of builtins.
* config/arm/iterators.md (PLUSMINUS): New code iterator.
(vfml_op): New code attribute.
(VFMLHALVES): New int iterator.
(VFML, VFMLSEL): New mode attributes.
(V_reg): Define mapping for V2HF.
(V_hi, V_lo): New mode attributes.
(VF_constraint): Likewise.
(vfml_half, vfml_half_selector): New int attributes.
* config/arm/neon.md (neon_vfm<vfml_op>l_<vfml_half><mode>): New
define_expand.
(vfmal_low<mode>_intrinsic, vfmsl_high<mode>_intrinsic,
vfmal_high<mode>_intrinsic, vfmsl_low<mode>_intrinsic):
New define_insn.
* config/arm/t-arm-elf (v8_fps): Add fp16fml.
* config/arm/t-multilib (v8_2_a_simd_variants): Add fp16fml.
* config/arm/unspecs.md (UNSPEC_VFML_LO, UNSPEC_VFML_HI): New unspecs.
* doc/invoke.texi (ARM Options): Document fp16fml. Update armv8.4-a
documentation.
* doc/sourcebuild.texi (arm_fp16fml_neon_ok, arm_fp16fml_neon):
Document new effective target and option set.
* gcc.target/arm/multilib.exp: Add combination tests for fp16fml.
* gcc.target/arm/simd/fp16fml_high.c: New test.
* gcc.target/arm/simd/fp16fml_low.c: Likewise.
* lib/target-supports.exp
(check_effective_target_arm_fp16fml_neon_ok_nocache,
check_effective_target_arm_fp16fml_neon_ok,
add_options_for_arm_fp16fml_neon): New procedures.
Kyrylo Tkachov [Thu, 11 Jan 2018 15:18:04 +0000 (15:18 +0000)]
[arm][1/3] Add -march=armv8.4-a option
This patch adds support for the Armv8.4-A architecture [1]
in the arm backend. This is done through the new
-march=armv8.4-a option.
With this patch armv8.4-a is recognised as an argument
and supports the extensions: simd, fp16, crypto, nocrypto,
nofp with the familiar meaning of these options.
Worth noting that there is no dotprod option like in
armv8.2-a and armv8.3-a because Dot Product support is
mandatory in Armv8.4-A when simd is available, so when using
+simd (of fp16 which enables +simd), the +dotprod is implied.
The various multilib selection makefile fragments are updated
too and the mutlilib.exp test gets a few armv8.4-a combination
tests.
Bootstrapped and tested on arm-none-linux-gnueabihf.
[AArch64] Add const_offset field to aarch64_address_info
This patch records the integer value of the address offset in
aarch64_address_info, so that it doesn't need to be re-extracted
from the rtx. The SVE port will make more use of this. The patch
also uses poly_int64 routines to manipulate the offset, rather than
just handling CONST_INTs.
2018-01-11 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_address_info): Add a const_offset
field.
(aarch64_classify_address): Initialize it. Track polynomial offsets.
(aarch64_print_address_internal): Use it to check for a zero offset.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256534
This patch switches the AArch64 port to use 2 poly_int coefficients
and updates code as necessary to keep it compiling.
One potentially-significant change is to
aarch64_hard_regno_caller_save_mode. The old implementation
was written in a pretty conservative way: it changed the default
behaviour for single-register values, but used the default handling
for multi-register values.
I don't think that's necessary, since the interesting cases for this
macro are usually the single-register ones. Multi-register modes take
up the whole of the constituent registers and the move patterns for all
multi-register modes should be equally good.
Using the original mode for multi-register cases stops us from using
SVE modes to spill multi-register NEON values. This was caught by
gcc.c-torture/execute/pr47538.c.
Also, aarch64_shift_truncation_mask used GET_MODE_BITSIZE - 1.
GET_MODE_UNIT_BITSIZE - 1 is equivalent for the cases that it handles
(which are all scalars), and I think it's more obvious, since if we ever
do use this for elementwise shifts of vector modes, the mask will depend
on the number of bits in each element rather than the number of bits in
the whole vector.
2018-01-11 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64-modes.def (NUM_POLY_INT_COEFFS): Set to 2.
* config/aarch64/aarch64-protos.h (aarch64_initial_elimination_offset):
Return a poly_int64 rather than a HOST_WIDE_INT.
(aarch64_offset_7bit_signed_scaled_p): Take the offset as a poly_int64
rather than a HOST_WIDE_INT.
* config/aarch64/aarch64.h (aarch64_frame): Protect with
HAVE_POLY_INT_H rather than HOST_WIDE_INT. Change locals_offset,
hard_fp_offset, frame_size, initial_adjust, callee_offset and
final_offset from HOST_WIDE_INT to poly_int64.
* config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args): Use
to_constant when getting the number of units in an Advanced SIMD
mode.
(aarch64_builtin_vectorized_function): Check for a constant number
of units.
* config/aarch64/aarch64-simd.md (mov<mode>): Handle polynomial
GET_MODE_SIZE.
(aarch64_ld<VSTRUCT:nregs>_lane<VALLDIF:mode>): Use the nunits
attribute instead of GET_MODE_NUNITS.
* config/aarch64/aarch64.c (aarch64_hard_regno_nregs)
(aarch64_class_max_nregs): Use the constant_lowest_bound of the
GET_MODE_SIZE for fixed-size registers.
(aarch64_const_vec_all_same_in_range_p): Use const_vec_duplicate_p.
(aarch64_hard_regno_call_part_clobbered, aarch64_classify_index)
(aarch64_mode_valid_for_sched_fusion_p, aarch64_classify_address)
(aarch64_legitimize_address_displacement, aarch64_secondary_reload)
(aarch64_print_operand, aarch64_print_address_internal)
(aarch64_address_cost, aarch64_rtx_costs, aarch64_register_move_cost)
(aarch64_short_vector_p, aapcs_vfp_sub_candidate)
(aarch64_simd_attr_length_rglist, aarch64_operands_ok_for_ldpstp):
Handle polynomial GET_MODE_SIZE.
(aarch64_hard_regno_caller_save_mode): Likewise. Return modes
wider than SImode without modification.
(tls_symbolic_operand_type): Use strip_offset instead of split_const.
(aarch64_pass_by_reference, aarch64_layout_arg, aarch64_pad_reg_upward)
(aarch64_gimplify_va_arg_expr): Assert that we don't yet handle
passing and returning SVE modes.
(aarch64_function_value, aarch64_layout_arg): Use gen_int_mode
rather than GEN_INT.
(aarch64_emit_probe_stack_range): Take the size as a poly_int64
rather than a HOST_WIDE_INT, but call sorry if it isn't constant.
(aarch64_allocate_and_probe_stack_space): Likewise.
(aarch64_layout_frame): Cope with polynomial offsets.
(aarch64_save_callee_saves, aarch64_restore_callee_saves): Take the
start_offset as a poly_int64 rather than a HOST_WIDE_INT. Track
polynomial offsets.
(offset_9bit_signed_unscaled_p, offset_12bit_unsigned_scaled_p)
(aarch64_offset_7bit_signed_scaled_p): Take the offset as a
poly_int64 rather than a HOST_WIDE_INT.
(aarch64_get_separate_components, aarch64_process_components)
(aarch64_expand_prologue, aarch64_expand_epilogue)
(aarch64_use_return_insn_p): Handle polynomial frame offsets.
(aarch64_anchor_offset): New function, split out from...
(aarch64_legitimize_address): ...here.
(aarch64_builtin_vectorization_cost): Handle polynomial
TYPE_VECTOR_SUBPARTS.
(aarch64_simd_check_vect_par_cnst_half): Handle polynomial
GET_MODE_NUNITS.
(aarch64_simd_make_constant, aarch64_expand_vector_init): Get the
number of elements from the PARALLEL rather than the mode.
(aarch64_shift_truncation_mask): Use GET_MODE_UNIT_BITSIZE
rather than GET_MODE_BITSIZE.
(aarch64_evpc_trn, aarch64_evpc_uzp, aarch64_evpc_ext)
(aarch64_evpc_rev, aarch64_evpc_dup, aarch64_evpc_zip)
(aarch64_expand_vec_perm_const_1): Handle polynomial
d->perm.length () and d->perm elements.
(aarch64_evpc_tbl): Likewise. Use nelt rather than GET_MODE_NUNITS.
Apply to_constant to d->perm elements.
(aarch64_simd_valid_immediate, aarch64_vec_fpconst_pow_of_2): Handle
polynomial CONST_VECTOR_NUNITS.
(aarch64_move_pointer): Take amount as a poly_int64 rather
than an int.
(aarch64_progress_pointer): Avoid temporary variable.
* config/aarch64/aarch64.md (aarch64_<crc_variant>): Use
the mode attribute instead of GET_MODE.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256533
[AArch64] Rework interface to add constant/offset routines
The port had aarch64_add_offset and aarch64_add_constant routines
that did similar things. This patch replaces them with an expanded
version of aarch64_add_offset that takes separate source and
destination registers. The new routine also takes a poly_int64 offset
instead of a HOST_WIDE_INT offset, but it leaves the HOST_WIDE_INT
case to aarch64_add_offset_1, which is basically a repurposed
aarch64_add_constant_internal. The SVE patch will put the handling
of VL-based constants in aarch64_add_offset, while still using
aarch64_add_offset_1 for the constant part.
The vcall_offset == 0 path in aarch64_output_mi_thunk will use temp0
as well as temp1 once SVE is added.
A side-effect of the patch is that we now generate:
mov x29, sp
instead of:
add x29, sp, 0
in the pr70044.c test.
2018-01-11 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_force_temporary): Assert that
x exists before using it.
(aarch64_add_constant_internal): Rename to...
(aarch64_add_offset_1): ...this. Replace regnum with separate
src and dest rtxes. Handle the case in which they're different,
including when the offset is zero. Replace scratchreg with an rtx.
Use 2 additions if there is no spare register into which we can
move a 16-bit constant.
(aarch64_add_constant): Delete.
(aarch64_add_offset): Replace reg with separate src and dest
rtxes. Take a poly_int64 offset instead of a HOST_WIDE_INT.
Use aarch64_add_offset_1.
(aarch64_add_sp, aarch64_sub_sp): Take the scratch register as
an rtx rather than an int. Take the delta as a poly_int64
rather than a HOST_WIDE_INT. Use aarch64_add_offset.
(aarch64_expand_mov_immediate): Update uses of aarch64_add_offset.
(aarch64_expand_prologue): Update calls to aarch64_sub_sp,
aarch64_allocate_and_probe_stack_space and aarch64_add_offset.
(aarch64_expand_epilogue): Update calls to aarch64_add_offset
and aarch64_add_sp.
(aarch64_output_mi_thunk): Use aarch64_add_offset rather than
aarch64_add_constant.
Richard Biener [Thu, 11 Jan 2018 12:12:39 +0000 (12:12 +0000)]
re PR lto/81968 (early lto debug objects make Solaris ld SEGV)
2018-01-11 Richard Biener <rguenther@suse.de>
Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
PR lto/81968
libiberty/
* simple-object-common.h (struct simple_object_functions):
Change copy_lto_debug_sections callback signature.
* simple-object-elf.c (SHN_HIRESERVE, SHT_SYMTAB_SHNDX,
SHF_INFO_LINK): Add defines.
(simple_object_elf_copy_lto_debug_sections): Instead of
leaving not to be copied sections empty unnamed SHT_NULL
remove them from the target section headers and adjust section
reference everywhere. Handle SHN_XINDEX in the symbol table
processing properly.
* simple-object.c (handle_lto_debug_sections): Change
interface to return a modified string and handle renaming
of relocation sections.
Sudakshina Das [Thu, 11 Jan 2018 10:46:59 +0000 (10:46 +0000)]
[PR82096] Fix ICE in int_mode_for_mode with arm-linux-gnueabi
The bug reported a particular test di-longlong64-sync-1.c failing when run
on arm-linux-gnueabi with options -mthumb -march=armv5t -O[g,1,2,3] and
-mthumb -march=armv6 -O[g,1,2,3].
The crash was caused because of the explicit VOIDmode argument that is sent
to emit_store_flag_force () and that the emit_store_flag_force () was not
handling the VOIDmode adequately. This patch fixes that.
ChangeLog entries:
*** gcc/ChangeLog ***
2017-01-11 Sudakshina Das <sudi.das@arm.com>
PR target/82096
* expmed.c (emit_store_flag_force): Swap if const op0
and change VOIDmode to mode of op0.
*** gcc/testsuite/ChangeLog ***
2017-01-11 Sudakshina Das <sudi.das@arm.com>
PR target/82096
* gcc.c-torture/compile/pr82096.c: New test.
Fix mode_for_size units in caller-save.c (PR83761)
The new opt_mode asserts triggered for replace_reg_with_saved_mem
because it was passing bytes rather than bits to mode_for_size.
Previously we ended up with a BLKmode register instead, but
presumably that didn't matter because this is "only" used for
debug insns.
2018-01-11 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
PR rtl-optimization/83761
* caller-save.c (replace_reg_with_saved_mem): Pass bits rather
than bytes to mode_for_size.
Gary Dismukes [Thu, 11 Jan 2018 08:56:18 +0000 (08:56 +0000)]
[Ada] Warning on out-of-range value for default-initialized scalar object
When an object of a type with a specified Default_Value aspect is
declared without an explicit initial value and the default value is
out of range of the objects subtype, the compiler now issues a warning
that Constraint_Error will be raised due to an out-of-range value.
The test below must output a compiler warning as follows:
$ gcc -c -gnatj70 default_warning.adb
default_warning.adb:7:08: warning: value not in range of type
"Subint" defined at line 5,
"Constraint_Error" will be raised at run
time
procedure Default_Warning is
type Int_With_Default is new Integer with Default_Value => 0;
subtype Subint is Int_With_Default range 1 .. 100;
S : Subint;
begin
null;
end Default_Warning;
2018-01-11 Gary Dismukes <dismukes@adacore.com>
gcc/ada/
* exp_ch3.adb (Default_Initialize_Object): Call New_Copy_Tree on the
result of Get_Simple_Init_Value and pass the source location of the
object declaration's object_definition.
Ed Schonberg [Thu, 11 Jan 2018 08:56:12 +0000 (08:56 +0000)]
[Ada] Crash on build-in-place call with address specification for target
The presence of an address clause complicates the build-in-place expansion
because the indicated address must be processed before the indirect call is
generated, including the definition of a local pointer to the object.
The address clause may come from an aspect specification or from an explicit
attribute specification appearing after the object declaration. These two
cases require different processing.
2018-01-11 Ed Schonberg <schonberg@adacore.com>
gcc/ada/
* exp_ch6.adb (Make_Build_In_Place_Call_In_Object_Declaration): Handle
properly object declarations with initializations that are
build-in-place function calls, when there is an address specification,
either as an aspect specification or an explicit attribute
specification clause, for the initialized object.
* freeze.adb (Check_Address_Clause): Do not remove side-effects from
initial expressions in the case of a build-in-place call.
gcc/testsuite/
* gnat.dg/bip_overlay.adb, gnat.dg/bip_overlay.ads: New testcase.
Piotr Trojanek [Thu, 11 Jan 2018 08:56:07 +0000 (08:56 +0000)]
[Ada] Allow uses of range utility routines on private types
Frontend only calls Is_Null_Range and Not_Null_Range routines on full views
of types, but backends (for example GNATprove) might call them also on
private types. This patch adapts those routines to transparently retrieve
the full type when called on a private type.
No frontend test, because only external backends are affected.
2018-01-11 Piotr Trojanek <trojanek@adacore.com>
gcc/ada/
* sem_eval.adb (Is_Null_Range): Retrieve the full view when called on a
private (sub)type; refactor to avoid early return statement.
(Not_Null_Range): Same as above.
This patch ensures that single concurrent type declarations are marked as Ghost
when they appear within a Ghost region. In addition, the patch verifies that no
concurrent type is declared within a Ghost region and issues an error.
------------
-- Source --
------------
-- types.ads
package Types with Ghost is
protected Prot_Obj is -- Error
end Prot_Obj;
protected type Prot_Typ is -- Error
end Prot_Typ;
task Task_Obj; -- Error
task type Task_Typ; -- Error
end Types;
----------------------------
-- Compilation and output --
----------------------------
$ gcc -c types.ads
types.ads:2:14: ghost type "Prot_Obj" cannot be concurrent
types.ads:5:19: ghost type "Prot_Typ" cannot be concurrent
types.ads:8:09: ghost type "Task_Obj" cannot be concurrent
types.ads:10:14: ghost type "Task_Typ" cannot be concurrent
* freeze.adb (Freeze_Entity): Ensure that a Ghost type is not
concurrent, nor effectively volatile.
* ghost.adb (Check_Ghost_Type): New routine.
* ghost.ads (Check_Ghost_Type): New routine.
* sem_util.adb (Is_Declaration): Reimplemented. The routine can now
consider specific subsets of declarations.
(Is_Declaration_Other_Than_Renaming): Removed. Its functionality is
replicated by Is_Declaration.
* sem_util.ads (Is_Declaration): New parameter profile. Update the
comment on usage.
(Is_Declaration_Other_Than_Renaming): Removed.
[Ada] Detection of illegal constituent assignments
This patch modifies the analysis of assignment statements to detect an illegal
attempt to alter the value of single protected type Part_Of constituent when
inside a protected function.
* sem_ch5.adb (Analyze_Assignment): Assignments to variables that act
as Part_Of consituents of single protected types are illegal when they
take place inside a protected function.
(Diagnose_Non_Variable_Lhs): Use Within_Function to check for an
enclosing function.
(Is_Protected_Part_Of_Constituent): New routine.
(Within_Function): New routine.
gcc/testsuite/
* gnat.dg/protected_func.adb, gnat.dg/protected_func.ads: New testcase.
Justin Squirek [Thu, 11 Jan 2018 08:54:34 +0000 (08:54 +0000)]
[Ada] No error on missing enclosing parentheses in Expression Function
This patch fixes an issue whereby an expression within an expression
function declaration or completion without proper parenthesization is
incorrectly accepted by the compiler.
2018-01-11 Justin Squirek <squirek@adacore.com>
gcc/ada/
* par-ch6.adb (Scan_Body_Or_Expression_Function): Add additional check
to make sure a given expression function is properly parenthesized.
This patch updates the detection of illegal with clauses which import private
child packages to properly detect a grandchild of Ada.
------------
-- Source --
------------
-- fake.ads
package Fake is
end Fake;
-- fake-ada.ads
package Fake.Ada is
end Fake.Ada;
-- fake-ada-text_io.ads
package Fake.Ada.Text_IO is
end Fake.Ada.Text_IO;
-- fake-ada-text_io-float_io.ads
private generic
type Num is digits <>;
package Fake.Ada.Text_IO.Float_IO is
end Fake.Ada.Text_IO.Float_IO;
-- fake-float_io.ads
private generic
type Num is digits <>;
package Fake.Float_IO is
end Fake.Float_IO;
-- main.ads
with Fake.Ada.Text_IO.Float_IO;
with Fake.Float_IO;
package Main is
end Main;
----------------------------
-- Compilation and output --
----------------------------
$ gcc -c main.ads
main.ads:1:06: unit in with clause is private child unit
main.ads:1:06: current unit must also have parent "Text_IO"
main.ads:2:06: unit in with clause is private child unit
main.ads:2:06: current unit must also have parent "Fake"
Ed Schonberg [Thu, 11 Jan 2018 08:54:17 +0000 (08:54 +0000)]
[Ada] Spurious error on referene to subcoponrnt in dynamic predicate
This patch fixes a visibility error in the expression for a dynamic predicate
of a record type, when the expression contains a reference to a subcomponent
of the record given by a selected component whose prefix is the name of the
enclosing component.
Executing
gnatmake -q -gnata main
./main
must yield:
TGV OK
Amtrak broken, as usual
----
with Text_IO; use Text_IO;
with Recpred; use Recpred;
procedure Main is
TGV : Train_Data;
Amtrak : Train_Data;
begin
TGV := (20, (10,10));
Put_Line ("TGV OK");
begin
Amtrak := (30, (40, 40));
exception
when Others =>
Put_Line ("Amtrak broken, as usual");
end;
end;
----
package Recpred is
type Train_Position is record
TTD : Integer;
VSS : Integer;
end record;
type Train_Data is record
MA : Integer;
Front_Position : Train_Position;
end record
with Dynamic_Predicate => MA >= Front_Position.TTD;
end Recpred;
2018-01-11 Ed Schonberg <schonberg@adacore.com>
gcc/ada/
* sem_ch13.adb (Replace_Type_Ref): Handle properly reference to a
subcomponent of the current entity when building the body for a dynamic
predicate function for a record with composite subcomponents.
[Ada] Secondary stack leaks during object initialization
This patch modifies the transient scope mechanism to prevent secondary stack
leaks during object initialization. The modifications are as follows:
1) Prior to this change, the secondary stack was never managed within type
initialization procedures, for reasons unknown. It is speculated that the
controlled type model used at that time may have influenced this decision.
The secondary stack is now managed within type initialization procedures
in order to recover the memory once individual components or whole objects
are initialized.
2) A transient scope now delegates the secondary stack management to an
enclosing scope if there is no suitable context to wrap. This ensures that
the requirement to manage the secondary stack is not lost when the scope was
established for that purpose in mind.
3) A previous mechanism which examined the definition of a type (recursively)
to determine whether the type will involve the secondary stack was removed
because a) the mechanism could not detect this need with certainty, and b) the
trigger for secondary stack usage is now moved to the resolution of function
calls, which is always accurate.
------------
-- Source --
------------
-- types.ads
with Ada.Finalization; use Ada.Finalization;
package Types is
type Ctrl is new Controlled with record
Id : Integer;
end record;
procedure Initialize (Obj : in out Ctrl);
function Make_Ctrl return Ctrl;
function Make_Ctrl_From (Obj : Ctrl) return Ctrl;
type Constr is array (1 .. 3) of Ctrl;
type Unconstr is array (Integer range <>) of Ctrl;
function Make_Constr return Constr;
function Make_Unconstr (Low : Integer; High : Integer) return Unconstr;
type Rec_1 is new Controlled with record
Comp : Ctrl := Make_Ctrl;
end record;
type Rec_2 is new Controlled with record
Comp : Ctrl := Make_Ctrl_From (Make_Ctrl);
end record;
type Rec_3 is new Controlled with record
Comp : Constr := Make_Constr;
end record;
type Rec_4 is new Controlled with record
Comp : Unconstr (1 .. 3) := Make_Unconstr (1, 3);
end record;
type Rec_5 is record
Comp : Integer := 1 + Make_Ctrl.Id;
end record;
type Rec_6 is record
Comp : Boolean := (for all X in 1 .. Make_Ctrl.Id =>
X = Make_Ctrl.Id);
end record;
end Types;
-- types.adb
package body Types is
Id_Gen : Integer := 0;
procedure Initialize (Obj : in out Ctrl) is
begin
Id_Gen := Id_Gen + 1;
Obj.Id := Id_Gen;
end Initialize;
function Make_Constr return Constr is
Result : constant Constr := (others => Make_Ctrl);
begin
return Result;
end Make_Constr;
function Make_Ctrl return Ctrl is
Result : Ctrl;
begin
return Result;
end Make_Ctrl;
function Make_Ctrl_From (Obj : Ctrl) return Ctrl is
Result : Ctrl;
begin
Result.Id := Obj.Id;
return Result;
end Make_Ctrl_From;
function Make_Unconstr (Low : Integer; High : Integer) return Unconstr is
Result : constant Unconstr (Low .. High) := (others => Make_Ctrl);
begin
return Result;
end Make_Unconstr;
end Types;
-- maker.ads
generic
type Obj_Typ is private;
procedure Maker (Count : Positive);
-- maker.adb
procedure Maker (Count : Positive) is
procedure Create is
Obj : Obj_Typ;
pragma Warnings (Off, Obj);
begin null; end Create;
begin
for Iter in 1 .. Count loop
Create;
end loop;
end Maker;
-- leaks.adb
with Maker;
with Types; use Types;
with Maker;
with Types; use Types;
procedure Leaks is
procedure Make_1 is new Maker (Rec_1);
procedure Make_2 is new Maker (Rec_2);
procedure Make_3 is new Maker (Rec_3);
procedure Make_4 is new Maker (Rec_4);
procedure Make_5 is new Maker (Rec_5);
procedure Make_6 is new Maker (Rec_6);
begin
Make_1 (5_000);
Make_2 (5_000);
Make_3 (5_000);
Make_4 (5_000);
Make_5 (5_000);
Make_6 (5_000);
end Leaks;
----------------------------
-- Compilation and output --
----------------------------
* exp_aggr.adb (Convert_Aggr_In_Object_Decl): Update the call to
Establish_Transient_Scope.
(Convert_To_Assignments): Update the call to Establish_Transient_Scope.
(Expand_Array_Aggregate): Update the call to Establish_Transient_Scope.
* exp_ch6.adb (Expand_Call_Helper): Update the call to
Establish_Transient_Scope.
(Make_Build_In_Place_Call_In_Object_Declaration): Update the call to
Establish_Transient_Scope.
* exp_ch7.adb (Establish_Transient_Scope): Restructured. Delegate the
management of the secondary stack to an enclosing scope if there is no
suitable construct to wrap, and the transient scope was intended to
manage the secondary stack.
(Find_Node_To_Be_Wrapped): Restructured. A case_statement_alternative
is a valid boundary for a transient expression which comes from the
statements of the alternative, otherwise alternatives cannot be
wrapped. Assignments of controlled objects which have controlled
actions suppressed now stop the traversal as there is no point in
looking for an enclosing construct. Add several N_xxx_Body choices to
the termination conditions for completeness.
* exp_ch7.ads (Establish_Transient_Scope): Update the parameter profile
and the associated comment on usage.
* exp_smem.adb (Add_Shared_Var_Lock_Procs): Update the call to
Establish_Transient_Scope.
(Add_Write_After): Update the call to Establish_Transient_Scope.
* sem_res.adb (Check_Initialization_Call): Removed.
(Resolve_Actuals): Account for additional cases where finalization
actions are required by utilizing predicate Needs_Finalization rather
than Is_Controlled.
(Resolve_Call): Type initialization procedures can now utilize
transient scopes to manage the secondary stack, thus preventing leaks
during initialization. Remove the previous kludgy algorithm which
attempts to manage the secondary stack at the object creation site.
Bob Duff [Thu, 11 Jan 2018 08:53:27 +0000 (08:53 +0000)]
[Ada] gnatbind -f switch gives an error for duplicates
If the -felab-order.txt switch is given to gnatbind, and there are duplicate
unit names in elab-order.txt, an error will be given.
The following test should get errors:
this (spec) <-- that (body)
error: elab-order.txt:5: duplicate unit name "this (spec)" from line 1
error: elab-order.txt:7: duplicate unit name "that (body)" from line 3
gnatmake: *** bind failed.
package body That is
end That;
package That is
pragma Elaborate_Body;
end That;
with This, That;
procedure That.Main is
begin
null;
end That.Main;
package body This is
end This;
package This is
pragma Elaborate_Body;
end This;
2018-01-11 Bob Duff <duff@adacore.com>
gcc/ada/
* binde.adb (Force_Elab_Order): Give an error if there are duplicate
unit names.
Ed Schonberg [Thu, 11 Jan 2018 08:53:15 +0000 (08:53 +0000)]
[Ada] Crash on expression function as completion, with implicit dereference
An implicit dereference freezes the corresponding designated type. Most
implicit dereferences are made explicit during expansion, but this is not the
case for a dispatching call where the the controlling parameter and the
corresponding controlling argument are access to a tagged type. In that case,
to enforce the rule that an expression function that is a completion freezes
type references within, we must locate controlling arguments of an access type
and freeze explicitly the corresponding designated type.
2018-01-11 Ed Schonberg <schonberg@adacore.com>
gcc/ada/
* sem_ch6.adb (Freeze_Expr_Types): If an access value is the
controlling argument of a dispatching call. freeze the corresponding
designated type.
gcc/testsuite/
* gnat.dg/expr_func3.adb, gnat.dg/expr_func3.ads: New testcase.
git://gcc.gnu.org / gcc.git / log