Georg-Johann Lay [Tue, 23 May 2023 12:54:12 +0000 (14:54 +0200)]
target/104327: Allow more inlining between different optimization levels.
avr-common.cc introduces the following options that are set depending
on optimization level: -mgas-isr-prologues, -mmain-is-OS-task and
-fsplit-wide-types-early. The inliner thinks that different options
disallow cross-optimization inlining, so provide can_inline_p.
gcc/
PR target/104327
* config/avr/avr.cc (avr_can_inline_p): New static function.
(TARGET_CAN_INLINE_P): Define to that function.
Georg-Johann Lay [Thu, 25 May 2023 17:02:34 +0000 (19:02 +0200)]
target/82931: Make a pattern more generic to match more bit-transfers.
There is already a pattern in avr.md that matches single-bit transfers
from one register to another one, but it only handled bit 0 of 8-bit
registers. This change makes that pattern more generic so it matches
more of similar single-bit transfers.
gcc/
PR target/82931
* config/avr/avr.md (*movbitqi.0): Rename to *movbit<mode>.0-6.
Handle any bit position and use mode QISI.
* config/avr/avr.cc (avr_rtx_costs_1) [IOR]: Return a cost
of 2 insns for bit-transfer of respective style.
gcc/testsuite/
PR target/82931
* gcc.target/avr/pr82931.c: New test.
Ju-Zhe Zhong [Thu, 25 May 2023 14:42:35 +0000 (22:42 +0800)]
VECT: Add decrement IV iteration loop control by variable amount support
This patch is supporting decrement IV by following the flow designed by
Richard:
(1) In vect_set_loop_condition_partial_vectors, for the first iteration of:
call vect_set_loop_controls_directly.
(2) vect_set_loop_controls_directly calculates "step" as in your patch.
If rgc has 1 control, this step is the SSA name created for that
control. Otherwise the step is a fresh SSA name, as in your patch.
(3) vect_set_loop_controls_directly stores this step somewhere for later
use, probably in LOOP_VINFO. Let's use "S" to refer to this stored
step.
(4) After the vect_set_loop_controls_directly call above, and outside
the "if" statement that now contains vect_set_loop_controls_directly,
check whether rgc->controls.length () > 1. If so, use
vect_adjust_loop_lens_control to set the controls based on S.
Then the only caller of vect_adjust_loop_lens_control is
vect_set_loop_condition_partial_vectors. And the starting
step for vect_adjust_loop_lens_control is always S.
This patch has well tested for single-rgroup and multiple-rgroup (SLP)
and passed all testcase in RISC-V port.
Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai> Co-Authored-By: Richard Sandiford <richard.sandiford@arm.com>
gcc/ChangeLog:
* tree-vect-loop-manip.cc (vect_adjust_loop_lens_control): New
function.
(vect_set_loop_controls_directly): Add decrement IV support.
(vect_set_loop_condition_partial_vectors): Ditto.
* tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): New
variable.
* tree-vectorizer.h (LOOP_VINFO_USING_DECREMENTING_IV_P): New
macro.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c: New test.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c: New test.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: New test.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: New test.
Kyrylo Tkachov [Thu, 25 May 2023 14:00:16 +0000 (15:00 +0100)]
aarch64: PR target/99195 Annotate complex FP patterns for vec-concat-zero
This patch annotates the complex add and mla patterns for vec-concat-zero.
Testing showed an interesting bug in our MD patterns where they were defined to match:
(plus:VHSDF (match_operand:VHSDF 1 "register_operand" "0")
(unspec:VHSDF [(match_operand:VHSDF 2 "register_operand" "w")
(match_operand:VHSDF 3 "register_operand" "w")
(match_operand:SI 4 "const_int_operand" "n")]
FCMLA))
but the canonicalisation rules for PLUS require the more "complex" operand to be first so
during combine when the new substituted patterns were attempted to be formed combine/recog would
try to match:
(plus:V2SF (unspec:V2SF [
(reg:V2SF 100)
(reg:V2SF 101)
(const_int 0 [0])
] UNSPEC_FCMLA270)
(reg:V2SF 99))
instead. This patch fixes the operands of the PLUS RTX in these patterns.
Similar patterns for the dot-product instructions already used the right order.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
gcc/ChangeLog:
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_fcadd<rot><mode>): Rename to...
(aarch64_fcadd<rot><mode><vczle><vczbe>): ... This.
Fix canonicalization of PLUS operands.
(aarch64_fcmla<rot><mode>): Rename to...
(aarch64_fcmla<rot><mode><vczle><vczbe>): ... This.
Fix canonicalization of PLUS operands.
(aarch64_fcmla_lane<rot><mode>): Rename to...
(aarch64_fcmla_lane<rot><mode><vczle><vczbe>): ... This.
Fix canonicalization of PLUS operands.
(aarch64_fcmla_laneq<rot>v4hf): Rename to...
(aarch64_fcmla_laneq<rot>v4hf<vczle><vczbe>): ... This.
Fix canonicalization of PLUS operands.
(aarch64_fcmlaq_lane<rot><mode>): Fix canonicalization of PLUS operands.
gcc/testsuite/ChangeLog:
PR target/99195
* gcc.target/aarch64/simd/pr99195_9.c: New test.
Chris Sidebottom [Thu, 25 May 2023 13:57:34 +0000 (14:57 +0100)]
arm: Implement ACLE Data Intrinsics
This patch implements a number of scalar data processing intrinsics from ACLE
that were requested by some users. Some of these have fast single-instruction
sequences for Armv6 and later, but even for earlier versions they can still emit
an inline sequence or a call to libgcc (and ACLE recommends them being unconditionally
available).
Chris Sidebottom wrote most of the patch, I just cleaned it up, wired up some builtins
and adjusted the tests.
Bootstrapped and tested on arm-none-linux-gnueabihf.
Co-authored-by: Chris Sidebottom <chris.sidebottom@arm.com>
gcc/ChangeLog:
* gcc.target/arm/acle/data-intrinsics-armv6.c: New test.
* gcc.target/arm/acle/data-intrinsics-assembly.c: New test.
* gcc.target/arm/acle/data-intrinsics-rbit.c: New test.
* gcc.target/arm/acle/data-intrinsics.c: New test.
where M1 and M2 are of equal mode size. That is problematic for the splitter
vfp.md:no_literal_pool_df_immediate in the arm backend, which tries to pun an
lvalue DFmode pseudo into DImode and assign a constant to it with
emit_move_insn, as the new transformation simply undoes this, and we end up
splitting indefinitely.
This patch changes things around in the arm backend so that we use a
DImode temporary (instead of DFmode) and first load the DImode constant
into the pseudo, and then pun the pseudo into DFmode as an rvalue in a
reg -> reg move. I believe this should be semantically equivalent but
avoids the pathalogical behaviour seen in the PR.
gcc/ChangeLog:
PR target/109800
* config/arm/arm.md (movdf): Generate temporary pseudo in DImode
instead of DFmode.
* config/arm/vfp.md (no_literal_pool_df_immediate): Rather than punning an
lvalue DFmode pseudo into DImode, use a DImode pseudo and pun it into
DFmode as an rvalue.
gcc/testsuite/ChangeLog:
PR target/109800
* gcc.target/arm/pure-code/pr109800.c: New test.
Richard Biener [Thu, 25 May 2023 10:55:11 +0000 (12:55 +0200)]
target/109955 - handle pattern generated COND_EXPR without vcond
The following properly handles pattern matching generated COND_EXPRs
which can still have embedded compares in vectorizable_condition
which will always code generate the masked vector variant. We
were requiring vcond with embedded comparisons instead of also
allowing (as code generated) split compare and VEC_COND_EXPR.
This fixes some of the fallout when removing vcond{,u,eq} expanders
from the x86 backend.
PR target/109955
* tree-vect-stmts.cc (vectorizable_condition): For
embedded comparisons also handle the case when the target
only provides vec_cmp and vcond_mask.
arc: Make TLS Local Dynamic work like Global Dynamic model
Current ARC's TLS Local Dynamic model is using two anchors to access
data, namely `.tdata` and `.tbss`. This implementation is unnecessary
complicated. However, the TLS Local Dynamic model has better results
using Global Dynamic model and anchors.
gcc/ChangeLog;
* config/arc/arc.cc (arc_call_tls_get_addr): Simplify access using
TLS Local Dynamic.
Kyrylo Tkachov [Thu, 25 May 2023 08:48:33 +0000 (09:48 +0100)]
aarch64: Implement vector FP absolute compare intrinsics with builtins
While optimising some vector math library code with intrinsics we stumbled upon the issue in the testcase.
The compiler should be generating a FACGT instruction but instead we generate:
foo(__Float32x4_t, __Float32x4_t, __Float32x4_t):
fabs v0.4s, v0.4s
adrp x0, .LC0
ldr q31, [x0, #:lo12:.LC0]
fcmgt v0.4s, v0.4s, v31.4s
ret
This is because the vcagtq_f32 intrinsic is open-coded in arm_neon.h as
return vabsq_f32 (__a) > vabsq_f32 (__b)
thus relying on the optimisers to merge it back together. But since one of the arms of the comparison
is a vector constant the combine pass optimises the abs into it and tries matching:
(set (reg:V4SI 101)
(neg:V4SI (gt:V4SI (reg:V4SF 100)
(const_vector:V4SF [
(const_double:SF 1.0e+2 [0x0.c8p+7]) repeated x4
]))))
and
(set (reg:V4SI 101)
(neg:V4SI (gt:V4SI (abs:V4SF (reg:V4SF 104))
(reg:V4SF 103))))
instead of what we want:
(insn 13 9 14 2 (set (reg/i:V4SI 32 v0)
(neg:V4SI (gt:V4SI (abs:V4SF (reg:V4SF 98))
(abs:V4SF (reg:V4SF 96)))))
I don't really see a good way around that with our current implementation of these intrinsics.
Therefore this patch reimplements these intrinsics with aarch64 builtins that generate the RTL for these
instructions directly. Apparently we already had them defined in aarch64-simd-builtins.def and have been
using them for the fp16 case already.
I realise that this approach is against the general principle of expressing intrinsics in the higher-level constructs,
so I'm willing to listen to counter-arguments.
That said, the FACGT/FACGE instructions are as fast as the non-ABS comparison instructions on all microarchitectures that I know of
so it should always be a win to have them in the merged form rather than split the fabs step separately or try to hoist it.
And the testcase does come from real library code that we're trying to optimise.
With this patch for the testcase we generate:
foo:
adrp x0, .LC0
ldr q31, [x0, #:lo12:.LC0]
facgt v0.4s, v0.4s, v31.4s
ret
Javier Miranda [Tue, 28 Feb 2023 18:20:38 +0000 (18:20 +0000)]
ada: Missing warning on null-excluding array aggregate component
The compiler does not report warnings on the initialization
of arrays of null-excluding access type components by means
of iterated component association, when the expression
initializing each component is either a conditional
expression or a case expression that may initialize
some component with a null value.
gcc/ada/
* sem_aggr.adb
(Warn_On_Null_Component_Association): New subprogram.
(Empty_Range): Adding missing support for iterated component
association node.
(Resolve_Array_Aggregate): Report warning on iterated component
association that may initialize some component of an array of
null-excluding access type components with a null value.
* exp_ch4.adb
(Expand_N_Expression_With_Actions): Add missing type check since
the subtype of the EWA node and the subtype of the expression
may differ.
Tom Tromey [Wed, 8 Mar 2023 17:21:59 +0000 (10:21 -0700)]
ada: Require successful build of xsnamest
While experimenting, I introduced a compilation error into xsnamest.
This took a little while to track down because, while the error was in
the log, the build did not stop. This patch changes Make-generated.in
to require a successful build of this program.
gcc/ada/
* Make-generated.in (ada/stamp-snames): Check result of
gnatmake.
Eric Botcazou [Wed, 8 Mar 2023 22:02:34 +0000 (23:02 +0100)]
ada: Minor adjustments to Standard_Address
Standard_Address is an internal entity that is meant to be a clone of
System.Address built at compilation startup. It needs to be seen as a
bona-fide address by the code generator. For the sake of completeness,
it is also given its modulus, although this does not matter in practice.
gcc/ada/
* cstand.adb (Create_Standard): Set the Is_Descendant_Of_Address
flag on Standard_Address.
* freeze.adb (Freeze_Entity): Copy the modulus of System.Address
onto Standard_Address.
Eric Botcazou [Wed, 8 Mar 2023 17:11:31 +0000 (18:11 +0100)]
ada: Add size clause to System.Address
Standard'Address_Size is the value provided by the code generator for the
size of pointers, and it is set as the default size of every thin pointer
by the front-end. Now it is documented in the GNAT RM as having the value
of System.Address'Size, which is indeed the case on (correctly configured)
platforms where pointers contain exactly the number of bits that are needed
to address the memory space.
However, on platforms where pointers contain additional bits of metadata,
it has a larger value and the documented relation does not hold, which also
means that unchecked conversions between System.Address and pointers are
seen as potentially problematic. In order to fix the discrepancy on these
platforms, this change adds the obvious size clause to System.Address, which
is confirming on all the other (correctly configured) platforms.
Bob Duff [Wed, 8 Mar 2023 17:15:13 +0000 (12:15 -0500)]
ada: Switch from E_Void to Is_Not_Self_Hidden
We had previously used Ekind = E_Void to indicate that a declaration is
self-hidden. We now use the Is_Not_Self_Hidden flag instead. This allows
us to avoid many "vanishing fields", which are (possibly-latent) bugs,
and we now enable the assertions in Atree that detect such bugs.
gcc/ada/
* atree.adb (Check_Vanishing_Fields): Fix bug in the "blah type
only" cases. Remove the special cases for E_Void. Misc cleanup.
(Mutate_Nkind): Disallow mutating to the same kind.
(Mutate_Ekind): Disallow mutating to E_Void.
(From E_Void is still OK -- entities start out as E_Void by
default.) Fix bug in statistics gathering -- was setting the wrong
count. Enable Check_Vanishing_Fields for entities.
* sem_ch8.adb (Is_Self_Hidden): New function.
(Find_Direct_Name): Call Is_Self_Hidden to use the new
Is_Not_Self_Hidden flag to determine whether a declaration is
hidden from all visibility by itself. This replaces the old method
of checking E_Void.
(Find_Expanded_Name): Likewise.
(Find_Selected_Component): Likewise.
* sem_util.adb (Enter_Name): Remove setting of Ekind to E_Void.
* sem_ch3.adb: Set the Is_Not_Self_Hidden flag in appropriate
places. Comment fixes.
(Inherit_Component): Remove setting of Ekind to E_Void.
* sem_ch9.adb
(Analyze_Protected_Type_Declaration): Update comment. Skip Itypes,
which should not be turned into components.
* atree.ads (Mutate_Nkind): Document error case.
(Mutate_Ekind): Remove comments apologizing for E_Void mutations.
Document error cases.
Eric Botcazou [Wed, 8 Mar 2023 14:12:27 +0000 (15:12 +0100)]
ada: Decouple size of addresses and pointers from size of memory space
This decouples the size of the types representing addresses and pointers,
which is Standard'Address_Size, from the size of the memory space, which
is System.Memory_Size (more precisely log2 of it). They are tied through
the definition of System.Address:
type Address is mod Memory_Size;
so Standard'Address_Size >= log2 (System.Memory_Size) necessarily, but the
equality does not hold on platforms where addresses and pointers contain
additional bits of metadata.
gcc/ada/
* libgnat/a-ststio.adb (Set_Mode): Test System.Memory_Size.
* libgnat/g-debuti.ads (Address_64): Likewise.
* libgnat/i-c.ads: Add with clause for System.
(ptrdiff_t): Define based on the size of memory space.
(size_t): Likewise.
* libgnat/s-crtl.ads (size_t): Likewise.
(ssize_t): Likewise.
* libgnat/s-memory.ads (size_t): Likewise.
* libgnat/s-parame.ads (Size_Type): Likewise.
* libgnat/s-parame__hpux.ads (Size_Type): Likewise.
* libgnat/s-parame__posix2008.ads (Size_Type): Likewise.
* libgnat/s-parame__vxworks.ads (Size_Type): Likewise.
* libgnat/s-putima.adb (Signed_Address): Likewise.
(Unsigned_Address): Likewise.
* libgnat/s-stoele.ads (Storage_Offset): Likewise.
Piotr Trojanek [Wed, 8 Mar 2023 14:30:41 +0000 (15:30 +0100)]
ada: Fix copying of quantified expressions
While visiting the AST as part of routine New_Copy_Tree we maintain
an EWA_Level variable in a stack-like fashion. This worked fine for
expression with actions nodes but not for quantified expressions.
gcc/ada/
* sem_util.adb (Visit_Node): Decrement EWA_Level with the same condition
as when it was incremented.
Piotr Trojanek [Wed, 8 Mar 2023 10:41:42 +0000 (11:41 +0100)]
ada: Deconstruct a no longer used parameter of New_Copy_Tree
Parameter Scopes_In_EWA_OK of New_Copy_Tree was introduced in 2018 to
deal with expressions-with-actions (EWA) in the build-in-place
machinery. However, after changes made in 2022 it is no longer used by
any caller.
Cleanup related to handling of expression functions in GNATprove;
semantics is unaffected.
gcc/ada/
* sem_util.ads (New_Copy_Tree): Remove Scopes_In_EWA_OK from spec;
adapt comment.
* sem_util.adb (New_Copy_Tree): Remove Scopes_In_EWA_OK from body;
adapt code.
Piotr Trojanek [Tue, 7 Mar 2023 18:52:40 +0000 (19:52 +0100)]
ada: Simplify copying of node lists
When creating a copy of a node list we called Copy_Entity for entities
and Copy_Separate_Tree for other nodes. This was unnecessary, because
the Copy_Separate_Tree when called on entities will just do Copy_Entity.
Code cleanup; semantics is unaffected.
gcc/ada/
* atree.adb (Copy_List): Call Copy_Separate_Tree for both entities and
other nodes.
Steve Baird [Fri, 3 Mar 2023 00:51:57 +0000 (16:51 -0800)]
ada: Avoid duplicated streaming subprograms
In some common cases, a reference to Some_Type'Some_Streaming_Attribute
causes the needed subprogram to be generated "on demand". If there are
multiple such references (e.g., two calls to Some_Type'Write) then we
want to avoid generating multiple essentially-identical subprograms.
This change implies that a generated streaming subprogram may now have
multiple call sites, so we can no longer use the source position information
from the (one and only) call site. If an exception is raised during a
streaming operation, this can make a difference in the reported raise location.
gcc/ada/
* exp_attr.adb
(Cached_Streaming_Ops): A new package, providing maps to save
previously-generated Read/Write/Input/Output procedures.
(Expand_N_Attribute_Reference): When a new subprogram is generated
for a Read/Write/Input/Output attribute reference, record that
type/subp pair in the appropriate Cached_Streaming_Ops map.
(Find_Stream_Subprogram): Check the appropriate
Cached_Streaming_Ops map to see if an appropriate subprogram has
already been generated. If so, then return it. The appropriateness
test includes a call to a new nested subprogram,
In_Available_Context.
* exp_strm.ads, exp_strm.adb: Do not pass in a Loc parameter (or a
source-location-bearing Nod parameter) to the 16 procedures
provided for building streaming-related subprograms. Use the
source location of the type instead.
* exp_dist.adb, exp_ch3.adb: Adapt to Exp_Strm spec changes. For
these calls the source location of the type was already being
used.
Marc Poulhiès [Tue, 7 Mar 2023 15:35:48 +0000 (16:35 +0100)]
ada: Fix crash during function return analysis
The compiler would crash when checking type relation between the
function's return type and the type of the expression used in the return
statement. It would not work if the function's return type is an access
type and the expression is not.
gcc/ada/
* sem_ch6.adb (Analyze_Function_Return): Add missing
Is_Access_Type check before accessing the Designated_Type field.
Marc Poulhiès [Mon, 6 Mar 2023 11:15:13 +0000 (12:15 +0100)]
ada: Fix (again) incorrect handling of Aggregate aspect
Previous fix stopped the processing of the Aggregate aspect early,
skipping the call to Record_Rep_Item, making later call to
Resolve_Container_Aggregate fail.
Also, the previous fix would not handle correctly the case where the
type is private and the check for non-array type can only be done at the
freeze point with the full type.
Adapt the resolving of the aspect when the input is not correct and the
parameters can't be resolved.
gcc/ada/
* sem_ch13.adb (Analyze_One_Aspect): Call Record_Rep_Item.
(Check_Aspect_At_Freeze_Point): Check the aspect is specified on
non-array type only...
(Analyze_One_Aspect): ... instead of doing it too early here.
* sem_aggr.adb (Resolve_Container_Aggregate): Do nothing in case
the parameters failed to resolve.
Piotr Trojanek [Sat, 4 Mar 2023 17:07:33 +0000 (18:07 +0100)]
ada: Fix comments for recently added SPARK aspects
Implementation of contract Subprogram_Variant and Exceptional_Cases was
based on the existing code for Contract_Cases, i.e. on the existing
occurrences of Aspect_Contract_Cases, Name_Contract_Cases and
Pragma_Contract_Cases. However, occurrences of "Contract_Cases" itself
in the comments were not updated.
gcc/ada/
* contracts.adb
(Add_Pre_Post_Condition): Mention new aspects in the comment.
* contracts.ads
(Add_Contract_Item): Likewise.
(Analyze_Subprogram_Body_Stub_Contract): Likewise.
* sem_prag.adb
(Contract_Freeze_Error): Likewise.
(Ensure_Aggregate_Form): Likewise.
* sem_prag.ads
(Find_Related_Declaration_Or_Body): Likewise.
* sinfo.ads
(Is_Generic_Contract_Pragma): Likewise.
Piotr Trojanek [Fri, 3 Mar 2023 16:45:20 +0000 (17:45 +0100)]
ada: Add missing supportive code for recently added SPARK aspects
Fix minor inconsistencies with the recently added SPARK aspects
Exceptional_Cases and Subprogram_Variant, whose implementation is based
on Contract_Cases.
gcc/ada/
* aspects.ads
(Implementation_Defined_Aspect): Recently added aspects are
implementation-defined, just like Contract_Cases.
* sem_prag.ads
(Aspect_Specifying_Pragma): Recently added aspects have corresponding
pragmas, just like Contract_Cases.
(Pragma_Significant_To_Subprograms): Recently added aspects are
significant to subprograms, just like Contract_Cases.
Piotr Trojanek [Mon, 6 Mar 2023 11:50:04 +0000 (12:50 +0100)]
ada: Tune handling of attributes Old in contract Exceptional_Cases
Contract Exceptional_Cases allows formal parameters to appear *in*
prefixes of attributes Old, but the code only allowed them to appear
*as* prefixes of those attributes.
For example, we now accetp expressions like "X.all'Old" that were
previously rejected.
gcc/ada/
* sem_res.adb (Resolve_Entity_Name): Tune handling of formal parameters
in contract Exceptional_Cases.
Eric Botcazou [Sat, 4 Mar 2023 14:02:32 +0000 (15:02 +0100)]
ada: Small tweak to implementation of by-copy semantics for storage models
Get_Actual_Subtype can be used to access the Actual_Designated_Subtype of
explicit dereferences with a storage model. As a side effect, this also
handles the case where the prefix of the dereference is a formal parameter.
gcc/ada/
* exp_ch6.adb (Add_Simple_Call_By_Copy_Code): Use Get_Actual_Subtype
to retrieve the actual subtype for all actuals and do it in only one
place for all unconstrained composite formal types.
This patch adds documentation to the subprogram Replace_Type in
Sem_Ch3. In particular, references to relevant parts of the Ada
reference manual are added.
gcc/ada/
* sem_ch3.adb (Replace_Type): Add more documentation.
This patch does not change the behavior of the compiler, but is
intended to improve readability. It seizes an opportunity to move
a variable declaration to a smaller scope, so that it's clearer
that the variable is not used outside of that scope.
gcc/ada/
* sem_ch3.adb (Replace_Type): Reduce span of variable.
Bob Duff [Fri, 3 Mar 2023 14:46:34 +0000 (09:46 -0500)]
ada: Set Is_Not_Self_Hidden flag in more cases
More work-in-progress for changing E_Void checks to the flag.
gcc/ada/
* sem_ch9.adb (Analyze_Protected_Type_Declaration): Set the flag
for protected types.
(Analyze_Single_Protected_Declaration): Likewise, for singleton
protected objects.
(Analyze_Task_Type_Declaration): Set the flag for task types.
(Analyze_Single_Task_Declaration): Likewise, for singleton task
objects.
* sem_ch10.adb (Decorate_Type): Set the flag for types treated as
incomplete.
(Build_Shadow_Entity): Set the flag for shadow entities.
(Decorate_State): Set the flag for an abstract state.
(Build_Limited_Views): Set the flag for limited view of package.
* sem_attr.adb (Check_Not_Incomplete_Type): Disable the check when
this is a current instance.
This patch improves the way controlling access parameters are
handled in dispatch table wrappers. The constructions of both the
specifications and the bodies of wrappers are modified.
gcc/ada/
* freeze.adb (Build_DTW_Body): Add appropriate type conversions for
controlling access parameters.
* sem_util.adb (Build_Overriding_Spec): Fix designated types in
controlling access parameters.
Bob Duff [Thu, 2 Mar 2023 15:12:29 +0000 (10:12 -0500)]
ada: Add Entry_Cancel_Parameter to E_Label
...and other (minor) changes.
gcc/ada/
* gen_il-gen-gen_entities.adb (E_Label): Add
Entry_Cancel_Parameter. This is necessary because
Analyze_Implicit_Label_Declaration set the Ekind to E_Label.
Without this change, this field would fail the vanishing-fields
check in Atree (which is currently commented out).
* einfo.ads (Entry_Cancel_Parameter): Document for E_Label.
* sem_eval.adb (Why_Not_Static): Protect against previous errors
(no need to explain why something is not static if it's already
illegal for other reasons).
* sem_util.ads (Enter_Name): Fix misleading comment.
Piotr Trojanek [Thu, 2 Mar 2023 14:11:40 +0000 (15:11 +0100)]
ada: Tune warning about assignment just before a raise statement
Tune warning about a possibly ineffective assignment to a formal
parameter that happens just before a raise statement.
The warning is now emitted for parameters of all by-copy types and not
just of scalar types (this gives more warnings), but is suppressed for
aliased parameters (this removes some spurious warnings).
gcc/ada/
* sem_ch11.adb (Analyze_Raise_Expression): Tune warning condition.
* libgnat/g-dirope.ads (Open): Remove a potentially inaccurate comment.
* libgnat/g-dirope.adb (Open): Remove a potentially useless assignment;
the Dir output parameter should be assigned a null value anyway by the
preceding call to Free.
Marc Poulhiès [Tue, 28 Feb 2023 10:01:47 +0000 (11:01 +0100)]
ada: Fix SPARK context not restored when Load_Unit is failing
When Load_Unit fails to find the unit or encounters an error, the
Load_Fail procedure is called and an exception is raised, skipping the
restoration of the SPARK/Ghost context stored on procedure entry.
gcc/ada/
* rtsfind.adb (Load_RTU.Restore_SPARK_Context): New.
(Load_RTU): Use Restore_SPARK_Context on all exit paths.
* sem_ch6.adb (Analyze_Subprogram_Body_Helper): Initialize local
variable to Empty.
Piotr Trojanek [Tue, 7 Feb 2023 23:54:06 +0000 (00:54 +0100)]
ada: Restrict use of formal parameters within exceptional cases
Restrict references to formal parameters within the new SPARK aspect
Exceptional_Cases and allow occurrences of 'Old in this aspect.
gcc/ada/
* sem_attr.adb
(Analyze_Attribute_Old_Result): Allow uses of 'Old and 'Result within
the new aspect.
* sem_res.adb
(Within_Exceptional_Cases_Consequence): New utility routine.
(Resolve_Entity_Name): Restrict use of formal parameters within the
new aspect.
Aldy Hernandez [Wed, 24 May 2023 17:55:09 +0000 (19:55 +0200)]
Disallow setting of NANs in frange setter unless setting trees.
frange::set() is confusing in that we can set a NAN by specifying a
bound of +-NAN, even though we tecnically disallow NANs in the setter
because the kind can never be VR_NAN. This is a wart for
get_tree_range(), which builds a range out of a tree from the source,
to work correctly. It's ugly, and it showed its limitation while
implementing LTO streaming of ranges.
This patch disallows passing NAN bounds in frange::set() and fixes
get_tree_range.
gcc/ChangeLog:
* value-query.cc (range_query::get_tree_range): Set NAN directly
if necessary.
* value-range.cc (frange::set): Assert that bounds are not NAN.
Aldy Hernandez [Wed, 24 May 2023 17:53:53 +0000 (19:53 +0200)]
Hash known NANs correctly for franges.
We're ICEing when trying to hash a known NAN. This is unnoticeable
because the only user would be IPA, and even so, it currently doesn't
handle floats. However, handling floats is a flip of a switch, so
it's best to handle them already.
Alexandre Oliva [Wed, 24 May 2023 06:07:56 +0000 (03:07 -0300)]
[PR100106] Reject unaligned subregs when strict alignment is required
The testcase for pr100106, compiled with optimization for 32-bit
powerpc -mcpu=604 with -mstrict-align expands the initialization of a
union from a float _Complex value into a load from an SCmode
constant pool entry, aligned to 4 bytes, into a DImode pseudo,
requiring 8-byte alignment.
The patch that introduced the testcase modified simplify_subreg to
avoid changing the MEM to outermode, but simplify_gen_subreg still
creates a SUBREG or a MEM that would require stricter alignment than
MEM's, and lra_constraints appears to get confused by that, repeatedly
creating unsatisfiable reloads for the SUBREG until it exceeds the
insn count.
Avoiding the unaligned SUBREG, expand splits the DImode dest into
SUBREGs and loads each SImode word of the constant pool with the
proper alignment.
for gcc/ChangeLog
PR target/100106
* emit-rtl.cc (validate_subreg): Reject a SUBREG of a MEM that
requires stricter alignment than MEM's.
Alexandre Oliva [Wed, 24 May 2023 06:07:46 +0000 (03:07 -0300)]
[testsuite] tsvc: skip include malloc.h when unavailable
tsvc tests all fail on systems that don't offer a malloc.h, other than
those that explicitly rule that out. Use the preprocessor to test for
malloc.h's availability.
tsvc.h also expects a definition for struct timeval, but it doesn't
include sys/time.h. Add a conditional include thereof.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/tsvc/tsvc.h: Test for and conditionally include
malloc.h and sys/time.h.
Alexandre Oliva [Wed, 24 May 2023 06:08:10 +0000 (03:08 -0300)]
[testsuite] [x86] cope with --enable-frame-pointer
Various x86 tests fail if the toolchain is configured with
--enable-frame-pointer, because the unexpected extra insns mess with
the expected asm counts. Add -fomit-frame-pointer so that they can
still pass.
Andrew MacLeod [Wed, 24 May 2023 13:52:26 +0000 (09:52 -0400)]
Gimple range PHI analyzer and testcases
Provide a PHI analyzer framework to provive better initial values for
PHI nodes which formk groups with initial values and single statements
which modify the PHI values in some predicatable way.
PR tree-optimization/107822
PR tree-optimization/107986
gcc/
* Makefile.in (OBJS): Add gimple-range-phi.o.
* gimple-range-cache.h (ranger_cache::m_estimate): New
phi_analyzer pointer member.
* gimple-range-fold.cc (fold_using_range::range_of_phi): Use
phi_analyzer if no loop info is available.
* gimple-range-phi.cc: New file.
* gimple-range-phi.h: New file.
* tree-vrp.cc (execute_ranger_vrp): Utililze a phi_analyzer.
Andrew MacLeod [Wed, 24 May 2023 13:17:32 +0000 (09:17 -0400)]
Provide relation queries for a stmt.
Allow fur_list and fold_stmt to be provided a range_query rather than
always defaultsing to NULL (which becomes a global query).
Also provide a fold_relations () routine which can provide a range_trio
for an arbitrary statement using any range_query
Andrew MacLeod [Wed, 24 May 2023 13:06:26 +0000 (09:06 -0400)]
Make ssa_cache a range_query.
By providing range_of_expr as a range_query, we can fold and do other
interesting things using values from the global table. Make ranger's
knonw globals available via const_query.
Harald Anlauf [Sun, 21 May 2023 20:25:29 +0000 (22:25 +0200)]
Fortran: checking and simplification of RESHAPE intrinsic [PR103794]
gcc/fortran/ChangeLog:
PR fortran/103794
* check.cc (gfc_check_reshape): Expand constant arguments SHAPE and
ORDER before checking.
* gfortran.h (gfc_is_constant_array_expr): Add prototype.
* iresolve.cc (gfc_resolve_reshape): Expand constant argument SHAPE.
* simplify.cc (is_constant_array_expr): If array is determined to be
constant, expand small array constructors if needed.
(gfc_is_constant_array_expr): Wrapper for is_constant_array_expr.
(gfc_simplify_reshape): Fix check for insufficient elements in SOURCE
when no padding specified.
gcc/testsuite/ChangeLog:
PR fortran/103794
* gfortran.dg/reshape_10.f90: New test.
* gfortran.dg/reshape_11.f90: New test.
PR libstdc++/109949
* include/experimental/bits/simd.h (__intrinsic_type): If
__ALTIVEC__ is defined, map gnu::vector_size types to their
corresponding __vector T types without losing unsignedness of
integer types. Also prefer long long over long.
* include/experimental/bits/simd_ppc.h (_S_popcount): Cast mask
object to the expected unsigned vector type.
Roger Sayle [Wed, 24 May 2023 16:32:20 +0000 (17:32 +0100)]
PR middle-end/109840: Preserve popcount/parity type in match.pd.
PR middle-end/109840 is a regression introduced by my recent patch to
fold popcount(bswap(x)) as popcount(x). When the bswap and the popcount
have the same precision, everything works fine, but this optimization also
allowed a zero-extension between the two. The oversight is that we need
to be strict with type conversions, both to avoid accidentally changing
the argument type to popcount, and also to reflect the effects of
argument/return-value promotion in the call to bswap, so this zero extension
needs to be preserved/explicit in the optimized form.
Interestingly, match.pd should (in theory) be able to narrow calls to
popcount and parity, removing a zero-extension from its argument, but
that is an independent optimization, that needs to check IFN_ support.
Many thanks to Andrew Pinski for his help/fixes with these transformations.
2023-05-24 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
PR middle-end/109840
* match.pd <popcount optimizations>: Preserve zero-extension when
optimizing popcount((T)bswap(x)) and popcount((T)rotate(x,y)) as
popcount((T)x), so the popcount's argument keeps the same type.
<parity optimizations>: Likewise preserve extensions when
simplifying parity((T)bswap(x)) and parity((T)rotate(x,y)) as
parity((T)x), so that the parity's argument type is the same.
gcc/testsuite/ChangeLog
PR middle-end/109840
* gcc.dg/fold-parity-8.c: New test.
* gcc.dg/fold-popcount-11.c: Likewise.
Aldy Hernandez [Wed, 17 May 2023 09:29:32 +0000 (11:29 +0200)]
Provide an API for ipa_vr.
This patch encapsulates the ipa_vr internals into an API. It also
makes it type agnostic, in preparation for upcoming changes to IPA.
Interestingly, there's a 0.44% improvement to IPA-cp, which I'm sure
we'll soak up with future changes in this area :).
gcc/ChangeLog:
* ipa-cp.cc (ipa_value_range_from_jfunc): Use new ipa_vr API.
(ipcp_store_vr_results): Same.
* ipa-prop.cc (ipa_vr::ipa_vr): New.
(ipa_vr::get_vrange): New.
(ipa_vr::set_unknown): New.
(ipa_vr::streamer_read): New.
(ipa_vr::streamer_write): New.
(write_ipcp_transformation_info): Use new ipa_vr API.
(read_ipcp_transformation_info): Same.
(ipa_vr::nonzero_p): Delete.
(ipcp_update_vr): Use new ipa_vr API.
* ipa-prop.h (class ipa_vr): Provide an API and hide internals.
* ipa-sra.cc (zap_useless_ipcp_results): Use new ipa_vr API.
One of the supplied argument strings is unneccesarily long (c-sky, using
basically the same code, fixed it to a shorter length) and this fixes overflow
warnings, as GCC fails to deduce that the full 256 bytes for load_op[] are
not used at all.
gcc/ChangeLog:
* config/mcore/mcore.cc (output_inline_const) Make buffer smaller to
silence overflow warnings later on.
Uros Bizjak [Wed, 24 May 2023 14:17:55 +0000 (16:17 +0200)]
i386: Add v<any_shift:insn>v4qi3 expander
Also, move v<any_shift:insn>v8qi3 expander to a better place and enable
it with TARGET_MMX_WITH_SSE. Remove handling of V8QImode from
ix86_expand_vecop_qihi2 since all partial QI->HI vector modes expand
via ix86_expand_vecop_qihi_partial.
gcc/ChangeLog:
* config/i386/i386-expand.cc (ix86_expand_vecop_qihi2):
Remove handling of V8QImode.
* config/i386/mmx.md (v<insn>v8qi3): Move from sse.md.
Call ix86_expand_vecop_qihi_partial. Enable for TARGET_MMX_WITH_SSE.
(v<insn>v4qi3): Ditto.
* config/i386/sse.md (v<insn>v8qi3): Remove.
gcc/testsuite/ChangeLog:
* gcc.target/i386/vect-shiftv4qi.c (dg-options):
Remove -ftree-vectorize.
* gcc.target/i386/vect-shiftv8qi.c (dg-options): Ditto.
* gcc.target/i386/vect-vshiftv4qi.c: New test.
* gcc.target/i386/vect-vshiftv8qi.c: New test.
Richard Biener [Wed, 24 May 2023 08:07:36 +0000 (10:07 +0200)]
target/109944 - avoid STLF fail for V16QImode CTOR expansion
The following dispatches to V2DImode CTOR expansion instead of
using sets of (subreg:DI (reg:V16QI 146) [08]) which causes
LRA to spill DImode and reload V16QImode. The same applies for
V8QImode or V4HImode construction from SImode parts which happens
during 32bit libgcc build.
PR target/109944
* config/i386/i386-expand.cc (ix86_expand_vector_init_general):
Perform final vector composition using
ix86_expand_vector_init_general instead of setting
the highpart and lowpart which causes spilling.
* gcc.target/i386/pr109944-1.c: New testcase.
* gcc.target/i386/pr109944-2.c: Likewise.
Andrew MacLeod [Tue, 23 May 2023 19:20:56 +0000 (15:20 -0400)]
Use negative values to reflect always_current in the temporal cache.
Instead of using 0, use negative timestamps to reflect always_current state.
If the value doesn't change, keep the timestamp rather than creating a new
one and invalidating any dependencies.
PR tree-optimization/109695
* gimple-range-cache.cc (temporal_cache::temporal_value): Return
a positive int.
(temporal_cache::current_p): Check always_current method.
(temporal_cache::set_always_current): Add param and set value
appropriately.
(temporal_cache::always_current_p): New.
(ranger_cache::get_global_range): Adjust.
(ranger_cache::set_global_range): set always current first.
Richard Biener [Wed, 24 May 2023 10:36:28 +0000 (12:36 +0200)]
tree-optimization/109849 - fix fallout of PRE hoisting change
The PR109849 fix made us no longer hoist some memory loads because
of the expression set intersection. We can still avoid to compute
the union by simply taking the first sets expressions and leave
the pruning of expressions with values not suitable for hoisting
to sorted_array_from_bitmap_set.
PR tree-optimization/109849
* tree-ssa-pre.cc (do_hoist_insertion): Do not intersect
expressions but take the first sets.
PR libstdc++/109261
* include/experimental/bits/simd.h (__intrinsic_type):
Specialize __intrinsic_type<double, 8> and
__intrinsic_type<double, 16> in any case, but provide the member
type only with __aarch64__.
PR libstdc++/109261
* include/experimental/bits/simd_neon.h (_S_reduce): Add
constexpr and make NEON implementation conditional on
not __builtin_is_constant_evaluated.
Gaius Mulley [Wed, 24 May 2023 10:14:07 +0000 (11:14 +0100)]
PR modula2/109952 Inconsistent HIGH values with 'ARRAY OF CHAR'
This patch fixes the case when a single character constant literal is
passed as a string actual parameter to an ARRAY OF CHAR formal parameter.
To be consistent a single character is promoted to a string and nul
terminated (and its high value is 1). Previously a single character
string would not be nul terminated and the high value was 0.
The documentation now includes a section describing the expected behavior
and included in this patch is some regression test code matching the
table inside the documentation.
gcc/ChangeLog:
PR modula2/109952
* doc/gm2.texi (High procedure function): New node.
(Using): New menu entry for High procedure function.
gcc/m2/ChangeLog:
PR modula2/109952
* Make-maintainer.in: Change header to include emacs file mode.
* gm2-compiler/M2GenGCC.mod (BuildHighFromChar): Check whether
operand is a constant string and is nul terminated then return one.
* gm2-compiler/PCSymBuild.mod (WalkFunction): Add default return
TRUE. Static analysis missing return path fix.
* gm2-libs/IO.mod (Init): Rewrite to help static analysis.
* target-independent/m2/gm2-libs.texi: Rebuild.
gcc/testsuite/ChangeLog:
PR modula2/109952
* gm2/pim/run/pass/hightests.mod: New test.
early-remat: Resync with new DF postorders [PR109940]
When I wrote early-remat, the DF_FORWARD block order was a postorder
of a reverse/backward walk (i.e. of the inverted cfg), rather than a
reverse postorder of a forward walk. A postorder of a backward walk
lacked the important property that dominators come before the blocks
they dominate; instead it ensures that postdominators come after
the blocks that they postdominate.
The DF_BACKWARD block order was similarly a postorder of a forward
walk. Since early-remat wanted a standard postorder and reverse
postorder with normal dominator properties, it used the DF_BACKWARD
order instead of the DF_FORWARD order.
g:53dddbfeb213ac4ec39f fixed the DF orders so that DF_FORWARD was
an RPO of a forward walk and so that DF_BACKWARD was an RPO of a
backward walk. This meant that iterating backwards over the
DF_BACKWARD order had the exact problem that the original DF_FORWARD
order had, triggering a flurry of ICEs for SVE.
This fixes the build with SVE enabled. It also fixes an ICE
in g++.target/aarch64/sve/pr99766.C with normal builds. I've
included the test from the PR as well, for extra coverage.
gcc/
PR rtl-optimization/109940
* early-remat.cc (postorder_index): Rename to...
(rpo_index): ...this.
(compare_candidates): Sort by decreasing rpo_index rather than
increasing postorder_index.
(early_remat::sort_candidates): Calculate the forward RPO from
DF_FORWARD.
(early_remat::local_phase): Follow forward RPO using DF_FORWARD,
rather than DF_BACKWARD in reverse.
gcc/testsuite/
* gcc.dg/torture/pr109940.c: New test.
Kyrylo Tkachov [Wed, 24 May 2023 08:33:04 +0000 (09:33 +0100)]
arm: PR target/109939 Correct signedness of return type of __ssat intrinsics
As the PR says we shouldn't be using qualifier_unsigned for the return type of the __ssat intrinsics.
UNSIGNED_SAT_BINOP_UNSIGNED_IMM_QUALIFIERS already exists for that.
This was just a thinko.
This patch fixes this and the warning with -Wconversion goes away.
Bootstrapped and tested on arm-none-linux-gnueabihf.
gcc/ChangeLog:
PR target/109939
* config/arm/arm-builtins.cc (SAT_BINOP_UNSIGNED_IMM_QUALIFIERS): Use
qualifier_none for the return operand.
gcc/testsuite/ChangeLog:
PR target/109939
* gcc.target/arm/pr109939.c: New test.
Juzhe-Zhong [Wed, 24 May 2023 07:31:46 +0000 (15:31 +0800)]
RISC-V: Add RVV mask logic auto-vectorization
This patch is adding mask logic auto-vectorization, define the pattern
as "define_insn_and_split" to allow combine PASS easily combine series
instructions.
For example:
combine vmxor.mm + vmnot.m into vmxnor.mm
Alexandre Oliva [Wed, 24 May 2023 06:07:44 +0000 (03:07 -0300)]
[testsuite] [i386] enable sse2 for signbit-2.c
The expected results for signbit-2 only arise on x86 with avx512f
disabled and sse2 enabled. The patch already disables avx512f
explicitly, but it fails to enable sse2.
Alexandre Oliva [Wed, 24 May 2023 06:07:41 +0000 (03:07 -0300)]
Check for sysconf decl on vxworks
The sysconf function is only available in rtp mode on vxworks. In
kernel mode, it is not even declared, but the feature test macro in
the testsuite doesn't notice its absence because it's a link test, and
vxworks kernel mode uses partial linking.
This patch introduces an alternate test on vxworks targets to check
for a declaration and for an often-used sysconf parameter.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_effective_target_sysconf):
Check for declaration and _SC_PAGESIZE on vxworks.
Kewen Lin [Wed, 24 May 2023 05:05:01 +0000 (00:05 -0500)]
vect: Enhance cost evaluation in vect_transform_slp_perm_load_1
Following Richi's suggestion in [1], I'm working on deferring
cost evaluation next to the transformation, this patch is
to enhance function vect_transform_slp_perm_load_1 which
could under-cost for vector permutation, since the costing
doesn't try to consider nvectors_per_build, it's inconsistent
with the transformation part.
Basically it changes the below
if (index == count)
{
if (!noop_p)
{
// A ...
// ++*n_perms;
if (!analyze_only)
{
// B1 ...
// B2 ...
for ...
// B3 building VEC_PERM_EXPR
}
}
else if (!analyze_only)
{
// no B2 since no any further uses here.
for ...
// B4 building nothing
}
// B5 ...
}
to:
if (index == count)
{
if (!noop_p)
{
// A ...
if (!analyze_only)
// B1 ...
// B2 ... (trivial computations during analyze_only or not)
for ...
{
// now n_perms is consistent with building VEC_PERM_EXPR
// ++*n_perms;
if (analyze_only)
continue;
// B3 building VEC_PERM_EXPR
}
}
else if (!analyze_only)
{
// no B2 since no any further uses here.
for ...
// B4 building nothing
}
// B5 ...
}
Juzhe-Zhong [Wed, 24 May 2023 03:37:01 +0000 (11:37 +0800)]
RISC-V: Add RVV comparison autovectorization
This patch enable RVV auto-vectorization including floating-point
unorder and order comparison.
The testcases are leveraged from Richard. So include Richard as co-author.
And this patch is the prerequisite patch for my current middle-end work.
Without this patch, I can't support len_mask_xxx middle-end pattern
since the mask is generated by comparison.
For example,
for (int i...; i < n.)
if (cond[i])
a[i] = b[i]
We need len_mask_load/len_mask_store for such code and I am gonna
support them in the middle-end after this patch is merged.
Both integer && floating (order and unorder) are tested.
built && regression passed.
Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai> Co-Authored-By: Richard Sandiford <richard.sandiford@arm.com>
gcc/ChangeLog:
* config/riscv/autovec.md (@vcond_mask_<mode><vm>): New pattern.
(vec_cmp<mode><vm>): New pattern.
(vec_cmpu<mode><vm>): New pattern.
(vcond<V:mode><VI:mode>): New pattern.
(vcondu<V:mode><VI:mode>): New pattern.
* config/riscv/riscv-protos.h (enum insn_type): Add new enum.
(emit_vlmax_merge_insn): New function.
(emit_vlmax_cmp_insn): Ditto.
(emit_vlmax_cmp_mu_insn): Ditto.
(expand_vec_cmp): Ditto.
(expand_vec_cmp_float): Ditto.
(expand_vcond): Ditto.
* config/riscv/riscv-v.cc (emit_vlmax_merge_insn): Ditto.
(emit_vlmax_cmp_insn): Ditto.
(emit_vlmax_cmp_mu_insn): Ditto.
(get_cmp_insn_code): Ditto.
(expand_vec_cmp): Ditto.
(expand_vec_cmp_float): Ditto.
(expand_vcond): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/rvv.exp:
* gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: New test.
* gcc.target/riscv/rvv/autovec/cmp/vcond-2.c: New test.
* gcc.target/riscv/rvv/autovec/cmp/vcond-3.c: New test.
* gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: New test.
* gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: New test.
Pan Li [Thu, 18 May 2023 06:21:30 +0000 (14:21 +0800)]
RISC-V: Support RVV VREINTERPRET from vbool*_t to vuint*m1_t
This patch support the RVV VREINTERPRET from the vbool*_t to the
vuint*m1_t. Aka:
vuint*m1_t __riscv_vreinterpret_x_x(vbool*_t);
These APIs help the users to convert vector the vbool*_t to the LMUL=1
unsigned integer vint*_t. According to the RVV intrinsic SPEC as below,
the reinterpret intrinsics only change the types of the underlying contents.
For example, given below code.
vuint8m1_t test_vreinterpret_v_b1_vuint8m1 (vbool1_t src) {
return __riscv_vreinterpret_v_b1_u8m1 (src);
}
It will generate the assembly code similar as below:
vsetvli a5,zero,e8,m8,ta,ma
vlm.v v1,0(a1)
vs1r.v v1,0(a0)
ret
Please NOTE the test files doesn't cover all the possible combinations
of the intrinsic APIs introduced by this PATCH due to too many.
This is the last PATCH for the reinterpret between the signed/unsigned
and the bool vector types.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/genrvv-type-indexer.cc (main): Add
unsigned_eew*_lmul1_interpret for indexer.
* config/riscv/riscv-vector-builtins-functions.def (vreinterpret):
Register vuint*m1_t interpret function.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS):
New macro for vuint8m1_t.
(DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
(vbool1_t): Add to unsigned_eew*_interpret_ops.
(vbool2_t): Likewise.
(vbool4_t): Likewise.
(vbool8_t): Likewise.
(vbool16_t): Likewise.
(vbool32_t): Likewise.
(vbool64_t): Likewise.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS):
New macro for vuint*m1_t.
(DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
(required_extensions_p): Add vuint*m1_t interpret case.
* config/riscv/riscv-vector-builtins.def (unsigned_eew8_lmul1_interpret):
Add vuint*m1_t interpret to base type.
(unsigned_eew16_lmul1_interpret): Likewise.
(unsigned_eew32_lmul1_interpret): Likewise.
(unsigned_eew64_lmul1_interpret): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c:
Enrich test cases.
Pan Li [Thu, 18 May 2023 02:46:38 +0000 (10:46 +0800)]
RISC-V: Support RVV VREINTERPRET from vbool*_t to vint*m1_t
This patch support the RVV VREINTERPRET from the vbool*_t to the
vint*m1_t. Aka:
vint*m1_t __riscv_vreinterpret_x_x(vbool*_t);
These APIs help the users to convert vector the vbool*_t to the LMUL=1
signed integer vint*_t. According to the RVV intrinsic SPEC as below,
the reinterpret intrinsics only change the types of the underlying contents.
For example, given below code.
vint8m1_t test_vreinterpret_v_b1_vint8m1 (vbool1_t src) {
return __riscv_vreinterpret_v_b1_i8m1 (src);
}
It will generate the assembly code similar as below:
vsetvli a5,zero,e8,m8,ta,ma
vlm.v v1,0(a1)
vs1r.v v1,0(a0)
ret
Please NOTE the test files doesn't cover all the possible combinations
of the intrinsic APIs introduced by this PATCH due to too many.
The reinterpret from vbool*_t to vuint*m1_t with lmul=1 will be coverred
in another PATCH.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/genrvv-type-indexer.cc (EEW_SIZE_LIST): New macro
for the eew size list.
(LMUL1_LOG2): New macro for the log2 value of lmul=1.
(main): Add signed_eew*_lmul1_interpret for indexer.
* config/riscv/riscv-vector-builtins-functions.def (vreinterpret):
Register vint*m1_t interpret function.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS):
New macro for vint8m1_t.
(DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
(vbool1_t): Add to signed_eew*_interpret_ops.
(vbool2_t): Likewise.
(vbool4_t): Likewise.
(vbool8_t): Likewise.
(vbool16_t): Likewise.
(vbool32_t): Likewise.
(vbool64_t): Likewise.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS):
New macro for vint*m1_t.
(DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
(required_extensions_p): Add vint8m1_t interpret case.
* config/riscv/riscv-vector-builtins.def (signed_eew8_lmul1_interpret):
Add vint*m1_t interpret to base type.
(signed_eew16_lmul1_interpret): Likewise.
(signed_eew32_lmul1_interpret): Likewise.
(signed_eew64_lmul1_interpret): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c:
Enrich the test cases.
git://gcc.gnu.org / gcc.git / log