read-rtl: Fix infinite loop while parsing [...]

read_rtx_operand would spin endlessly for:

   (unspec [(...))] UNSPEC_FOO)

because read_nested_rtx does nothing if the next character is not '('.

gcc/
* read-rtl.cc (read_rtx_operand): Avoid spinning endlessly for
invalid [...] operands.

openmp: Mention C attribute syntax in documentation

This patch mentions the C attribute syntax support in the libgomp documentation.

2023-11-05  Jakub Jelinek  <jakub@redhat.com>

* libgomp.texi (Enabling OpenMP): Adjust wording for attribute syntax
supported also in C.

openmp: Adjust handling of __has_attribute (omp::directive)/sequence and add omp::decl

I forgot to tweak c_common_has_attribute for the C++ omp::decl addition and now
also for the C omp::{directive,sequence,decl} addition.

2023-11-05  Jakub Jelinek  <jakub@redhat.com>

* c-lex.cc (c_common_has_attribute): Return 1 for omp::directive
and omp::sequence with -fopenmp or -fopenmp-simd also for C, not
just for C++.  Return 1 for omp::decl with -fopenmp or -fopenmp-simd
for both C and C++.

* c-c++-common/gomp/attrs-1.c: Adjust for omp::directive and
omp::sequence being supported also in C and add tests for omp::decl.
* c-c++-common/gomp/attrs-2.c: Likewise.
* c-c++-common/gomp/attrs-3.c: Add tests for omp::decl.

aarch64: Rework aarch64_modes_tieable_p [PR112105]

On AArch64, can_change_mode_class and modes_tieable_p are
mostly answering the same questions:

(a) Do two modes have the same layout for the bytes that are
    common to both modes?

(b) Do all valid subregs involving the two modes behave as
    GCC would expect?

(c) Is there at least one register that can hold both modes?

These questions involve no class-dependent tests, and the relationship
is symmetrical.  This means we can do most of the checks in a common
subroutine.

can_change_mode_class is the hook that matters for correctness,
while modes_tieable_p is more for optimisation.  It was therefore
can_change_mode_class that had the more accurate tests.
modes_tieable_p was looser in some ways (e.g. it missed some
big-endian tests) and overly strict in others (it didn't allow
ties between a vector structure mode and the mode of a single lane).
The overly strict part caused a missed combination in the testcase.

I think the can_change_mode_class logic also needed some tweaks,
as described in the changelog.

gcc/
PR target/112105
* config/aarch64/aarch64.cc (aarch64_modes_compatible_p): New
function, with the core logic extracted from...
(aarch64_can_change_mode_class): ...here.  Extend the previous rules
to allow changes between partial SVE modes and other modes if
the other mode is no bigger than an element, and if no other rule
prevents it.  Use the aarch64_modes_tieable_p handling of
partial Advanced SIMD structure modes.
(aarch64_modes_tieable_p): Use aarch64_modes_compatible_p.
Allow all vector mode ties that it allows.

gcc/testsuite/
PR target/112105
* gcc.target/aarch64/pr112105.c: New test.
* gcc.target/aarch64/sve/pcs/struct_3_128.c: Expect a 32-bit spill
rather than a 16-bit spill.

RISC-V: Support FP rint to i/l/ll diff size autovec

This patch would like to support the FP below API auto vectorization
with different type size

+---------+-----------+----------+
| API     | RV64      | RV32     |
+---------+-----------+----------+
| irint   | DF => SI  | DF => SI |
| irintf  | -         | -        |
| lrint   | -         | DF => SI |
| lrintf  | SF => DI  | -        |
| llrint  | -         | -        |
| llrintf | SF => DI  | SF => DI |
+---------+-----------+----------+

Given below code:
void
test_lrintf (long *out, float *in, unsigned count)
{
  for (unsigned i = 0; i < count; i++)
    out[i] = __builtin_lrintf (in[i]);
}

Before this patch:
test_lrintf:
  beq     a2,zero,.L8
  slli    a5,a2,32
  srli    a2,a5,30
  add     a4,a1,a2
.L3:
  flw     fa5,0(a1)
  addi    a1,a1,4
  addi    a0,a0,8
  fcvt.l.s a5,fa5,dyn
  sd      a5,-8(a0)
  bne     a1,a4,.L3

After this patch:
test_lrintf:
  beq     a2,zero,.L8
  slli    a2,a2,32
  srli    a2,a2,32
.L3:
  vsetvli a5,a2,e32,mf2,ta,ma
  vle32.v v2,0(a1)
  slli    a3,a5,2
  slli    a4,a5,3
  vfwcvt.x.f.v    v1,v2
  sub     a2,a2,a5
  vse64.v v1,0(a0)
  add     a1,a1,a3
  add     a0,a0,a4
  bne     a2,zero,.L3

Unfortunately, the HF mode is not include due to it requires
additional middle-end support from internal-fun.def.

gcc/ChangeLog:

* config/riscv/autovec.md: Remove the size check of lrint.
* config/riscv/riscv-v.cc (emit_vec_narrow_cvt_x_f): New help
emit func impl.
(emit_vec_widden_cvt_x_f): New help emit func impl.
(emit_vec_rounding_to_integer): New func impl to emit the
rounding from FP to integer.
(expand_vec_lrint): Leverage emit_vec_rounding_to_integer.
* config/riscv/vector.md: Take V_VLSF for vfncvt.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/unop/math-irint-run-0.c:
* gcc.target/riscv/rvv/autovec/unop/math-irint-1.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-irintf-run-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-llrintf-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-llrintf-run-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-lrint-rv32-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-lrint-rv32-run-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-lrintf-rv64-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-lrintf-rv64-run-0.c: New test.
* gcc.target/riscv/rvv/autovec/vls/math-irint-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/math-llrintf-0.c: New test.
* gcc.target/riscv/rvv/autovec/vls/math-lrint-rv32-0.c: New test.
* gcc.target/riscv/rvv/autovec/vls/math-lrintf-rv64-0.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Fix bug of vlds attribute

This issue is noticed when support strided load/store auto-vectorization.
Commit it as it is obvious.

gcc/ChangeLog:

* config/riscv/vector.md: Fix bug.

Daily bump.

diagnostics: fix gcc-urlifier.cc bootstrap failure [PR112379]

Without the change `./configure --enable-checking=release` bootstrap
fails as:

    gcc/gcc-urlifier.cc:100:1: error: 'get_url_suffix_for_quoted_text()'
        defined but not used [-Werror=unused-function]

This happens because the helper is used only in `ASSERT` macros which
don't always get expanded to executable code.

The fix marks helper function with `ATTRIBUTE_UNUSED`.

gcc/
PR bootstrap/112379
* gcc-urlifier.cc (get_url_suffix_for_quoted_text): Mark as
ATTRIBUTE_UNUSED.

libstdc++: Remove redundant partial specialization in _Nth_type

libstdc++-v3/ChangeLog:

* include/bits/utility.h (_Nth_type): Remove redundant partial
specialization.

libstdc++: Use strerror_r in std::generic_category()::message(int) [PR110133]

Use strerror_r instead of strerror when available, due to the latter not
being thread-safe. This is complicated by Glibc providing a GNU-specific
strerror_r which is not compatible with POSIX strerror_r, so we need to
dispatch on the return type.

We can use the recently-added std::string::__resize_and_overwrite to
write directly into the string buffer when possible. Because we estimate
the initial buffer size we might end up with excess capacity in the
returned std::string. We can slightly tweak the std::system_error
constructors to make use of that excess capacity, so that in some cases
we require fewer allocations to construct the std::system_error::what()
string.

libstdc++-v3/ChangeLog:

PR libstdc++/110133
* include/std/system_error (system_error::system_error): Group
arguments so that concatenation can reuse rvalue's capacity.
* src/c++11/system_error.cc (strerror_string): New function.
[_GLIBCXX_HAVE_STRERROR_R] (use_strerror_result): New functions.
(generic_error_category::message): Use strerror_string.
(system_error_category::message): Likewise.

libstdc++: Replace "_N" in examples of naming conventions

The name "_N" is listed as a reserved name on Solaris, so we shouldn't
use it as an example of our naming conventions.

libstdc++-v3/ChangeLog:

* doc/xml/manual/appendix_contributing.xml: Replace example that
uses a BADNAME.
* doc/html/manual/source_code_style.html: Regenerate.

openmp: Add omp::decl support for C2X

This patch adds omp::decl support which has been added recently for
C++ also to C.

2023-11-04  Jakub Jelinek  <jakub@redhat.com>

* c-parser.h (c_maybe_parse_omp_decl): Declare.
* c-parser.cc (struct c_parser): Add in_omp_decl_attribute member.
(c_parser_std_attribute): Uncoment omp::decl handling.
(c_parser_omp_var_list_parens): If parser->in_omp_decl_attribute
don't expect any arguments, instead create clause or TREE_LIST for
that decl.
(c_maybe_parse_omp_decl): New function.
(c_parser_omp_declare_target): If parser->in_omp_decl_attribute and
first token isn't name or comma invoke c_parser_omp_var_list_parens.
* c-decl.cc (c_decl_attributes): Uncomment omp::decl handling and
use *node rather than non-existing *decl.

* gcc.dg/gomp/attrs-19.c: New test.
* gcc.dg/gomp/attrs-20.c: New test.
* gcc.dg/gomp/attrs-21.c: New test.

openmp: Add support for omp::directive and omp::sequence attributes in C2X

The following patch adds support for attribute syntax which we have in C++11
and above since GCC 12 also for C, where OpenMP standard is going to add it
in OpenMP 6.0.

2023-11-04  Jakub Jelinek  <jakub@redhat.com>

gcc/c/
* c-tree.def: New file.
* c-tree.h (struct c_tree_token_vec): Forward declare.
(c_tree_size): Declare.
* c-lang.h (struct c_omp_declare_target_attr): Add attr_syntax member.
(struct c_omp_begin_assumes_data): New type.
(current_omp_begin_assumes): Change type from int to
vec<c_omp_begin_assumes_data, va_gc> *.
* c-lang.cc: Include c-family/c-pragma.h and c-parser.h.
* c-parser.h (struct c_tree_token_vec_struct): New type.
(C_TOKEN_VEC_TOKENS): New macro.
* c-parser.cc (struct c_parser): Add omp_attrs_forbidden_p and
in_omp_attribute_pragma members.
(c_parser_skip_until_found): Handle CPP_PRAGMA_EOL when
parser->in_omp_attribute_pragma.
(c_parser_skip_to_pragma_eol): Likewise.
(c_parser_translation_unit): Adjust for current_omp_begin_assumes
being a vector rather than counter.
(c_parser_declaration_or_fndef): Handle omp::directive and
omp::sequence attributes on attribute declaration and declare simd
or declare variant directives in those on function declarations.
(c_parser_check_balanced_raw_token_sequence): Forward declare.
(c_parser_omp_directive_args, c_parser_omp_sequence_args): New
functions.
(c_parser_std_attribute): Handle omp::directive and omp::sequence
attributes.
(struct c_omp_attribute_data): New type.
(c_parser_handle_statement_omp_attributes,
c_parser_handle_directive_omp_attributes): New functions.
(c_parser_compound_statement_nostart): Handle omp::directive and
omp::sequence attributes on statements.  Formatting fix.
(c_parser_all_labels): Handle omp::directive and omp::sequence
attributes on statements.
(c_parser_statement): Clear parser->omp_attrs_forbidden_p.
(c_parser_omp_variable_list): Handle parser->tokens
!= &parser->tokens_buf[0] by saving/restoring it.
(c_parser_omp_structured_block): Set parser->omp_attrs_forbidden_p.
(c_parser_omp_section_scan): New function.
(c_parser_omp_structured_block_sequence, c_parser_omp_sections_scope):
Use it.
(c_parser_omp_parallel): Set parser->omp_attrs_forbidden_p.
(c_parser_omp_task): Likewise.
(c_parser_omp_declare_simd): Handle function declaration after
std attributes.
(c_finish_omp_declare_simd): Don't assert all kinds are the same.
(c_parser_omp_declare_target): Also push attr_syntax flag.
(c_parser_omp_begin): Likewise.  Adjust for current_omp_begin_assumes
type change.
(c_parser_omp_end): Adjust for current_omp_begin_assumes type
change.  Diagnose mixing of attribute vs. pragma syntax on end assumes
or end declare target.
(c_parser_omp_declare_reduction): Handle parser->tokens
!= &parser->tokens_buf[0] by saving/restoring it.
* c-decl.cc: Include c-parser.h.
(current_omp_begin_assumes): Change type from int to
vec<c_omp_begin_assumes_data, va_gc> *.
(struct c_tree_token_vec): New type.  Add static assertions
for sizeof and offsetof.
(union lang_tree_node): Add c_token_vec member and adjust GTY
desc for it.
(c_tree_size): New function.
(c_decl_attributes): Diagnose invalid omp::directive attribute
uses.
* c-objc-common.h (LANG_HOOKS_TREE_SIZE): Redefine.
gcc/cp/
* parser.h (struct cp_parser): Adjust comment on omp_attrs_forbidden_p
member.
* parser.cc (cp_parser_omp_section_scan): Allow __directive__ spelling.
gcc/objc/
* objc-act.h (objc_common_tree_size): Remove.
* objc-act.cc (objc_common_tree_size): Remove.
* objc-lang.cc (LANG_HOOKS_TREE_SIZE): Remove.
gcc/testsuite/
* gcc.dg/gomp/attrs-1.c: New test.
* gcc.dg/gomp/attrs-2.c: New test.
* gcc.dg/gomp/attrs-3.c: New test.
* gcc.dg/gomp/attrs-4.c: New test.
* gcc.dg/gomp/attrs-5.c: New test.
* gcc.dg/gomp/attrs-6.c: New test.
* gcc.dg/gomp/attrs-7.c: New test.
* gcc.dg/gomp/attrs-8.c: New test.
* gcc.dg/gomp/attrs-9.c: New test.
* gcc.dg/gomp/attrs-10.c: New test.
* gcc.dg/gomp/attrs-11.c: New test.
* gcc.dg/gomp/attrs-12.c: New test.
* gcc.dg/gomp/attrs-13.c: New test.
* gcc.dg/gomp/attrs-14.c: New test.
* gcc.dg/gomp/attrs-15.c: New test.
* gcc.dg/gomp/attrs-16.c: New test.
* gcc.dg/gomp/attrs-17.c: New test.
* gcc.dg/gomp/attrs-18.c: New test.
* g++.dg/gomp/attrs-2.C: Enable for c++11 rather than just
c++17.  Avoid using omp : syntax for c++11, c++14 and c.

RISC-V: Remove HF modes of FP to INT rounding autovec

The [i|l|ll][rint|round|ceil|floor] internal functions are
defined as DEF_INTERNAL_FLT_FN instead of DEF_INTERNAL_FLT_FLOATN_FN.
Then the *f16 (N=16 of FLOATN) format of these functions are not
available when try to get the ifn from the given cfn in the
vectorizable_call. Aka:

BUILT_IN_LRINTF16 => IFN_LAST (should be IFN_LRINT here)
BUILT_IN_RINTF16 => IFN_RINT

It is better to remove FP16 related modes until the additional
middle-end support is ready. This patch would like to clean the FP16
modes with some comments.

gcc/ChangeLog:

* config/riscv/vector-iterators.md: Remove HF modes.

Signed-off-by: Pan Li <pan2.li@intel.com>

diagnostics: add automatic URL-ification within messages

In r10-3781-gd26082357676a3 GCC's pretty-print framework gained
the ability to emit embedding URLs via escape sequences
for marking up text output..

In r10-3783-gb4c7ca2ef3915a GCC started using this for the
[-Wname-of-option] emitted at the end of each diagnostic so that it
becomes a hyperlink to the documentation for that option on the GCC
website.

This makes it much more convenient for the user to locate pertinent
documentation when a diagnostic is emitted.

The above involved special-casing in one specific place, but there is
plenty of quoted text throughout GCC's diagnostic messages that could
usefully have a documentation URL: references to options, pragmas, etc

This patch adds a new optional "urlifier" parameter to pp_format.
The idea is that a urlifier object has responsibility for mapping from
quoted strings in diagnostic messages to URLs, and pp_format has the
ability to automatically add URL escapes for strings that the urlifier
gives it URLs for.

For example, given the format string:

  "%<#pragma pack%> has no effect with %<-fpack-struct%>"

with this patch GCC is able to automatically linkify the "#pragma pack"
text to
  https://gcc.gnu.org/onlinedocs/gcc/Structure-Layout-Pragmas.html
and the "-fpack-struct" text to:
  https://gcc.gnu.org/onlinedocs/gcc/Code-Gen-Options.html#index-fpack-struct

and we don't have to modify the format string itself.

This is only done for the pp_format within
diagnostic_context::report_diagnostic i.e. just for the primary message
in each diagnostics, and not for other places within GCC that use pp
format internally.

"urlifier" is an abstract base class, with a GCC-specific subclass
implementing the logic for generating URLs into GCC's HTML
documentation via binary search in a data table.  This patch implements
the gcc_urlifier with a small table generated by hand; the data table in
this patch only covers various pragmas and the option referenced by the
above pragma message.

I have a followup patch that scripts the creation of this data by
directly scraping the output of "make html", thus automating all this,
and (I hope) minimizing the work of ensuring that documentation URLs
emitted by GCC match the generated documentation.

gcc/ChangeLog:
* Makefile.in (GCC_OBJS): Add gcc-urlifier.o.
(OBJS): Likewise.

gcc/c-family/ChangeLog:
* c-pragma.cc:: (handle_pragma_push_options): Fix missing "GCC" in
name of pragma in "junk" message.
(handle_pragma_pop_options): Likewise.

gcc/ChangeLog:
* diagnostic.cc: Include "pretty-print-urlifier.h".
(diagnostic_context::initialize): Initialize m_urlifier.
(diagnostic_context::finish): Clean up m_urlifier
(diagnostic_report::diagnostic): m_urlifier to pp_format.
* diagnostic.h (diagnostic_context::m_urlifier): New field.
* gcc-urlifier.cc: New file.
* gcc-urlifier.def: New file.
* gcc-urlifier.h: New file.
* gcc.cc: Include "gcc-urlifier.h".
(driver::global_initializations): Initialize global_dc->m_urlifier.
* pretty-print-urlifier.h: New file.
* pretty-print.cc: Include "pretty-print-urlifier.h".
(obstack_append_string): New.
(urlify_quoted_string): New.
(pp_format): Add "urlifier" param and use it to implement optional
urlification of quoted text strings.
(pp_output_formatted_text): Make buffer a const pointer.
(selftest::pp_printf_with_urlifier): New.
(selftest::test_urlification): New.
(selftest::pretty_print_cc_tests): Call it.
* pretty-print.h (class urlifier): New forward declaration.
(pp_format): Add optional urlifier param.
* selftest-run-tests.cc (selftest::run_tests): Call
selftest::gcc_urlifier_cc_tests .
* selftest.h (selftest::gcc_urlifier_cc_tests): New decl.
* toplev.cc: Include "gcc-urlifier.h".
(general_init): Initialize global_dc->m_urlifier.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

diagnostics: convert diagnostic_context to a class

This patch:
- converts "struct diagnostic_context" to "class diagnostic_context".
- ensures all data members have an "m_" prefix, except for "printer",
  which has so many uses that renaming would be painful.
- makes most of the data members private
- converts much of the diagnostic_* functions to member functions of
  diagnostic_context, adding compatibility wrappers for users such as
  the Fortran frontend, and making as many as possible private.

No functional change intended.

gcc/ChangeLog:
* common.opt (fdiagnostics-text-art-charset=): Remove refererence
to diagnostic-text-art.h.
* coretypes.h (struct diagnostic_context): Replace forward decl
with...
(class diagnostic_context): ...this.
* diagnostic-format-json.cc: Update for changes to
diagnostic_context.
* diagnostic-format-sarif.cc: Likewise.
* diagnostic-show-locus.cc: Likewise.
* diagnostic-text-art.h: Deleted file, moving content...
(enum diagnostic_text_art_charset): ...to diagnostic.h,
(DIAGNOSTICS_TEXT_ART_CHARSET_DEFAULT): ...deleting,
(diagnostics_text_art_charset_init): ...deleting in favor of
diagnostic_context::set_text_art_charset.
* diagnostic.cc: Remove include of "diagnostic-text-art.h".
(pedantic_warning_kind): Update for field renaming.
(permissive_error_kind): Likewise.
(permissive_error_option): Likewise.
(diagnostic_initialize): Convert to...
(diagnostic_context::initialize): ...this, updating for field
renamings.
(diagnostic_color_init): Convert to...
(diagnostic_context::color_init): ...this.
(diagnostic_urls_init): Convert to...
(diagnostic_context::urls_init): ...this.
(diagnostic_initialize_input_context): Convert to...
(diagnostic_context::initialize_input_context): ...this.
(diagnostic_finish): Convert to...
(diagnostic_context::finish): ...this, updating for field
renamings.
(diagnostic_context::set_output_format): New.
(diagnostic_context::set_client_data_hooks): New.
(diagnostic_context::create_edit_context): New.
(diagnostic_converted_column): Convert to...
(diagnostic_context::converted_column): ...this.
(diagnostic_get_location_text): Update for field renaming.
(diagnostic_check_max_errors): Convert to...
(diagnostic_context::check_max_errors): ...this, updating for
field renamings.
(diagnostic_action_after_output): Convert to...
(diagnostic_context::action_after_output): ...this, updating for
field renamings.
(last_module_changed_p): Delete.
(set_last_module): Delete.
(includes_seen): Convert to...
(diagnostic_context::includes_seen_p): ...this, updating for field
renamings.
(diagnostic_report_current_module): Convert to...
(diagnostic_context::report_current_module): ...this, updating for
field renamings, and replacing uses of last_module_changed_p and
set_last_module to simple field accesses.
(diagnostic_show_any_path): Convert to...
(diagnostic_context::show_any_path): ...this.
(diagnostic_classify_diagnostic): Convert to...
(diagnostic_context::classify_diagnostic): ...this, updating for
field renamings.
(diagnostic_push_diagnostics): Convert to...
(diagnostic_context::push_diagnostics): ...this, updating for field
renamings.
(diagnostic_pop_diagnostics): Convert to...
(diagnostic_context::pop_diagnostics): ...this, updating for field
renamings.
(get_any_inlining_info): Convert to...
(diagnostic_context::get_any_inlining_info): ...this, updating for
field renamings.
(update_effective_level_from_pragmas): Convert to...
(diagnostic_context::update_effective_level_from_pragmas):
...this, updating for field renamings.
(print_any_cwe): Convert to...
(diagnostic_context::print_any_cwe): ...this.
(print_any_rules): Convert to...
(diagnostic_context::print_any_rules): ...this.
(print_option_information): Convert to...
(diagnostic_context::print_option_information): ...this, updating
for field renamings.
(diagnostic_enabled): Convert to...
(diagnostic_context::diagnostic_enabled): ...this, updating for
field renamings.
(warning_enabled_at): Convert to...
(diagnostic_context::warning_enabled_at): ...this.
(diagnostic_report_diagnostic): Convert to...
(diagnostic_context::report_diagnostic): ...this, updating for
field renamings and conversions to member functions.
(diagnostic_append_note): Update for field renaming.
(diagnostic_impl): Use diagnostic_context::report_diagnostic
directly.
(diagnostic_n_impl): Likewise.
(diagnostic_emit_diagram): Convert to...
(diagnostic_context::emit_diagram): ...this, updating for field
renamings.
(error_recursion): Convert to...
(diagnostic_context::error_recursion): ...this.
(diagnostic_text_output_format::~diagnostic_text_output_format):
Use accessor.
(diagnostics_text_art_charset_init): Convert to...
(diagnostic_context::set_text_art_charset): ...this.
(assert_location_text): Update for field renamings.
* diagnostic.h (enum diagnostic_text_art_charset): Move here from
diagnostic-text-art.h.
(struct diagnostic_context): Convert to...
(class diagnostic_context): ...this.
(diagnostic_context::ice_handler_callback_t): New typedef.
(diagnostic_context::set_locations_callback_t): New typedef.
(diagnostic_context::initialize): New decl.
(diagnostic_context::color_init): New decl.
(diagnostic_context::urls_init): New decl.
(diagnostic_context::file_cache_init): New decl.
(diagnostic_context::finish): New decl.
(diagnostic_context::set_set_locations_callback): New.
(diagnostic_context::initialize_input_context): New decl.
(diagnostic_context::warning_enabled_at): New decl.
(diagnostic_context::option_unspecified_p): New.
(diagnostic_context::report_diagnostic): New decl.
(diagnostic_context::report_current_module): New decl.
(diagnostic_context::check_max_errors): New decl.
(diagnostic_context::action_after_output): New decl.
(diagnostic_context::classify_diagnostic): New decl.
(diagnostic_context::push_diagnostics): New decl.
(diagnostic_context::pop_diagnostics): New decl.
(diagnostic_context::emit_diagram): New decl.
(diagnostic_context::set_output_format): New decl.
(diagnostic_context::set_text_art_charset): New decl.
(diagnostic_context::set_client_data_hooks): New decl.
(diagnostic_context::create_edit_context): New decl.
(diagnostic_context::set_warning_as_error_requested): New.
(diagnostic_context::set_report_bug): New.
(diagnostic_context::set_extra_output_kind): New.
(diagnostic_context::set_show_cwe): New.
(diagnostic_context::set_show_rules): New.
(diagnostic_context::set_path_format): New.
(diagnostic_context::set_show_path_depths): New.
(diagnostic_context::set_show_option_requested): New.
(diagnostic_context::set_max_errors): New.
(diagnostic_context::set_escape_format): New.
(diagnostic_context::set_ice_handler_callback): New.
(diagnostic_context::warning_as_error_requested_p): New.
(diagnostic_context::show_path_depths_p): New.
(diagnostic_context::get_path_format): New.
(diagnostic_context::get_escape_format): New.
(diagnostic_context::get_file_cache): New.
(diagnostic_context::get_edit_context): New.
(diagnostic_context::get_client_data_hooks): New.
(diagnostic_context::get_diagram_theme): New.
(diagnostic_context::converted_column): New decl.
(diagnostic_context::diagnostic_count): New.
(diagnostic_context::includes_seen_p): New decl.
(diagnostic_context::print_any_cwe): New decl.
(diagnostic_context::print_any_rules): New decl.
(diagnostic_context::print_option_information): New decl.
(diagnostic_context::show_any_path): New decl.
(diagnostic_context::error_recursion): New decl.
(diagnostic_context::diagnostic_enabled): New decl.
(diagnostic_context::get_any_inlining_info): New decl.
(diagnostic_context::update_effective_level_from_pragmas): New
decl.
(diagnostic_context::m_file_cache): Make private.
(diagnostic_context::diagnostic_count): Rename to...
(diagnostic_context::m_diagnostic_count): ...this and make
private.
(diagnostic_context::warning_as_error_requested): Rename to...
(diagnostic_context::m_warning_as_error_requested): ...this and
make private.
(diagnostic_context::n_opts): Rename to...
(diagnostic_context::m_n_opts): ...this and make private.
(diagnostic_context::classify_diagnostic): Rename to...
(diagnostic_context::m_classify_diagnostic): ...this and make
private.
(diagnostic_context::classification_history): Rename to...
(diagnostic_context::m_classification_history): ...this and make
private.
(diagnostic_context::n_classification_history): Rename to...
(diagnostic_context::m_n_classification_history): ...this and make
private.
(diagnostic_context::push_list): Rename to...
(diagnostic_context::m_push_list): ...this and make private.
(diagnostic_context::n_push): Rename to...
(diagnostic_context::m_n_push): ...this and make private.
(diagnostic_context::show_cwe): Rename to...
(diagnostic_context::m_show_cwe): ...this and make private.
(diagnostic_context::show_rules): Rename to...
(diagnostic_context::m_show_rules): ...this and make private.
(diagnostic_context::path_format): Rename to...
(diagnostic_context::m_path_format): ...this and make private.
(diagnostic_context::show_path_depths): Rename to...
(diagnostic_context::m_show_path_depths): ...this and make
private.
(diagnostic_context::show_option_requested): Rename to...
(diagnostic_context::m_show_option_requested): ...this and make
private.
(diagnostic_context::abort_on_error): Rename to...
(diagnostic_context::m_abort_on_error): ...this.
(diagnostic_context::show_column): Rename to...
(diagnostic_context::m_show_column): ...this.
(diagnostic_context::pedantic_errors): Rename to...
(diagnostic_context::m_pedantic_errors): ...this.
(diagnostic_context::permissive): Rename to...
(diagnostic_context::m_permissive): ...this.
(diagnostic_context::opt_permissive): Rename to...
(diagnostic_context::m_opt_permissive): ...this.
(diagnostic_context::fatal_errors): Rename to...
(diagnostic_context::m_fatal_errors): ...this.
(diagnostic_context::dc_inhibit_warnings): Rename to...
(diagnostic_context::m_inhibit_warnings): ...this.
(diagnostic_context::dc_warn_system_headers): Rename to...
(diagnostic_context::m_warn_system_headers): ...this.
(diagnostic_context::max_errors): Rename to...
(diagnostic_context::m_max_errors): ...this and make private.
(diagnostic_context::internal_error): Rename to...
(diagnostic_context::m_internal_error): ...this.
(diagnostic_context::option_enabled): Rename to...
(diagnostic_context::m_option_enabled): ...this.
(diagnostic_context::option_state): Rename to...
(diagnostic_context::m_option_state): ...this.
(diagnostic_context::option_name): Rename to...
(diagnostic_context::m_option_name): ...this.
(diagnostic_context::get_option_url): Rename to...
(diagnostic_context::m_get_option_url): ...this.
(diagnostic_context::print_path): Rename to...
(diagnostic_context::m_print_path): ...this.
(diagnostic_context::make_json_for_path): Rename to...
(diagnostic_context::m_make_json_for_path): ...this.
(diagnostic_context::x_data): Rename to...
(diagnostic_context::m_client_aux_data): ...this.
(diagnostic_context::last_location): Rename to...
(diagnostic_context::m_last_location): ...this.
(diagnostic_context::last_module): Rename to...
(diagnostic_context::m_last_module): ...this and make private.
(diagnostic_context::lock): Rename to...
(diagnostic_context::m_lock): ...this and make private.
(diagnostic_context::lang_mask): Rename to...
(diagnostic_context::m_lang_mask): ...this.
(diagnostic_context::inhibit_notes_p): Rename to...
(diagnostic_context::m_inhibit_notes_p): ...this.
(diagnostic_context::report_bug): Rename to...
(diagnostic_context::m_report_bug): ...this and make private.
(diagnostic_context::extra_output_kind): Rename to...
(diagnostic_context::m_extra_output_kind): ...this and make
private.
(diagnostic_context::column_unit): Rename to...
(diagnostic_context::m_column_unit): ...this and make private.
(diagnostic_context::column_origin): Rename to...
(diagnostic_context::m_column_origin): ...this and make private.
(diagnostic_context::tabstop): Rename to...
(diagnostic_context::m_tabstop): ...this and make private.
(diagnostic_context::escape_format): Rename to...
(diagnostic_context::m_escape_format): ...this and make private.
(diagnostic_context::edit_context_ptr): Rename to...
(diagnostic_context::m_edit_context_ptr): ...this and make
private.
(diagnostic_context::set_locations_cb): Rename to...
(diagnostic_context::m_set_locations_cb): ...this and make
private.
(diagnostic_context::ice_handler_cb): Rename to...
(diagnostic_context::m_ice_handler_cb): ...this and make private.
(diagnostic_context::includes_seen): Rename to...
(diagnostic_context::m_includes_seen): ...this and make private.
(diagnostic_inhibit_notes): Update for field renaming.
(diagnostic_context_auxiliary_data): Likewise.
(diagnostic_abort_on_error): Convert from macro to inline function
and update for field renaming.
(diagnostic_kind_count): Convert from macro to inline function and
use diagnostic_count accessor.
(diagnostic_report_warnings_p): Update for field renaming.
(diagnostic_initialize): Convert decl to inline function calling
into diagnostic_context.
(diagnostic_color_init): Likewise.
(diagnostic_urls_init): Likewise.
(diagnostic_urls_init): Likewise.
(diagnostic_finish): Likewise.
(diagnostic_report_current_module): Likewise.
(diagnostic_show_any_path): Delete decl.
(diagnostic_initialize_input_context): Convert decl to inline
function calling into diagnostic_context.
(diagnostic_classify_diagnostic): Likewise.
(diagnostic_push_diagnostics): Likewise.
(diagnostic_pop_diagnostics): Likewise.
(diagnostic_report_diagnostic): Likewise.
(diagnostic_action_after_output): Likewise.
(diagnostic_check_max_errors): Likewise.
(diagnostic_file_cache_fini): Delete decl.
(diagnostic_converted_column): Delete decl.
(warning_enabled_at): Convert decl to inline function calling into
diagnostic_context.
(option_unspecified_p): New.
(diagnostic_emit_diagram): Delete decl.
* gcc.cc: Remove include of "diagnostic-text-art.h".
Update for changes to diagnostic_context.
* input.cc (diagnostic_file_cache_init): Move implementation
to...
(diagnostic_context::file_cache_init): ...this new member
function.
(diagnostic_file_cache_fini): Delete.
(diagnostics_file_cache_forcibly_evict_file): Update for
m_file_cache becoming private.
(location_get_source_line): Likewise.
(get_source_file_content): Likewise.
(location_missing_trailing_newline): Likewise.
* input.h (diagnostics_file_cache_fini): Delete.
* langhooks.cc: Update for changes to diagnostic_context.
* lto-wrapper.cc: Likewise.
* opts.cc: Remove include of "diagnostic-text-art.h".
Update for changes to diagnostic_context.
* selftest-diagnostic.cc: Update for changes to
diagnostic_context.
* toplev.cc: Likewise.
* tree-diagnostic-path.cc: Likewise.
* tree-diagnostic.cc: Likewise.

gcc/ada/ChangeLog:
* gcc-interface/misc.cc: Update for changes to diagnostic_context.

gcc/analyzer/ChangeLog:
* bounds-checking.cc: Update for changes to diagnostic_context.

gcc/c-family/ChangeLog:
* c-common.cc: Update for changes to diagnostic_context.
* c-indentation.cc: Likewise.
* c-opts.cc: Likewise.
* c-warn.cc: Likewise.

gcc/cp/ChangeLog:
* call.cc: Update for changes to diagnostic_context.
* class.cc: Likewise.
* decl.cc: Likewise.
* error.cc: Likewise.
* except.cc: Likewise.
* pt.cc: Likewise.

gcc/fortran/ChangeLog:
* cpp.cc: Update for changes to diagnostic_context.
* error.cc: Likewise.
* options.cc: Likewise.

gcc/jit/ChangeLog:
* jit-playback.cc: Update for changes to diagnostic_context.
* jit-playback.h: Likewise.

gcc/testsuite/ChangeLog:
* gcc.dg/plugin/diagnostic_group_plugin.c: Update for changes to
diagnostic_context.
* gcc.dg/plugin/diagnostic_plugin_test_text_art.c: Likewise.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

Daily bump.

Reduce false positives for -Wnonnull for VLA parameters [PR98541]

This patch limits the warning about NULL arguments to VLA
parameters declared [static n].

PR c/98541

gcc/
* gimple-ssa-warn-access.cc
(pass_waccess::maybe_check_access_sizes): For VLA bounds
in parameters, only warn about null pointers with 'static'.

gcc/testsuite:
* gcc.dg/Wnonnull-4.c: Adapt test.
* gcc.dg/Wstringop-overflow-40.c: Adapt test.

Fortran: fix issue with multiple references of a procedure pointer [PR97245]

gcc/fortran/ChangeLog:

PR fortran/97245
* match.cc (gfc_match_call): If a procedure pointer has already been
resolved, do not create a new symbol in a procedure reference of
the same name shadowing the first one if it is host-associated.

gcc/testsuite/ChangeLog:

PR fortran/97245
* gfortran.dg/proc_ptr_53.f90: New test.

vect: allow using inbranch simdclones for masked loops

In a previous patch I did most of the work for this, but forgot to change the
check for number of arguments matching between call and simdclone.  This check
should accept calls without a mask to be matched against simdclones with mask
arguments.  I also added tests to verify this feature actually works.

gcc/ChangeLog:

* tree-vect-stmts.cc (vectorizable_simd_clone_call): Allow unmasked
calls to use masked simdclones.

gcc/testsuite/ChangeLog:

* gcc.dg/vect/vect-simd-clone-20.c: New file.
* gfortran.dg/simd-builtins-1.h: Adapt.
* gfortran.dg/simd-builtins-6.f90: Adapt.

diagnostics: consolidate group-handling fields in diagnostic_context

No functional change intended.

gcc/ChangeLog:
* diagnostic.cc (diagnostic_initialize): Update for consolidation
of group-based fields.
(diagnostic_report_diagnostic): Likewise.
(diagnostic_context::begin_group): New, based on body of
auto_diagnostic_group's ctor.
(diagnostic_context::end_group): New, based on body of
auto_diagnostic_group's dtor.
(auto_diagnostic_group::auto_diagnostic_group): Convert to a call
to begin_group.
(auto_diagnostic_group::~auto_diagnostic_group): Convert to a call
to end_group.
* diagnostic.h (diagnostic_context::begin_group): New decl.
(diagnostic_context::end_group): New decl.
(diagnostic_context::diagnostic_group_nesting_depth): Rename to...
(diagnostic_context::m_diagnostic_groups.m_nesting_depth):
...this.
(diagnostic_context::diagnostic_group_emission_count): Rename
to...
(diagnostic_context::m_diagnostic_groups::m_emission_count):
...this.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

Fortran: passing of allocatable/pointer arguments to OPTIONAL+VALUE [PR92887]

gcc/fortran/ChangeLog:

PR fortran/92887
* trans-expr.cc (conv_cond_temp): Helper function for creation of a
conditional temporary.
(gfc_conv_procedure_call): Handle passing of allocatable or pointer
actual argument to dummy with OPTIONAL + VALUE attribute.  Actual
arguments that are not allocated or associated are treated as not
present.

gcc/testsuite/ChangeLog:

PR fortran/92887
* gfortran.dg/value_optional_1.f90: New test.

Adjust operators equal and not_equal to check bitmasks against constants

Check to see if a comparison to a constant can be determined to always
be not-equal based on the bitmask.

PR tree-optimization/111766
gcc/
* range-op.cc (operator_equal::fold_range): Check constants
against the bitmask.
(operator_not_equal::fold_range): Ditto.
* value-range.h (irange_bitmask::member_p): New.

gcc/testsuite/
* gcc.dg/pr111766.c: New.

Remove simple ranges from trailing zero bitmasks.

During the intersection operation, it can be helpful to remove any
low-end ranges when the bitmask has trailing zeros.  This prevents
obviously incorrect ranges from appearing without requiring a bitmask
check.

* value-range.cc (irange_bitmask::adjust_range): New.
(irange::intersect_bitmask): Call adjust_range.
* value-range.h (irange_bitmask::adjust_range): New prototype.

i386: Handle multiple address register classes

The patch generalizes address register class handling to allow multiple
register classes.  For APX EGPR targets, some instructions do not support
GPR32 registers, so it is necessary to limit address register set to
avoid them.  The same situation happens for instructions with high registers,
where REX registers can not be used in the address, so the existing
infrastructure can be adapted to also handle this case.

The patch is mostly a mechanical rename of "gpr32" attribute to "addr" and
introduces no functional changes, although it fixes a couple of inconsistent
attribute values in passing.

A follow-up patch will use the above infrastructure to limit address register
class to legacy registers for instructions with high registers.

gcc/ChangeLog:

* config/i386/i386.cc (ix86_memory_address_use_extended_reg_class_p):
Rename to ...
(ix86_memory_address_reg_class): ... this.  Generalize address
register class handling to allow multiple address register classes.
Return maximal class for unrecognized instructions.  Improve comments.
(ix86_insn_base_reg_class): Rewrite to handle
multiple address register classes.
(ix86_regno_ok_for_insn_base_p): Ditto.
(ix86_insn_index_reg_class): Ditto.
* config/i386/i386.md: Rename "gpr32" attribute to "addr"
and substitute its values with "0" -> "gpr16", "1" -> "*".
(addr): New attribute to limit allowed address register set.
(gpr32): Remove.
* config/i386/mmx.md: Rename "gpr32" attribute to "addr"
and substitute its values with "0" -> "gpr16", "1" -> "*".
* config/i386/sse.md: Ditto.

Testcases for vectorizer peeling

The following exercise otherwise not exercised paths in the
vectorizer peeling code, resulting in CPU 2017 build ICEs
when patching but no fallout in the testsuite.

* gfortran.dg/20231103-1.f90: New testcase.
* gfortran.dg/20231103-2.f90: Likewise.

Cleanup vectorizable_live_operation

During analyzing PR111950 I found the loop live operation code-gen
odd, in particular only replacing a single PHI but then adjusting
possibly remaining PHIs afterwards where there shouldn't really
be any out-of-loop uses of the scalar in-loop def left.

* tree-vect-loop.cc (vectorizable_live_operation): Simplify
LC PHI replacement.

GCN: Address undeclared 'NULL' usage in 'libgcc/config/gcn/gthr-gcn.h:__gthread_getspecific'

For 'libgcc/config/gcn/gthr-gcn.h' used in libstdc++ context (WIP), we have:

    [...]/build-gcc-offload-amdgcn-amdhsa/amdgcn-amdhsa/libstdc++-v3/include/amdgcn-amdhsa/bits/gthr-default.h: In function ‘void* __gthread_getspecific(__gthread_key_t)’:
    [...]/build-gcc-offload-amdgcn-amdhsa/amdgcn-amdhsa/libstdc++-v3/include/amdgcn-amdhsa/bits/gthr-default.h:90:10: error: ‘NULL’ was not declared in this scope
       90 |   return NULL;
          |          ^~~~

Resolve this with 's%NULL%0', as is used in
'libgcc/gthr-single.h:__gthread_getspecific', for example.

Follow-up to commit 76d463310787c8c7fd0c55cf88031b240311ab68
"Create GCN-specific gthreads".

libgcc/
* config/gcn/gthr-gcn.h (__gthread_getspecific): 's%NULL%0'.

Format gotools.sum closer to what DejaGnu does

... to restore compatability with validate_failures.py .
The testsuite script validate_failures.py expects
"Running <sub-testsuite> ..." to extract <sub-testsuite> values,
and gotools.sum provided "Running <sub-testsuite>".

Note that libgo.sum, which also uses Makefile logic to generate
DejaGnu-like output, already has "..." suffix.

gotools/ChangeLog:

* Makefile.am: Update "Running <sub-testsuite> ..." output
* Makefile.in: Regenerate.

Signed-off-by: Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>

ARC: Improve DImode left shift by a single bit.

This patch improves the code generated for x << 1 (and for x + x) when
X is 64-bit DImode, using the same two instruction code sequence used
for DImode addition.

For the test case:

long long foo(long long x) { return x << 1; }

GCC -O2 currently generates the following code:

foo:    lsr     r2,r0,31
        asl_s   r1,r1,1
        asl_s   r0,r0,1
        j_s.d   [blink]
        or_s    r1,r1,r2

and on CPU without a barrel shifter, i.e. -mcpu=em

foo: add.f   0,r0,r0
        asl_s   r1,r1
        rlc     r2,0
        asl_s   r0,r0
        j_s.d   [blink]
        or_s    r1,r1,r2

with this patch (both with and without a barrel shifter):

foo: add.f   r0,r0,r0
        j_s.d   [blink]
        adc     r1,r1,r1

A similar optimization is also applicable to H8300H, that could also use
a two instruction sequence (plus rts) but currently GCC generates 16
instructions (plus an rts) for foo above.

2023-11-03  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
* config/arc/arc.md (addsi3): Fix GNU-style code formatting.
(adddi3): Change define_expand to generate a *adddi3.
(*adddi3): New define_insn_and_split to lower DImode additions
during the split1 pass (after combine and before reload).
(ashldi3): New define_expand to (only) generate *ashldi3_cnt1
for DImode left shifts by a single bit.
(*ashldi3_cnt1): New define_insn_and_split to lower DImode
left shifts by one bit to an *adddi3.

gcc/testsuite/ChangeLog
* gcc.target/arc/adddi3-1.c: New test case.
* gcc.target/arc/ashldi3-1.c: Likewise.

aarch64: Remove unnecessary can_create_pseudo_p condition

This patch removes a can_create_pseudo_p condition from
*cmov_uxtw_insn_insv, bringing it in line with *cmov<mode>_insn_insv.
The constraints correctly describe the requirements.

gcc/
* config/aarch64/aarch64.md (*cmov_uxtw_insn_insv): Remove
can_create_pseudo_p condition.

VECT: Support SLP for MASK_LEN_GATHER_LOAD with dummy mask

This patch fixes following FAILs for RVV:
FAIL: gcc.dg/vect/vect-gather-1.c -flto -ffat-lto-objects  scan-tree-dump vect "Loop contains only SLP stmts"
FAIL: gcc.dg/vect/vect-gather-1.c scan-tree-dump vect "Loop contains only SLP stmts"

Bootstrap on X86 and regtest passed.

Ok for trunk ?

        PR tree-optimization/111721

gcc/ChangeLog:

* tree-vect-slp.cc (vect_get_and_check_slp_defs): Support SLP for dummy mask -1.
* tree-vect-stmts.cc (vectorizable_load): Ditto.

tree-optimization/112366 - remove assert for failed live lane code gen

The following removes a bogus assert constraining the uses that
could appear when a built from scalar defs SLP node constrains
code generation in a way so earlier uses of the vector CTOR
components fail to get vectorized.  We can't really constrain the
operation such use appears in.

PR tree-optimization/112366
* tree-vect-loop.cc (vectorizable_live_operation): Remove
assert.

Skip a number of 'g++.dg/tree-prof/' test cases for '-fno-exceptions' testing

Running 'make check' with: 'RUNTESTFLAGS=--target_board=unix/-fno-exceptions',
'error: exception handling disabled' is triggered for C++ 'throw' etc. usage,
and per 'gcc/testsuite/lib/gcc-dg.exp:gcc-dg-prune':

    # If exceptions are disabled, mark tests expecting exceptions to be enabled
    # as unsupported.
    if { ![check_effective_target_exceptions_enabled] } {
        if [regexp "(^|\n)\[^\n\]*: error: exception handling disabled" $text] {
          return "::unsupported::exception handling disabled"
        }

..., which generally means:

    -PASS: [...] (test for excess errors)
    +UNSUPPORTED: [...]: exception handling disabled

However, this doesn't work for 'g++.dg/tree-prof/' test cases.  For example:

    [-PASS:-]{+UNSUPPORTED:+} g++.dg/tree-prof/indir-call-prof-2.C [-compilation,  -fprofile-generate -D_PROFILE_GENERATE-]{+compilation: exception handling disabled+}
    [-PASS:-]{+UNRESOLVED:+} g++.dg/tree-prof/indir-call-prof-2.C execution,    -fprofile-generate -D_PROFILE_GENERATE
    [-PASS:-]{+UNRESOLVED:+} g++.dg/tree-prof/indir-call-prof-2.C compilation,  -fprofile-use -D_PROFILE_USE
    [-PASS:-]{+UNRESOLVED:+} g++.dg/tree-prof/indir-call-prof-2.C execution,    -fprofile-use -D_PROFILE_USE

Dependent tests turn UNRESOLVED if the first "compilation" runs into the
expected 'UNSUPPORTED: [...] compile: exception handling disabled'.

Specify 'dg-require-effective-target exceptions_enabled' for those test cases.

gcc/testsuite/
* g++.dg/tree-prof/indir-call-prof-2.C: Specify
'dg-require-effective-target exceptions_enabled'.
* g++.dg/tree-prof/partition1.C: Likewise.
* g++.dg/tree-prof/partition2.C: Likewise.
* g++.dg/tree-prof/partition3.C: Likewise.
* g++.dg/tree-prof/pr51719.C: Likewise.
* g++.dg/tree-prof/pr57451.C: Likewise.
* g++.dg/tree-prof/pr59255.C: Likewise.

Skip a number of 'g++.dg/lto/' test cases for '-fno-exceptions' testing

Running 'make check' with: 'RUNTESTFLAGS=--target_board=unix/-fno-exceptions',
'error: exception handling disabled' is triggered for C++ 'throw' etc. usage,
and per 'gcc/testsuite/lib/gcc-dg.exp:gcc-dg-prune':

    # If exceptions are disabled, mark tests expecting exceptions to be enabled
    # as unsupported.
    if { ![check_effective_target_exceptions_enabled] } {
        if [regexp "(^|\n)\[^\n\]*: error: exception handling disabled" $text] {
          return "::unsupported::exception handling disabled"
        }

..., which generally means:

    -PASS: [...] (test for excess errors)
    +UNSUPPORTED: [...]: exception handling disabled

However, this doesn't work for "split files" test cases.  For example:

    [-PASS:-]{+UNSUPPORTED:+} g++.dg/lto/20081109-1 cp_lto_20081109-1_0.o [-assemble, -fPIC -flto -flto-partition=1to1-]{+assemble: exception handling disabled+}
    [-PASS:-]{+UNRESOLVED:+} g++.dg/lto/20081109-1 cp_lto_20081109-1_0.o-cp_lto_20081109-1_0.o [-link,-]{+link+} -fPIC -flto -flto-partition=1to1
    {+UNRESOLVED: g++.dg/lto/20081109-1 cp_lto_20081109-1_0.o-cp_lto_20081109-1_0.o execute -fPIC -flto -flto-partition=1to1+}

The "compile"/"assemble" tests (either continue to work, or) result in the
expected 'UNSUPPORTED: [...] compile: exception handling disabled', but
dependent "link" and "execute" tests then turn UNRESOLVED.

Specify 'dg-require-effective-target exceptions_enabled' for those test cases.

gcc/testsuite/
* g++.dg/lto/20081109-1_0.C: Specify
'dg-require-effective-target exceptions_enabled'.
* g++.dg/lto/20081109_0.C: Likewise.
* g++.dg/lto/20091026-1_0.C: Likewise.
* g++.dg/lto/pr87906_0.C: Likewise.
* g++.dg/lto/pr88046_0.C: Likewise.

Skip a number of 'g++.dg/compat/' test cases for '-fno-exceptions' testing

Running 'make check' with: 'RUNTESTFLAGS=--target_board=unix/-fno-exceptions',
'error: exception handling disabled' is triggered for C++ 'throw' etc. usage,
and per 'gcc/testsuite/lib/gcc-dg.exp:gcc-dg-prune':

    # If exceptions are disabled, mark tests expecting exceptions to be enabled
    # as unsupported.
    if { ![check_effective_target_exceptions_enabled] } {
        if [regexp "(^|\n)\[^\n\]*: error: exception handling disabled" $text] {
          return "::unsupported::exception handling disabled"
        }

..., which generally means:

    -PASS: [...] (test for excess errors)
    +UNSUPPORTED: [...]: exception handling disabled

However, this doesn't work for "split files" test cases.  For example:

    PASS: g++.dg/compat/eh/ctor1 cp_compat_main_tst.o compile
    [-PASS:-]{+UNSUPPORTED:+} g++.dg/compat/eh/ctor1 cp_compat_x_tst.o [-compile-]{+compile: exception handling disabled+}
    [-PASS:-]{+UNSUPPORTED:+} g++.dg/compat/eh/ctor1 cp_compat_y_tst.o [-compile-]{+compile: exception handling disabled+}
    [-PASS:-]{+UNRESOLVED:+} g++.dg/compat/eh/ctor1 cp_compat_x_tst.o-cp_compat_y_tst.o link
    [-PASS:-]{+UNRESOLVED:+} g++.dg/compat/eh/ctor1 cp_compat_x_tst.o-cp_compat_y_tst.o execute

The "compile"/"assemble" tests (either continue to work, or) result in the
expected 'UNSUPPORTED: [...] compile: exception handling disabled', but
dependent "link" and "execute" tests then turn UNRESOLVED.

Specify 'dg-require-effective-target exceptions_enabled' for those test cases.

gcc/testsuite/
* g++.dg/compat/eh/ctor1_main.C: Specify
'dg-require-effective-target exceptions_enabled'.
* g++.dg/compat/eh/ctor2_main.C: Likewise.
* g++.dg/compat/eh/dtor1_main.C: Likewise.
* g++.dg/compat/eh/filter1_main.C: Likewise.
* g++.dg/compat/eh/filter2_main.C: Likewise.
* g++.dg/compat/eh/new1_main.C: Likewise.
* g++.dg/compat/eh/nrv1_main.C: Likewise.
* g++.dg/compat/eh/spec3_main.C: Likewise.
* g++.dg/compat/eh/template1_main.C: Likewise.
* g++.dg/compat/eh/unexpected1_main.C: Likewise.
* g++.dg/compat/init/array5_main.C: Likewise.

Skip a number of C++ test cases for '-fno-exceptions' testing

Running 'make check' with: 'RUNTESTFLAGS=--target_board=unix/-fno-exceptions',
'error: exception handling disabled' is triggered for C++ 'throw' etc. usage,
and per 'gcc/testsuite/lib/gcc-dg.exp:gcc-dg-prune':

    # If exceptions are disabled, mark tests expecting exceptions to be enabled
    # as unsupported.
    if { ![check_effective_target_exceptions_enabled] } {
if [regexp "(^|\n)\[^\n\]*: error: exception handling disabled" $text] {
    return "::unsupported::exception handling disabled"
}

..., which generally means:

    -PASS: [...] (test for excess errors)
    +UNSUPPORTED: [...]: exception handling disabled

However, if there are additional 'dg-error' etc. directives, these may regress
PASS -> FAIL (or similar) -- if their associated diagnostics are precluded by
'error: exception handling disabled'.  For example:

    PASS: g++.dg/cpp2a/explicit1.C    (test for errors, line 43)
    PASS: g++.dg/cpp2a/explicit1.C    (test for errors, line 47)
    [-PASS:-]{+FAIL:+} g++.dg/cpp2a/explicit1.C    (test for errors, line 50)
    [-PASS:-]{+FAIL:+} g++.dg/cpp2a/explicit1.C    (test for errors, line 51)
    PASS: g++.dg/cpp2a/explicit1.C    (test for errors, line 52)
    PASS: g++.dg/cpp2a/explicit1.C    (test for errors, line 53)
    PASS: g++.dg/cpp2a/explicit1.C    (test for errors, line 59)
    [-PASS:-]{+UNSUPPORTED:+} g++.dg/cpp2a/explicit1.C  [-(test for excess errors)-]{+: exception handling disabled+}

Specify 'dg-require-effective-target exceptions_enabled' for those test cases.

gcc/testsuite/
* g++.dg/cpp0x/catch1.C: Specify
'dg-require-effective-target exceptions_enabled'.
* g++.dg/cpp0x/constexpr-throw.C: Likewise.
* g++.dg/cpp1y/constexpr-89785-2.C: Likewise.
* g++.dg/cpp1y/constexpr-throw.C: Likewise.
* g++.dg/cpp1y/pr79393-3.C: Likewise.
* g++.dg/cpp2a/consteval-memfn1.C: Likewise.
* g++.dg/cpp2a/consteval11.C: Likewise.
* g++.dg/cpp2a/consteval34.C: Likewise.
* g++.dg/cpp2a/consteval9.C: Likewise.
* g++.dg/cpp2a/explicit1.C: Likewise.
* g++.dg/cpp2a/explicit2.C: Likewise.
* g++.dg/cpp2a/explicit5.C: Likewise.
* g++.dg/eh/builtin10.C: Likewise.
* g++.dg/eh/builtin11.C: Likewise.
* g++.dg/eh/builtin6.C: Likewise.
* g++.dg/eh/builtin7.C: Likewise.
* g++.dg/eh/builtin9.C: Likewise.
* g++.dg/eh/dtor4.C: Likewise.
* g++.dg/eh/pr42859.C: Likewise.
* g++.dg/ext/stmtexpr25.C: Likewise.
* g++.dg/ext/vla4.C: Likewise.
* g++.dg/init/placement4.C: Likewise.
* g++.dg/other/error32.C: Likewise.
* g++.dg/parse/crash55.C: Likewise.
* g++.dg/parse/pr31952-2.C: Likewise.
* g++.dg/parse/pr31952-3.C: Likewise.
* g++.dg/tm/noexcept-7.C: Likewise.
* g++.dg/torture/pr43257.C: Likewise.
* g++.dg/torture/pr56694.C: Likewise.
* g++.dg/torture/pr81659.C: Likewise.
* g++.dg/warn/Wcatch-value-1.C: Likewise.
* g++.dg/warn/Wcatch-value-2.C: Likewise.
* g++.dg/warn/Wcatch-value-3.C: Likewise.
* g++.dg/warn/Wcatch-value-3b.C: Likewise.
* g++.dg/warn/Wexceptions1.C: Likewise.
* g++.dg/warn/Wexceptions3.C: Likewise.
* g++.dg/warn/Winfinite-recursion-3.C: Likewise.
* g++.dg/warn/Wreturn-6.C: Likewise.
* g++.dg/warn/Wstringop-truncation-2.C: Likewise.
* g++.dg/warn/Wterminate1.C: Likewise.
* g++.old-deja/g++.eh/catch1.C: Likewise.
* g++.old-deja/g++.eh/catch10.C: Likewise.
* g++.old-deja/g++.eh/cond1.C: Likewise.
* g++.old-deja/g++.eh/ctor1.C: Likewise.
* g++.old-deja/g++.eh/throw2.C: Likewise.
* g++.old-deja/g++.other/cond5.C: Likewise.

tree-optimization/112310 - code hoisting undefined behavior

The following avoids hoisting expressions that may invoke undefined
behavior and are not computed on all paths.  This is realized by
noting that we have to avoid materializing expressions as part
of hoisting that are not part of the set of expressions we have
found eligible for hoisting.  Instead of picking the expression
corresponding to the hoistable values from the first successor
we now keep a union of the expressions so that hoisting can pick
the expression that has its dependences fully hoistable.

PR tree-optimization/112310
* tree-ssa-pre.cc (do_hoist_insertion): Keep the union
of expressions, validate dependences are contained within
the hoistable set before hoisting.

* gcc.dg/torture/pr112310.c: New testcase.

Fortran: Defined operators with unlimited polymorphic args [PR98498]

2023-11-03  Paul Thomas  <pault@gcc.gnu.org>

gcc/fortran
PR fortran/98498
* interface.cc (upoly_ok): Defined operators using unlimited
polymorphic formal arguments must not override the intrinsic
operator use.

gcc/testsuite/
PR fortran/98498
* gfortran.dg/interface_50.f90: New test.

RISC-V: Refactor prefix [I/L/LL] rounding API autovec iterator

Update in v2:

* Add mode size equal check to disable different mode size when expand,
  because the underlying codegen is not implemented yet.

Original log:

The previous rounding API start with i/l/ll only works on the same
mode types. For example as below, and we arrange the iterator similar
to fcvt.

* SF => SI
* DF => DI

After we refined this limination from middle-end, these API can also
vectorized with different type sizes, aka:

* HF => SI, HF => DI
* SF => DI, SF => SI
* DF => SI, DF => DI

Then the iterator cannot take care of this simply and this patch
would like to re-arrange the iterator in two items.

* V_VLS_F_CONVERT_SI: handle (HF, SF, DF) => SI
* V_VLS_F_CONVERT_DI: handle (HF, SF, DF) => DI

As well as related mode_attr to reconcile the new iterator.

gcc/ChangeLog:

* config/riscv/autovec.md (lrint<mode><v_i_l_ll_convert>2): Remove.
(lround<mode><v_i_l_ll_convert>2): Ditto.
(lceil<mode><v_i_l_ll_convert>2): Ditto.
(lfloor<mode><v_i_l_ll_convert>2): Ditto.
(lrint<mode><v_f2si_convert>2): New pattern for cvt from
FP to SI.
(lround<mode><v_f2si_convert>2): Ditto.
(lceil<mode><v_f2si_convert>2): Ditto.
(lfloor<mode><v_f2si_convert>2): Ditto.
(lrint<mode><v_f2di_convert>2): New pattern for cvt from
FP to DI.
(lround<mode><v_f2di_convert>2): Ditto.
(lceil<mode><v_f2di_convert>2): Ditto.
(lfloor<mode><v_f2di_convert>2): Ditto.
* config/riscv/vector-iterators.md: Renew iterators for both
the SI and DI.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Fix redundant vsetvl in fixed-vlmax vectorized codes[PR112326]

With compile option --param=riscv-autovec-preference=fixed-vlmax, we have
redundant AVL/VL toggling:

vsetvli a5,a3,e8,mf4,ta,ma -> should be changed into e32m1
vle32.v v1,0(a1)
vle32.v v2,0(a0)
vsetivli zero,4,e32,m1,ta,ma -> redundant
slli a2,a5,2
vadd.vv v1,v1,v2
sub a3,a3,a5
vsetvli zero,a5,e32,m1,ta,ma -> redundant
vse32.v v1,0(a4)
add a0,a0,a2
add a1,a1,a2
add a4,a4,a2
bne a3,zero,.L3

The root cause is because we simplify AVL into immediate AVL too early
in FIXED-VLMAX situation. The later avlprop PASS failed to propagate AVL
generated by (SELECT_VL/vsetvl VL, AVL) into the normal RVV instruction.

So we need to remove immedate AVL simplification in 'expand' stage.

After this patch:

   vsetvli a5,a3,e32,m1,ta,ma
slli a2,a5,2
vle32.v v1,0(a1)
vle32.v v2,0(a0)
sub a3,a3,a5
vadd.vv v1,v1,v2
vse32.v v1,0(a4)
add a0,a0,a2
add a1,a1,a2
add a4,a4,a2
bne a3,zero,.L3

After the removed simplification, the following situation should be fixed:
typedef int8_t vnx2qi __attribute__ ((vector_size (2)));

__attribute__ ((noipa)) void
f_vnx2qi (int8_t a, int8_t b, int8_t *out)
{
  vnx2qi v = {a, b};
  *(vnx2qi *) out = v;
}

We should use vsetvili zero, 2 instead of vsetvl a5,zero.
Such simplification is done in avlprop PASS which is also included in this patch
to fix regression of these situation.

PR target/112326

gcc/ChangeLog:

* config/riscv/riscv-avlprop.cc (get_insn_vtype_mode): New function.
(simplify_replace_vlmax_avl): Ditto.
(pass_avlprop::execute): Add immediate AVL simplification.
* config/riscv/riscv-protos.h (imm_avl_p): Rename.
* config/riscv/riscv-v.cc (const_vlmax_p): Ditto.
(imm_avl_p): Ditto.
(emit_vlmax_insn): Adapt for new interface name.
* config/riscv/vector.md (mode_idx): New attribute.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr112326.c: New test.

Revert "RISC-V: Refactor prefix [I/L/LL] rounding API autovec iterator"

This reverts commit 81a81abec5c28f2c08f986f1f17ac66e555cbd4b.

Daily bump.

RISC-V: Add check for types without insn reservations

Now that all insns are guaranteed to have a type, ensure every insn
is associated with a cpu unit/insn reservation.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_sched_variable_issue): add disabled assert

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>

Fortran: Fix for regression in ASSOCIATE [PR112316]

2023-11-02  Paul Thomas  <pault@gcc.gnu.org>

gcc/fortran
PR fortran/112316
* parse.cc (parse_associate): Remove condition that caused this
regression.

gcc/testsuite/
PR fortran/112316
* gfortran.dg/pr112316.f90: New test.

c++: use hash_set in nrv_data

I noticed we were using a hash_table directly here instead of the simpler
hash_set interface.  Also, let's check for the variable itself and repeats
earlier, since they should happen more often than any of the other cases.

gcc/cp/ChangeLog:

* semantics.cc (nrv_data): Change visited to hash_set.
(finalize_nrv_r): Reorganize.

c++: retval dtor on rethrow [PR112301]

In r12-6333 for PR33799, I fixed the example in [except.ctor]/2.  In that
testcase, the exception is caught and the function returns again,
successfully.

In this testcase, however, the exception is rethrown, and hits two separate
cleanups: one in the try block and the other in the function body.  So we
destroy twice an object that was only constructed once.

Fortunately, the fix for the normal case is easy: we just need to clear the
"return value constructed by return" flag when we do it the first time.

This gets more complicated with the named return value optimization, since
we don't want to destroy the return value while the NRV variable is still in
scope.

PR c++/112301
PR c++/102191
PR c++/33799

gcc/cp/ChangeLog:

* except.cc (maybe_splice_retval_cleanup): Clear
current_retval_sentinel when destroying retval.
* semantics.cc (nrv_data): Add in_nrv_cleanup.
(finalize_nrv): Set it.
(finalize_nrv_r): Fix handling of throwing cleanups.

gcc/testsuite/ChangeLog:

* g++.dg/eh/return1.C: Add more cases.

libstdc++: Add assertion to std::string_view::remove_suffix [PR112314]

libstdc++-v3/ChangeLog:

PR libstdc++/112314
* include/std/string_view (string_view::remove_suffix): Add
debug assertion.
* testsuite/21_strings/basic_string_view/modifiers/remove_prefix/debug.cc:
New test.
* testsuite/21_strings/basic_string_view/modifiers/remove_suffix/debug.cc:
New test.

c: Add missing conditions in Walloc-size to avoid ICEs [PR112347]

Fix ICE because of forgotten checks for pointers to void
and incomplete arrays.

Committed as obvious.

PR c/112347

gcc/c:
* c-typeck.cc (convert_for_assignment): Add missing check.

gcc/testsuite:

* gcc.dg/Walloc-size-3.c: New test.

d: Merge upstream dmd, druntime 643b1261bb, phobos 1c98326e7

D front-end changes:

    - Suggested preview switches now give gdc flags (PR109681).
    - `new S[10]' is now lowered to `_d_newarrayT!S(10)'.

D runtime changes:

    - Runtime compiler library functions `_d_newarrayU', `_d_newarrayT',
      `_d_newarrayiT' have been converted to templates.

Phobos changes:

    - Add new `std.traits.Unshared' template.

gcc/d/ChangeLog:

* dmd/MERGE: Merge upstream dmd 643b1261bb.
* d-attribs.cc (build_attributes): Update for new front-end interface.
* d-lang.cc (d_post_options): Likewise.
* decl.cc (layout_class_initializer): Likewise.

libphobos/ChangeLog:

* libdruntime/MERGE: Merge upstream druntime 643b1261bb.
* libdruntime/Makefile.am (DRUNTIME_DSOURCES_FREEBSD): Add
core/sys/freebsd/ifaddrs.d, core/sys/freebsd/net/if_dl.d,
core/sys/freebsd/sys/socket.d, core/sys/freebsd/sys/types.d.
(DRUNTIME_DSOURCES_LINUX): Add core/sys/linux/linux/if_arp.d,
core/sys/linux/linux/if_packet.d.
* libdruntime/Makefile.in: Regenerate.
* src/MERGE: Merge upstream phobos 1c98326e7.

libstdc++: Fix warning during configure

The checks for snprintf give a -Wformat warning due to a missing
argument.

libstdc++-v3/ChangeLog:

* acinclude.m4 (GLIBCXX_ENABLE_C99): Fix snprintf checks.
* configure: Regenerate.

[committed] Improve H8 sequences for single bit sign extractions

Spurred by Roger's recent work on ARC, this patch improves the code we
generation for single bit sign extractions.

The basic idea is to get the bit we want into C, the use a subx;ext.w;ext.l
sequence to sign extend it in a GPR.

For bits 0..15 we can use a bld instruction to get the bit we want into C.  For
bits 16..31, we can move the high word into the low word, then use bld.
There's a couple special cases where we can shift the bit we want from the high
word into C which is an instruction smaller.

Not surprisingly most cases seen in newlib and the test suite are extractions
from the low byte, HImode sign bit and top two bits of SImode.

Regression tested on the H8 with no regressions.  Installing on the trunk.

gcc/
* config/h8300/combiner.md: Add new patterns for single bit
sign extractions.

analyzer: fix clang warnings [PR112317]

No functional change intended.

gcc/analyzer/ChangeLog:
PR analyzer/112317
* access-diagram.cc (class x_aligned_x_ruler_widget): Eliminate
unused field "m_col_widths".
(access_diagram_impl::add_valid_vs_invalid_ruler): Update for
above change.
* region-model.cc
(check_one_function_attr_null_terminated_string_arg): Remove
unused variables "cd_unchecked", "strlen_sval", and
"limited_sval".
* region-model.h (region_model_context_decorator::warn): Add
missing "override".

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

RISC-V: Refactor prefix [I/L/LL] rounding API autovec iterator

The previous rounding API start with i/l/ll only works on the same
mode types. For example as below, and we arrange the iterator similar
to fcvt.

* SF => SI
* DF => DI

After we refined this limination from middle-end, these API can also
vectorized with different type sizes, aka:

* HF => SI, HF => DI
* SF => DI, SF => SI
* DF => SI, DF => DI

Then the iterator cannot take care of this simply and this patch
would like to re-arrange the iterator in two items.

* V_VLS_F_CONVERT_SI: handle (HF, SF, DF) => SI
* V_VLS_F_CONVERT_DI: handle (HF, SF, DF) => DI

As well as related mode_attr to reconcile the new iterator.

gcc/ChangeLog:

* config/riscv/autovec.md (lrint<mode><v_i_l_ll_convert>2): Remove.
(lround<mode><v_i_l_ll_convert>2): Ditto.
(lceil<mode><v_i_l_ll_convert>2): Ditto.
(lfloor<mode><v_i_l_ll_convert>2): Ditto.
(lrint<mode><v_f2si_convert>2): New pattern for cvt from
FP to SI.
(lround<mode><v_f2si_convert>2): Ditto.
(lceil<mode><v_f2si_convert>2): Ditto.
(lfloor<mode><v_f2si_convert>2): Ditto.
(lrint<mode><v_f2di_convert>2): New pattern for cvt from
FP to DI.
(lround<mode><v_f2di_convert>2): Ditto.
(lceil<mode><v_f2di_convert>2): Ditto.
(lfloor<mode><v_f2di_convert>2): Ditto.
* config/riscv/vector-iterators.md: Renew iterators for both
the SI and DI.

Signed-off-by: Pan Li <pan2.li@intel.com>

doc: explicitly say 'lifetime' for DCE

Say 'memory lifetime' rather than 'memory life' as lifetime is the more
standard term nowadays (indeed we have e.g. -fno-lifetime-dse).

It's also easier to grep for if someone is looking for the documentation on
where we do that.

gcc/ChangeLog:
* doc/passes.texi (Dead code elimination): Explicitly say 'lifetime'
as this has become the standard term for what we're doing here.

Signed-off-by: Sam James <sam@gentoo.org>

RISC-V: Fix bug of AVL propagation PASS

A run FAIL suddenly shows up today to me:
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-11.c execution test

that I didn't have before.

After investigation, I realize that there is a bug in AVL propagtion PASS.

gcc/ChangeLog:

* config/riscv/riscv-avlprop.cc
(pass_avlprop::get_vlmax_ta_preferred_avl): Don't allow
non-real insn AVL propation.

ifcvt/vect: Emit COND_OP for conditional scalar reduction.

As described in PR111401 we currently emit a COND and a PLUS expression
for conditional reductions.  This makes it difficult to combine both
into a masked reduction statement later.
This patch improves that by directly emitting a COND_ADD/COND_OP during
ifcvt and adjusting some vectorizer code to handle it.

It also makes neutral_op_for_reduction return -0 if HONOR_SIGNED_ZEROS
is true.

gcc/ChangeLog:

PR middle-end/111401
* internal-fn.cc (internal_fn_else_index): New function.
* internal-fn.h (internal_fn_else_index): Define.
* tree-if-conv.cc (convert_scalar_cond_reduction): Emit COND_OP
if supported.
(predicate_scalar_phi): Add whitespace.
* tree-vect-loop.cc (fold_left_reduction_fn): Add IFN_COND_OP.
(neutral_op_for_reduction): Return -0 for PLUS.
(check_reduction_path): Don't count else operand in COND_OP.
(vect_is_simple_reduction): Ditto.
(vect_create_epilog_for_reduction): Fix whitespace.
(vectorize_fold_left_reduction): Add COND_OP handling.
(vectorizable_reduction): Don't count else operand in COND_OP.
(vect_transform_reduction): Add COND_OP handling.
* tree-vectorizer.h (neutral_op_for_reduction): Add default
parameter.

gcc/testsuite/ChangeLog:

* gcc.dg/vect/vect-cond-reduc-in-order-2-signed-zero.c: New test.
* gcc.target/riscv/rvv/autovec/cond/pr111401.c: New test.
* gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: Adjust.
* gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c: Ditto.

tree-optimization/112320 - bougs debug IL after SCCP

The following addresses wrong debug IL created by SCCP rewriting stmts
to defined overflow.  I addressed another inefficiency there but
needed to adjust the API of rewrite_to_defined_overflow for this
which is now taking a stmt iterator for in-place operation and a
stmt for sequence producing because gsi_for_stmt doesn't work for
stmts not in the IL.

PR tree-optimization/112320
* gimple-fold.h (rewrite_to_defined_overflow): New overload
for in-place operation.
* gimple-fold.cc (rewrite_to_defined_overflow): Add stmt
iterator argument to worker, define separate API for
in-place and not in-place operation.
* tree-if-conv.cc (predicate_statements): Simplify.
* tree-scalar-evolution.cc (final_value_replacement_loop):
Likewise.
* tree-ssa-ifcombine.cc (pass_tree_ifcombine::execute): Adjust.
* tree-ssa-reassoc.cc (update_range_test): Likewise.

* gcc.dg/pr112320.c: New testcase.

i386: Move stack protector patterns above mov $0 -> xor peephole

Move stack protector patterns above mov $0,%reg -> xor %reg,%reg
so the later won't interfere with stack protector peephole2s.

gcc/ChangeLog:

* config/i386/i386.md: Move stack protector patterns
above mov $0,%reg -> xor %reg,%reg peephole2 pattern.

Make GCN target effective-target 'vect_gather_load_ifn'

This fixes:

     PASS: gcc.dg/vect/vect-gather-2.c (test for excess errors)
    -FAIL: gcc.dg/vect/vect-gather-2.c scan-tree-dump vect "different gather base"
    -FAIL: gcc.dg/vect/vect-gather-2.c scan-tree-dump vect "different gather scale"
     PASS: gcc.dg/vect/vect-gather-2.c scan-tree-dump-not vect "Loop contains only SLP stmts"

..., and enables other test cases.

gcc/testsuite/
* lib/target-supports.exp
(check_effective_target_vect_gather_load_ifn): True for GCN
target.

Support cmul{_conj}v4hf3/cmla{_conj}v4hf4 with AVX512FP16 instruction.

gcc/ChangeLog:

* config/i386/mmx.md (cmlav4hf4): New expander.
(cmla_conjv4hf4): Ditto.
(cmulv4hf3): Ditto.
(cmul_conjv4hf3): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/part-vect-complexhf.c: New test.

c++: Implement C++26 P2361R6 - Unevaluated strings [PR110342]

The following patch implements C++26 unevaluated-string.
As it seems to me just extra pedanticity, it is implemented only for
-std=c++26 or -std=gnu++26 and later and only if -pedantic/-pedantic-errors.
Nothing is done for inline asm, while the spec changes those, it changes it
to a balanced token sequence with implementation defined rules on what is
and isn't allowed (so pedantically accepting asm ("" : "+m" (x));
was accepts-invalid before C++26, but we didn't diagnose anything).
For the other spots mentioned in the paper, static_assert message,
linkage specification, deprecated/nodiscard attributes it enforces the
requirements (no prefixes, udlit suffixes, no octal/hexadecimal escapes
(conditional escape sequences were rejected with pedantic already before).
For the deprecated operator "" identifier case I've kept things as is,
because everything seems to have been diagnosed already (a lot being implied
from the string having to be empty).

2023-11-02  Jakub Jelinek  <jakub@redhat.com>

PR c++/110342
gcc/cp/
* parser.cc: Implement C++26 P2361R6 - Unevaluated strings.
(uneval_string_attr): New enumerator.
(cp_parser_string_literal_common): Add UNEVAL argument.  If true,
pass CPP_UNEVAL_STRING rather than CPP_STRING to
cpp_interpret_string_notranslate.
(cp_parser_string_literal, cp_parser_userdef_string_literal): Adjust
callers of cp_parser_string_literal_common.
(cp_parser_unevaluated_string_literal): New function.
(cp_parser_parenthesized_expression_list): Handle uneval_string_attr.
(cp_parser_linkage_specification): Use
cp_parser_unevaluated_string_literal for C++26.
(cp_parser_static_assert): Likewise.
(cp_parser_std_attribute): Use uneval_string_attr for standard
deprecated and nodiscard attributes.
gcc/testsuite/
* g++.dg/cpp26/unevalstr1.C: New test.
* g++.dg/cpp26/unevalstr2.C: New test.
* g++.dg/cpp0x/udlit-error1.C (lol): Expect an error for C++26
about user-defined literal in deprecated attribute.
libcpp/
* include/cpplib.h (TTYPE_TABLE): Add CPP_UNEVAL_STRING literal
entry.  Use C++11 instead of C++-0x in comments.
* charset.cc (convert_escape): Add UNEVAL argument, if true,
pedantically diagnose numeric escape sequences.
(cpp_interpret_string_1): Formatting fix.  Adjust convert_escape
caller.
(cpp_interpret_string): Formatting string.
(cpp_interpret_string_notranslate): Pass type through to
cpp_interpret_string if it is CPP_UNEVAL_STRING.

RISC-V: Fix redundant attributes

Notice that there are some reundant 'vimov' codes in attribute.

Committed as it is obvious.

gcc/ChangeLog:

* config/riscv/vector.md: Fix redundant codes in attributes.

RISC-V: Support vcreate intrinsics for non-tuple types

https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/288

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc: Expand non-tuple intrinsics.
* config/riscv/riscv-vector-builtins-functions.def (vcreate): Define non-tuple intrinsics.
* config/riscv/riscv-vector-builtins-shapes.cc (struct vcreate_def): Ditto.
* config/riscv/riscv-vector-builtins.cc: Add arg types.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/tuple_create.c: Rename to vcreate.c.
* gcc.target/riscv/rvv/base/vcreate.c: New test.

VECT: Refine the type size restriction of call vectorizer

Update in v4:

* Append the check to vectorizable_internal_function.

Update in v3:

* Add func to predicate type size is legal or not for vectorizer call.

Update in v2:

* Fix one ICE of type assertion.
* Adjust some test cases for aarch64 sve and riscv vector.

Original log:

The vectoriable_call has one restriction of the size of data type.
Aka DF to DI is allowed but SF to DI isn't. You may see below message
when try to vectorize function call like lrintf.

void
test_lrintf (long *out, float *in, unsigned count)
{
  for (unsigned i = 0; i < count; i++)
    out[i] = __builtin_lrintf (in[i]);
}

lrintf.c:5:26: missed: couldn't vectorize loop
lrintf.c:5:26: missed: not vectorized: unsupported data-type

Then the standard name pattern like lrintmn2 cannot work for different
data type size like SF => DI. This patch would like to refine this data
type size check and unblock the standard name like lrintmn2 on conditions.

The type size of vectype_out need to be exactly the same as the type
size of vectype_in when the vectype_out size isn't participating in
the optab selection. While there is no such restriction when the
vectype_out is somehow a part of the optab query.

The below test are passed for this patch.

* The risc-v regression tests.
* Ensure the lrintf standard name in risc-v.

The below test are ongoing.

* The x86 bootstrap and regression test.
* The aarch64 regression test.

gcc/ChangeLog:

* tree-vect-stmts.cc (vectorizable_internal_function): Add type
size check for vectype_out doesn't participating for optab query.
(vectorizable_call): Remove the type size check.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Allow dest operand and accumulator operand overlap of widen reduction instruction[PR112327]

Consider this following intrinsic code:

void rvv_dot_prod(int16_t *pSrcA, int16_t *pSrcB, uint32_t n, int64_t *result)
{
    size_t vl;
    vint16m4_t vSrcA, vSrcB;
    vint64m1_t vSum = __riscv_vmv_s_x_i64m1(0, 1);
    while (n > 0) {
        vl = __riscv_vsetvl_e16m4(n);
        vSrcA = __riscv_vle16_v_i16m4(pSrcA, vl);
        vSrcB = __riscv_vle16_v_i16m4(pSrcB, vl);
        vSum = __riscv_vwredsum_vs_i32m8_i64m1(__riscv_vwmul_vv_i32m8(vSrcA, vSrcB, vl), vSum, vl);
        pSrcA += vl;
        pSrcB += vl;
        n -= vl;
    }
    *result = __riscv_vmv_x_s_i64m1_i64(vSum);
}

https://godbolt.org/z/vWd35W7G6

Before this patch:

...
Loop:
...
vmv1r.v v2,v1
...
vwredsum.vs     v1,v8,v2
...

After this patch:

...
Loop:
...
vwredsum.vs v1,v8,v1
...

PR target/112327

gcc/ChangeLog:

* config/riscv/vector.md: Add '0'.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pr112327-1.c: New test.
* gcc.target/riscv/rvv/base/pr112327-2.c: New test.

Daily bump.

Minor formatting fix for newly-added file from previous commit

Committing under the "obvious" rule.

ChangeLog:

* .github/CONTRIBUTING.md: Wrap lines more tightly.

Add files to discourage submissions of PRs to the GitHub mirror.

Currently there is an unofficial mirror of GCC on GitHub that people
sometimes submit pull requests to:
https://github.com/gcc-mirror/gcc
However, this is not the proper way to contribute to GCC, so that means
that someone (usually Jonathan Wakely) has to go through the PRs and
manually tell people that they're sending their PRs to the wrong place.
One thing that would help mitigate this problem would be files in a
special .github directory that GitHub would automatically open when
contributors attempt to open a PR, that would then tell them the proper
way to contribute instead. This patch attempts to add two such files.
They are written in Markdown, which I'm realizing might require some
special handling in this repository, since the ".md" extension is also
used for GCC's "Machine Description" files here, but I'm not quite sure
how to go about handling that. Also note that I adapted these files from
equivalent files in the git repository for Git itself:
https://github.com/git/git/blob/master/.github/CONTRIBUTING.md
https://github.com/git/git/blob/master/.github/PULL_REQUEST_TEMPLATE.md
What do people think?

ChangeLog:

* .github/CONTRIBUTING.md: New file.
* .github/PULL_REQUEST_TEMPLATE.md: New file.

PR target/110551: Tweak mulx register allocation using peephole2.

This patch is a follow-up to my previous PR target/110551 patch, this
time to address the additional move after mulx, seen on TARGET_BMI2
architectures (such as -march=haswell).  The complication here is
that the flexible multiple-set mulx instruction is introduced into
RTL after reload, by split2, and therefore can't benefit from register
preferencing.  This results in RTL like the following:

(insn 32 31 17 2 (parallel [
            (set (reg:DI 4 si [orig:101 r ] [101])
                (mult:DI (reg:DI 1 dx [109])
                    (reg:DI 5 di [109])))
            (set (reg:DI 5 di [ r+8 ])
                (umul_highpart:DI (reg:DI 1 dx [109])
                    (reg:DI 5 di [109])))
        ]) "pr110551-2.c":8:17 -1
     (nil))

(insn 17 32 9 2 (set (reg:DI 0 ax [107])
        (reg:DI 5 di [ r+8 ])) "pr110551-2.c":9:40 90 {*movdi_internal}
     (expr_list:REG_DEAD (reg:DI 5 di [ r+8 ])
        (nil)))

Here insn 32, the mulx instruction, places its results in si and di,
and then immediately after decides to move di to ax, with di now dead.
This can be trivially cleaned up by a peephole2.  I've added an
additional constraint that the two SET_DESTs can't be the same
register to avoid confusing the middle-end, but this has well-defined
behaviour on x86_64/BMI2, encoding a umul_highpart.

For the new test case, compiled on x86_64 with -O2 -march=haswell:

Before:
mulx64: movabsq $-7046029254386353131, %rdx
        mulx    %rdi, %rsi, %rdi
        movq    %rdi, %rax
        xorq    %rsi, %rax
        ret

After:
mulx64: movabsq $-7046029254386353131, %rdx
        mulx    %rdi, %rsi, %rax
        xorq    %rsi, %rax
        ret

2023-11-01  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
PR target/110551
* config/i386/i386.md (*bmi2_umul<mode><dwi>3_1): Tidy condition
as operands[2] with predicate register_operand must be !MEM_P.
(peephole2): Optimize a mulx followed by a register-to-register
move, to place result in the correct destination if possible.

gcc/testsuite/ChangeLog
PR target/110551
* gcc.target/i386/pr110551-2.c: New test case.

RISC-V: Use riscv_subword_address for atomic_test_and_set

Other subword atomic patterns use riscv_subword_address to calculate
the aligned address, shift amount, mask and !mask. atomic_test_and_set
was implemented before the common function was added. After this patch
all subword atomic patterns use riscv_subword_address.

gcc/ChangeLog:

* config/riscv/sync.md:  Use riscv_subword_address function to
calculate the address and shift in atomic_test_and_set.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>

RISC-V: Enable ztso tests on rv32

This patch transitions the ztso testcases to use the testsuite infrastructure,
enabling the tests on both rv64 and rv32 targets.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Ztso extension to
dg-options for dg-do compile.
* gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-load-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-load-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-load-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-store-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-store-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-store-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto.
* lib/target-supports.exp: Add testing infrastructure to require the
Ztso extension or add it to an existing -march.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>

RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls

Fixes: 3496ca4e6566 ("RISC-V: Add runtime invariant support")
riscv_promote_function_mode doesn't promote a SI to DI for libcalls
case. It intends to do that however the code is broken (regression).

The fix is what generic promote_mode () in explow.cc does. I really
don't understand why the old code didn't work, but stepping thru the
debugger shows old code didn't and fixed does.

This showed up when testing Ajit's REE ABI extension series which probes
the ABI (using a NULL tree type) and ends up hitting the libcall code path.

gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_promote_function_mode): Fix mode
returned for libcall case.

Tested-by: Patrick O'Neill <patrick@rivosinc.com> # pre-commit-CI #526
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>

c: Add Walloc-size to warn about insufficient size in allocations [PR71219]

Add option Walloc-size that warns about allocations that have
insufficient storage for the target type of the pointer the
storage is assigned to. Added to Wextra.

PR c/71219
gcc:
* doc/invoke.texi: Document -Walloc-size option.

gcc/c-family:

* c.opt (Walloc-size): New option.

gcc/c:
* c-typeck.cc (convert_for_assignment): Add warning.

gcc/testsuite:

* gcc.dg/Walloc-size-1.c: New test.
* gcc.dg/Walloc-size-2.c: New test.

Make genautomata.cc output reflect insn-attr.h expectation

genautomata was writing the insn_has_dfa_reservation_p function
inside of the CPU_UNITS_QUERY conditional when it shouldn't have.
Move insn_has_dfa_reservation_p outside of conditional group.

gcc/ChangeLog:

* genautomata.cc (write_automata): move endif

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>

omp: Reorder call for TARGET_SIMD_CLONE_ADJUST

This patch moves the call to TARGET_SIMD_CLONE_ADJUST until after the arguments
and return types have been transformed into vector types.  It also constructs
the adjuments and retval modifications after this call, allowing targets to
alter the types of the arguments and return of the clone prior to the
modifications to the function definition.

gcc/ChangeLog:

* omp-simd-clone.cc (simd_clone_adjust_return_type): Hoist out code to
create return array and don't return new type.
(simd_clone_adjust_argument_types): Hoist out code that creates
ipa_param_body_adjustments and don't return them.
(simd_clone_adjust): Call TARGET_SIMD_CLONE_ADJUST after return and
argument types have been vectorized, create adjustments and return array
after the hook.
(expand_simd_clones): Call TARGET_SIMD_CLONE_ADJUST after return and
argument types have been vectorized.

i386: Fix stack protector peephole2 operand predicate [PR112332]

PR target/112332

gcc/ChangeLog:

* config/i386/i386.md (stack_protexct_set_2 peephole2):
Use general_gr_operand as operand 4 predicate.

i386: Improve stack protector patterns and peephole2s

Improve stack protector patterns and peephole2s to substitute stack
protector scratch register clear with unrelated subsequent register
initialization in several ways:

a. Explicitly generate scratch register as named pseudo.  This allows
optimizers to eventually reuse the zero value in the register.

b. Allow scratch register in different mode (SWI48) than PTR mode:

    d000: 65 48 8b 04 25 28 00  mov    %gs:0x28,%rax
    d007: 00 00
    d009: 48 89 44 24 08        mov    %rax,0x8(%rsp)
    d00e: 8b 87 e0 01 00 00     mov    0x1e0(%rdi),%eax

   SImode moves on x86 zero-extend to the whole DImode register,
   so stack protector paranoia is not compromised.

c. Relax peephole2 constraint that stack protector scratch register
   must match new initialized register.  This relaxation substantially
   improves peephole2 opportunities, and generates sequences like:

    a310: 65 4c 8b 34 25 28 00  mov    %gs:0x28,%r14
    a317: 00 00
    a319: 4c 89 74 24 08        mov    %r14,0x8(%rsp)
    a31e: 4c 8b b7 98 00 00 00  mov    0x98(%rdi),%r14

   We have to ensure the new scratch is dead in front of the sequence.

The patch also fixes omission of earlyclobbers for all alternatives of
new initialized register in *stack_protect_set_3, avoiding the need for
reg_overlap_mentioned_p constraint.  Earlyclobbers are per alternative,
not per operand.

Also, instructions are already valid in peephole2 pass, so we don't
have to explicitly re-check their operands for validity.

gcc/ChangeLog:

* config/i386/i386.md (stack_protect_set): Explicitly
generate scratch register in word mode.
(@stack_protect_set_1_<mode>): Rename to ...
(@stack_protect_set_1_<PTR:mode>_<SWI48:mode>): ... this.
Use SWI48 mode iterator to match scratch register.
(stack_protexct_set_1 peephole2): Use PTR, W and SWI48 mode
iterators to match peephole sequence.  Use general_operand
predicate for operand 4.  Allow different operand 2 and operand 3
registers and use peep2_reg_dead_p to ensure new scratch
register is dead before peephole seqeunce. Use peep2_reg_dead_p
to ensure old scratch register is dead after peephole sequence.
(*stack_protect_set_2_<mode>): Rename to ...
(*stack_protect_set_2_<mode>_si): .. this.
(*stack_protect_set_3): Rename to ...
(*stack_protect_set_2_<mode>_di): ... this.
Use PTR mode iterator to match stack protector memory move.
Use earlyclobber for all alternatives of operand 1.
(stack_protexct_set_2 peephole2): Use PTR, W and SWI48 mode
iterators to match peephole sequence.  Use general_operand
predicate for operand 4.  Allow different operand 2 and operand 3
registers and use peep2_reg_dead_p to ensure new scratch
register is dead before peephole seqeunce. Use peep2_reg_dead_p
to ensure old scratch register is dead after peephole sequence.

PR modula2/102989: reimplement overflow detection in ztype though WIDE_INT_MAX_PRECISION

The ZTYPE in iso modula2 is used to denote intemediate ordinal type const
expressions and these are always converted into the
approriate language or user ordinal type prior to code generation.
The increase of bits supported by _BitInt causes the modula2 largeconst.mod
regression failure tests to pass.  The largeconst.mod test has been
increased to fail, however the char at a time overflow check is now too slow
to detect failure.  The overflow detection for the ZTYPE has been
rewritten to check against exceeding WIDE_INT_MAX_PRECISION (many orders of
magnitude faster).

gcc/m2/ChangeLog:

PR modula2/102989
* gm2-compiler/SymbolTable.mod (OverflowZType): Import from m2expr.
(ConstantStringExceedsZType): Remove import.
(GetConstLitType): Replace ConstantStringExceedsZType with OverflowZType.
* gm2-gcc/m2decl.cc (m2decl_ConstantStringExceedsZType): Remove.
(m2decl_BuildConstLiteralNumber): Re-write.
* gm2-gcc/m2decl.def (ConstantStringExceedsZType): Remove.
* gm2-gcc/m2decl.h (m2decl_ConstantStringExceedsZType): Remove.
* gm2-gcc/m2expr.cc (m2expr_StrToWideInt): Rewrite to check overflow.
(m2expr_OverflowZType): New function.
(ToWideInt): New function.
* gm2-gcc/m2expr.def (OverflowZType): New procedure function declaration.
* gm2-gcc/m2expr.h (m2expr_OverflowZType): New prototype.

gcc/testsuite/ChangeLog:

PR modula2/102989
* gm2/pim/fail/largeconst.mod: Updated foo to an outrageous value.
* gm2/pim/fail/largeconst2.mod: Duplicate test removed.

Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>

RISC-V: Support vundefine intrinsics for tuple types

https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/288

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-functions.def (vundefined): Add vundefine
intrinsics for tuple types.
* config/riscv/riscv-vector-builtins.cc: Ditto.
* config/riscv/vector.md (@vundefined<mode>): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/tuple_vundefined.c: New test.

NFC: Fix whitespace

Notice there is a whitspace issue in previous commit:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=f66b2fc122b8a17591afbb881d580b32e8ddb708

Sorry for missing fixing this whitespace.

Committed as it is obvious.

gcc/ChangeLog:

* tree-vect-slp.cc (vect_build_slp_tree_1): Fix whitespace.

Daily bump.

analyzer: move class record_layout to its own .h/.cc

No functional change intended.

gcc/ChangeLog:
* Makefile.in (ANALYZER_OBJS): Add analyzer/record-layout.o.

gcc/analyzer/ChangeLog:
* record-layout.cc: New file, based on material in region-model.cc.
* record-layout.h: Likewise.
* region-model.cc: Include "analyzer/record-layout.h".
(class record_layout): Move to record-layout.cc and .h

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

libcpp: eliminate MACRO_MAP_EXPANSION_POINT_LOCATION

This patch eliminates the function "MACRO_MAP_EXPANSION_POINT_LOCATION"
(which hasn't been a macro since r6-739-g0501dbd932a7e9) in favor of
a new line_map_macro::get_expansion_point_location accessor.

No functional change intended.

gcc/c-family/ChangeLog:
* c-warn.cc (warn_for_multistatement_macros): Update for removal
of MACRO_MAP_EXPANSION_POINT_LOCATION.

gcc/cp/ChangeLog:
* module.cc (ordinary_loc_of): Update for removal of
MACRO_MAP_EXPANSION_POINT_LOCATION.
(module_state::note_location): Update for renaming of field.
(module_state::write_macro_maps): Likewise.

gcc/ChangeLog:
* input.cc (dump_location_info): Update for removal of
MACRO_MAP_EXPANSION_POINT_LOCATION.
* tree-diagnostic.cc (maybe_unwind_expanded_macro_loc):
Likewise.

libcpp/ChangeLog:
* include/line-map.h
(line_map_macro::get_expansion_point_location): New accessor.
(line_map_macro::expansion): Rename field to...
(line_map_macro::mexpansion): Rename field to...
(MACRO_MAP_EXPANSION_POINT_LOCATION): Delete this function.
* line-map.cc (linemap_enter_macro): Update for renaming of field.
(linemap_macro_map_loc_to_exp_point): Update for removal of
MACRO_MAP_EXPANSION_POINT_LOCATION.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

opts.cc: fix comment about DOCUMENTATION_ROOT_URL

gcc/ChangeLog:
* opts.cc (get_option_url): Update comment; the requirement to
pass DOCUMENTATION_ROOT_URL's value via -D was removed in
r10-8065-ge33a1eae25b8a8.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

pretty-print: gracefully handle null URLs

gcc/ChangeLog:
* pretty-print.cc (pretty_printer::pretty_printer): Initialize
m_skipping_null_url.
(pp_begin_url): Handle URL being null.
(pp_end_url): Likewise.
(selftest::test_null_urls): New.
(selftest::pretty_print_cc_tests): Call it.
* pretty-print.h (pretty_printer::m_skipping_null_url): New.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

VECT: Support SLP MASK_LEN_GATHER_LOAD with conditional mask

This patch leverage current MASK_GATHER_LOAD to support SLP MASK_LEN_GATHER_LOAD with condtional mask.

Unconditional MASK_LEN_GATHER_LOAD (base, offset, scale, zero, -1) SLP is not included in this patch
since it seems that we can't support it in the middle-end:

FAIL: gcc.dg/tree-ssa/pr44306.c (internal compiler error: in vectorizable_load, at tree-vect-stmts.cc:9885)

May be we should support GATHER_LOAD explictily in RISC-V backend to walk around this issue.

I am gonna support GATHER_LOAD explictly work around in RISC-V backend.

This patch also adds conditional gather load test since there is no conditional gather load test.

Ok for trunk ?

gcc/ChangeLog:

* tree-vect-slp.cc (vect_get_operand_map): Add MASK_LEN_GATHER_LOAD.
(vect_build_slp_tree_1): Ditto.
(vect_build_slp_tree_2): Ditto.

gcc/testsuite/ChangeLog:

* gcc.dg/vect/vect-gather-6.c: New test.

bpf: Improvements in CO-RE builtins implementation.

This patch moved the processing of attribute preserve_access_index to
its own independent pass in a gimple lowering pass.
This approach is more consistent with the implementation of the CO-RE
builtins when used explicitly in the code.  The attributed type accesses
are now early converted to __builtin_core_reloc builtin instead of being
kept as an expression in code through out all of the middle-end.
This disables the compiler to optimize out or manipulate the expression
using the local defined type, instead of assuming nothing is known about
this expression, as it should be the case in all of the CO-RE
relocations.

In the process, also the __builtin_preserve_access_index has been
improved to generate code for more complex expressions that would
require more then one CO-RE relocation.
This turned out to be a requirement, since bpf-next selftests would rely on
loop unrolling in order to convert an undefined index array access into a
defined one. This seemed extreme to expect for the unroll to happen, and for
that reason GCC still generates correct code in such scenarios, even when index
access is never predictable or unrolling does not occur.

gcc/ChangeLog:
* config/bpf/bpf-passes.def (pass_lower_bpf_core): Added pass.
* config/bpf/bpf-protos.h: Added prototype for new pass.
* config/bpf/bpf.cc (bpf_delegitimize_address): New function.
* config/bpf/bpf.md (mov_reloc_core<MM:mode>): Prefixed
name with '*'.
* config/bpf/core-builtins.cc (cr_builtins) Added access_node to
struct.
(is_attr_preserve_access): Improved check.
(core_field_info): Make use of root_for_core_field_info
function.
(process_field_expr): Adapted to new functions.
(pack_type): Small improvement.
(bpf_handle_plugin_finish_type): Adapted to GTY(()).
(bpf_init_core_builtins): Changed to new function names.
(construct_builtin_core_reloc): Improved implementation.
(bpf_resolve_overloaded_core_builtin): Changed how
__builtin_preserve_access_index is converted.
(compute_field_expr): Corrected implementation. Added
access_node argument.
(bpf_core_get_index): Added valid argument.
(root_for_core_field_info, pack_field_expr)
(core_expr_with_field_expr_plus_base, make_core_safe_access_index)
(replace_core_access_index_comp_expr, maybe_get_base_for_field_expr)
(core_access_clean, core_is_access_index, core_mark_as_access_index)
(make_gimple_core_safe_access_index, execute_lower_bpf_core)
(make_pass_lower_bpf_core): Added functions.
(pass_data_lower_bpf_core): New pass struct.
(pass_lower_bpf_core): New gimple_opt_pass class.
(pack_field_expr_for_preserve_field)
(bpf_replace_core_move_operands): Removed function.
(bpf_enum_value_kind): Added GTY(()).
* config/bpf/core-builtins.h (bpf_field_info_kind, bpf_type_id_kind)
(bpf_type_info_kind, bpf_enum_value_kind): New enum.
* config/bpf/t-bpf: Added pass bpf-passes.def to PASSES_EXTRA.

gcc/testsuite/ChangeLog:
* gcc.target/bpf/core-attr-5.c: New test.
* gcc.target/bpf/core-attr-6.c: New test.
* gcc.target/bpf/core-builtin-1.c: Corrected
* gcc.target/bpf/core-builtin-enumvalue-opt.c: Corrected regular
expression.
* gcc.target/bpf/core-builtin-enumvalue.c: Corrected regular
expression.
* gcc.target/bpf/core-builtin-exprlist-1.c: New test.
* gcc.target/bpf/core-builtin-exprlist-2.c: New test.
* gcc.target/bpf/core-builtin-exprlist-3.c: New test.
* gcc.target/bpf/core-builtin-exprlist-4.c: New test.
* gcc.target/bpf/core-builtin-fieldinfo-offset-1.c: Extra tests

gcc: config: microblaze: fix cpu version check

The MICROBLAZE_VERSION_COMPARE was incorrectly using strcasecmp
instead of strverscmp to check the mcpu version against feature
options.  By simply changing the define to use strverscmp,
the new version 10.0 is treated correctly as a higher version
than previous versions.

gcc/ChangeLog:

* config/microblaze/microblaze.cc: Fix mcpu version check.

gcc/testsuite/ChangeLog:

* gcc.target/microblaze/isa/bshift.c: Bump to mcpu=v10.0.
* gcc.target/microblaze/isa/div.c: Ditto.
* gcc.target/microblaze/isa/fcmp1.c: Ditto.
* gcc.target/microblaze/isa/fcmp2.c: Ditto.
* gcc.target/microblaze/isa/fcmp3.c: Ditto.
* gcc.target/microblaze/isa/fcmp4.c: Ditto.
* gcc.target/microblaze/isa/fcvt.c: Ditto.
* gcc.target/microblaze/isa/float.c: Ditto.
* gcc.target/microblaze/isa/fsqrt.c: Ditto.
* gcc.target/microblaze/isa/mul-bshift-pcmp.c: Ditto.
* gcc.target/microblaze/isa/mul-bshift.c: Ditto.
* gcc.target/microblaze/isa/mul.c: Ditto.
* gcc.target/microblaze/isa/mulh-bshift-pcmp.c: Ditto.
* gcc.target/microblaze/isa/mulh.c: Ditto.
* gcc.target/microblaze/isa/nofcmp.c: Ditto.
* gcc.target/microblaze/isa/nofloat.c: Ditto.
* gcc.target/microblaze/isa/pcmp.c: Ditto.
* gcc.target/microblaze/isa/vanilla.c: Ditto.
* gcc.target/microblaze/microblaze.exp: Ditto.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michael J. Eager <eager@eagercon.com>

RISC-V: Require a extension for testcases with atomic insns

Add testsuite infrastructure for the A extension and use it to require the A
extension for dg-do run and add the add extension for non-A dg-do compile.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/amo-table-a-6-amo-add-1.c: Add A extension to
dg-options for dg-do compile.
* gcc.target/riscv/amo-table-a-6-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-a-6-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-a-6-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-a-6-amo-add-5.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Ditto.
* gcc.target/riscv/inline-atomics-2.c: Ditto.
* gcc.target/riscv/inline-atomics-3.c: Require A extension for dg-do
run.
* gcc.target/riscv/inline-atomics-4.c: Ditto.
* gcc.target/riscv/inline-atomics-5.c: Ditto.
* gcc.target/riscv/inline-atomics-6.c: Ditto.
* gcc.target/riscv/inline-atomics-7.c: Ditto.
* gcc.target/riscv/inline-atomics-8.c: Ditto.
* lib/target-supports.exp: Add testing infrastructure to require the A
extension or add it to an existing -march.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>

RISC-V: Let non-atomic targets use optimized amo loads/stores

Non-atomic targets are currently prevented from using the optimized fencing for
seq_cst load/seq_cst store. This patch removes that constraint.

gcc/ChangeLog:

* config/riscv/sync-rvwmo.md (atomic_load_rvwmo<mode>): Remove
TARGET_ATOMIC constraint
(atomic_store_rvwmo<mode>): Ditto.
* config/riscv/sync-ztso.md (atomic_load_ztso<mode>): Ditto.
(atomic_store_ztso<mode>): Ditto.
* config/riscv/sync.md (atomic_load<mode>): Ditto.
(atomic_store<mode>): Ditto.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>

riscv: thead: Add support for the XTheadFMemIdx ISA extension

The XTheadFMemIdx ISA extension provides additional load and store
instructions for floating-point registers with new addressing modes.

The following memory accesses types are supported:
* load/store: [w,d] (single-precision FP, double-precision FP)

The following addressing modes are supported:
* register offset with additional immediate offset (4 instructions):
  flr<type>, fsr<type>
* zero-extended register offset with additional immediate offset
  (4 instructions): flur<type>, fsur<type>

These addressing modes are also part of the similar XTheadMemIdx
ISA extension support, whose code is reused and extended to support
floating-point registers.

One challenge that this patch needs to solve are GP registers in FP-mode
(e.g. "(reg:DF a2)"), which cannot be handled by the XTheadFMemIdx
instructions. Such registers are the result of independent
optimizations, which can happen after register allocation.
This patch uses a simple but efficient method to address this:
add a dependency for XTheadMemIdx to XTheadFMemIdx optimizations.
This allows to use the instructions from XTheadMemIdx in case
of such registers.

The added tests ensure that this feature won't regress without notice.
Testing: GCC regression test suite and SPEC CPU 2017 intrate (base&peak).

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_index_reg_class):
Return GR_REGS for XTheadFMemIdx.
(riscv_regno_ok_for_index_p): Add support for XTheadFMemIdx.
* config/riscv/riscv.h (HARDFP_REG_P): New macro.
* config/riscv/thead.cc (is_fmemidx_mode): New function.
(th_memidx_classify_address_index): Add support for XTheadFMemIdx.
(th_fmemidx_output_index): New function.
(th_output_move): Add support for XTheadFMemIdx.
* config/riscv/thead.md (TH_M_ANYF): New mode iterator.
(TH_M_NOEXTF): Likewise.
(*th_fmemidx_movsf_hardfloat): New INSN.
(*th_fmemidx_movdf_hardfloat_rv64): Likewise.
(*th_fmemidx_I_a): Likewise.
(*th_fmemidx_I_c): Likewise.
(*th_fmemidx_US_a): Likewise.
(*th_fmemidx_US_c): Likewise.
(*th_fmemidx_UZ_a): Likewise.
(*th_fmemidx_UZ_c): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xtheadfmemidx-index-update.c: New test.
* gcc.target/riscv/xtheadfmemidx-index-xtheadbb-update.c: New test.
* gcc.target/riscv/xtheadfmemidx-index-xtheadbb.c: New test.
* gcc.target/riscv/xtheadfmemidx-index.c: New test.
* gcc.target/riscv/xtheadfmemidx-uindex-update.c: New test.
* gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb-update.c: New test.
* gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb.c: New test.
* gcc.target/riscv/xtheadfmemidx-uindex.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

riscv: thead: Add support for the XTheadMemIdx ISA extension

The XTheadMemIdx ISA extension provides a additional load and store
instructions with new addressing modes.

The following memory accesses types are supported:
* load: b,bu,h,hu,w,wu,d
* store: b,h,w,d

The following addressing modes are supported:
* immediate offset with PRE_MODIFY or POST_MODIFY (22 instructions):
  l<ltype>.ia, l<ltype>.ib, s<stype>.ia, s<stype>.ib
* register offset with additional immediate offset (11 instructions):
  lr<ltype>, sr<stype>
* zero-extended register offset with additional immediate offset
  (11 instructions): lur<ltype>, sur<stype>

The RISC-V base ISA does not support index registers, so the changes
are kept separate from the RISC-V standard support as much as possible.

To combine the shift/multiply instructions into the memory access
instructions, this patch comes with a few insn_and_split optimizations
that allow the combiner to do this task.

Handling the different cases of extensions results in a couple of INSNs
that look redundant on first view, but they are just the equivalence
of what we already have for Zbb as well. The only difference is, that
we have much more load instructions.

We already have a constraint with the name 'th_f_fmv', therefore,
the new constraints follow this pattern and have the same length
as required ('th_m_mia', 'th_m_mib', 'th_m_mir', 'th_m_miu').

The added tests ensure that this feature won't regress without notice.
Testing: GCC regression test suite, GCC bootstrap build, and
SPEC CPU 2017 intrate (base&peak) on C920.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
gcc/ChangeLog:

* config/riscv/constraints.md (th_m_mia): New constraint.
(th_m_mib): Likewise.
(th_m_mir): Likewise.
(th_m_miu): Likewise.
* config/riscv/riscv-protos.h (enum riscv_address_type):
Add new address types ADDRESS_REG_REG, ADDRESS_REG_UREG,
and ADDRESS_REG_WB and their documentation.
(struct riscv_address_info): Add new field 'shift' and
document the field usage for the new address types.
(riscv_valid_base_register_p): New prototype.
(th_memidx_legitimate_modify_p): Likewise.
(th_memidx_legitimate_index_p): Likewise.
(th_classify_address): Likewise.
(th_output_move): Likewise.
(th_print_operand_address): Likewise.
* config/riscv/riscv.cc (riscv_index_reg_class):
Return GR_REGS for XTheadMemIdx.
(riscv_regno_ok_for_index_p): Add support for XTheadMemIdx.
(riscv_classify_address): Call th_classify_address() on top.
(riscv_output_move): Call th_output_move() on top.
(riscv_print_operand_address): Call th_print_operand_address()
on top.
* config/riscv/riscv.h (HAVE_POST_MODIFY_DISP): New macro.
(HAVE_PRE_MODIFY_DISP): Likewise.
* config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2): Disable
for XTheadMemIdx.
(*zero_extendqi<SUPERQI:mode>2_internal): Convert to expand,
create INSN with same name and disable it for XTheadMemIdx.
(extendsidi2): Likewise.
(*extendsidi2_internal): Disable for XTheadMemIdx.
* config/riscv/thead.cc (valid_signed_immediate): New helper
function.
(th_memidx_classify_address_modify): New function.
(th_memidx_legitimate_modify_p): Likewise.
(th_memidx_output_modify): Likewise.
(is_memidx_mode): Likewise.
(th_memidx_classify_address_index): Likewise.
(th_memidx_legitimate_index_p): Likewise.
(th_memidx_output_index): Likewise.
(th_classify_address): Likewise.
(th_output_move): Likewise.
(th_print_operand_address): Likewise.
* config/riscv/thead.md (*th_memidx_operand): New splitter.
(*th_memidx_zero_extendqi<SUPERQI:mode>2): New INSN.
(*th_memidx_extendsidi2): Likewise.
(*th_memidx_zero_extendsidi2): Likewise.
(*th_memidx_zero_extendhi<GPR:mode>2): Likewise.
(*th_memidx_extend<SHORT:mode><SUPERQI:mode>2): Likewise.
(*th_memidx_bb_zero_extendsidi2): Likewise.
(*th_memidx_bb_zero_extendhi<GPR:mode>2): Likewise.
(*th_memidx_bb_extendhi<GPR:mode>2): Likewise.
(*th_memidx_bb_extendqi<SUPERQI:mode>2): Likewise.
(TH_M_ANYI): New mode iterator.
(TH_M_NOEXTI): Likewise.
(*th_memidx_I_a): New combiner optimization.
(*th_memidx_I_b): Likewise.
(*th_memidx_I_c): Likewise.
(*th_memidx_US_a): Likewise.
(*th_memidx_US_b): Likewise.
(*th_memidx_US_c): Likewise.
(*th_memidx_UZ_a): Likewise.
(*th_memidx_UZ_b): Likewise.
(*th_memidx_UZ_c): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xtheadmemidx-helpers.h: New test.
* gcc.target/riscv/xtheadmemidx-index-update.c: New test.
* gcc.target/riscv/xtheadmemidx-index-xtheadbb-update.c: New test.
* gcc.target/riscv/xtheadmemidx-index-xtheadbb.c: New test.
* gcc.target/riscv/xtheadmemidx-index.c: New test.
* gcc.target/riscv/xtheadmemidx-modify-xtheadbb.c: New test.
* gcc.target/riscv/xtheadmemidx-modify.c: New test.
* gcc.target/riscv/xtheadmemidx-uindex-update.c: New test.
* gcc.target/riscv/xtheadmemidx-uindex-xtheadbb-update.c: New test.
* gcc.target/riscv/xtheadmemidx-uindex-xtheadbb.c: New test.
* gcc.target/riscv/xtheadmemidx-uindex.c: New test.

rs6000, Add missing overloaded bcd builtin tests, documentation

Currently we have the documentation for __builtin_vec_bcdsub_{eq,gt,lt} but
not for __builtin_bcdsub_{gl}e, this patch is to supplement the descriptions
for them.  Although they are mainly for __builtin_bcdcmp{ge,le}, we already
have some testing coverage for __builtin_vec_bcdsub_{eq,gt,lt}, this patch
adds the corresponding explicit test cases as well.

gcc/ChangeLog:
* doc/extend.texi (__builtin_bcdsub_le, __builtin_bcdsub_ge): Add
documentation for the builti-ins.

gcc/testsuite/ChangeLog:
* gcc.target/powerpc/bcd-3.c (do_sub_ge, do_suble): Add functions
to test builtins __builtin_bcdsub_ge and __builtin_bcdsub_le.

gcc: config: microblaze: fix cpu version check

The MICROBLAZE_VERSION_COMPARE was incorrectly using strcasecmp
instead of strverscmp to check the mcpu version against feature
options.  By simply changing the define to use strverscmp,
the new version 10.0 is treated correctly as a higher version
than previous versions.

Fix incorrect warning with -mcpu=10.0:
  warning: '-mxl-multiply-high' can be used only with
  '-mcpu=v6.00.a' or greater

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michael J. Eager <eager@eagercon.com>

[RA]: Fixing LRA cycling for multi-reg variable containing a fixed reg

PR111971 test case uses a multi-reg variable containing a fixed reg.  LRA
rejects such multi-reg because of this when matching the constraint for
an asm insn.  The rejection results in LRA cycling.  The patch fixes this issue.

gcc/ChangeLog:

PR rtl-optimization/111971
* lra-constraints.cc: (process_alt_operands): Don't check start
hard regs for regs originated from register variables.

gcc/testsuite/ChangeLog:

PR rtl-optimization/111971
* gcc.target/powerpc/pr111971.c: New test.

Add OpenACC 'acc_map_data' variant to 'libgomp.oacc-c-c++-common/deep-copy-8.c'

libgomp/
* testsuite/libgomp.oacc-c-c++-common/deep-copy-8.c: Add OpenACC
'acc_map_data' variant.

RISC-V: Add vector fmin/fmax expanders.

This patch adds expanders for fmin and fmax.  As per RISC-V V Spec 1.0
vfmin/vfmax are IEEE 754-2019 compliant which differs from IEEE 754-2008
that fmin/fmax require (particularly in the signaling-NaN handling).
Therefore the pattern conditions include a !HONOR_SNANS.

gcc/ChangeLog:

* config/riscv/autovec.md (<ieee_fmaxmin_op><mode>3): fmax/fmin
expanders.
(cond_<ieee_fmaxmin_op><mode>): Ditto.
(cond_len_<ieee_fmaxmin_op><mode>): Ditto.
(reduc_fmax_scal_<mode>): Ditto.
(reduc_fmin_scal_<mode>): Ditto.
* config/riscv/riscv-v.cc (needs_fp_rounding): Add fmin/fmax.
* config/riscv/vector-iterators.md (fmin): New UNSPEC.
(UNSPEC_VFMIN): Ditto.
* config/riscv/vector.md (@pred_<ieee_fmaxmin_op><mode>): Add
UNSPEC insn patterns.
(@pred_<ieee_fmaxmin_op><mode>_scalar): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Remove
-ffast-math.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/fmax-1.c: New test.
* gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c: New test.
* gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/binop/fmin-1.c: New test.
* gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c: New test.
* gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c: New test.
* gcc.target/riscv/rvv/autovec/reduc/reduc-10.c: New test.
* gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c: New test.
* gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c: New test.
* gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c: New test.

genemit: Split insn-emit.cc into several partitions.

On riscv insn-emit.cc has grown to over 1.2 mio lines of code and
compiling it takes considerable time.
Therefore, this patch adjust genemit to create several partitions
(insn-emit-1.cc to insn-emit-n.cc).  The available patterns are
written to the given files in a sequential fashion.

Similar to match.pd a configure option --with-emitinsn-partitions=num
is introduced that makes the number of partition configurable.

gcc/ChangeLog:

PR bootstrap/84402
PR target/111600

* Makefile.in: Handle split insn-emit.cc.
* configure: Regenerate.
* configure.ac: Add --with-insnemit-partitions.
* genemit.cc (output_peephole2_scratches): Print to file instead
of stdout.
(print_code): Ditto.
(gen_rtx_scratch): Ditto.
(gen_exp): Ditto.
(gen_emit_seq): Ditto.
(emit_c_code): Ditto.
(gen_insn): Ditto.
(gen_expand): Ditto.
(gen_split): Ditto.
(output_add_clobbers): Ditto.
(output_added_clobbers_hard_reg_p): Ditto.
(print_overload_arguments): Ditto.
(print_overload_test): Ditto.
(handle_overloaded_code_for): Ditto.
(handle_overloaded_gen): Ditto.
(print_header): New function.
(handle_arg): New function.
(main): Split output into 10 files.
* gensupport.cc (count_patterns): New function.
* gensupport.h (count_patterns): Define.
* read-md.cc (md_reader::print_md_ptr_loc): Add file argument.
* read-md.h (class md_reader): Change definition.

hardcfr: support checking at abnormal edges [PR111943]

Control flow redundancy may choose abnormal edges for early checking,
but that breaks because we can't insert checks on such edges.

Introduce conditional checking on the dest block of abnormal edges,
and leave it for the optimizer to drop the conditional.

for  gcc/ChangeLog

PR tree-optimization/111943
* gimple-harden-control-flow.cc: Adjust copyright year.
(rt_bb_visited): Add vfalse and vtrue data members.
Zero-initialize them in the ctor.
(rt_bb_visited::insert_exit_check_on_edge): Upon encountering
abnormal edges, insert initializers for vfalse and vtrue on
entry, and insert the check sequence guarded by a conditional
in the dest block.

for  libgcc/ChangeLog

* hardcfr.c: Adjust copyright year.

for  gcc/testsuite/ChangeLog

PR tree-optimization/111943
* gcc.dg/harden-cfr-pr111943.c: New.