coroutines: Collect the function body rewrite code.
The standard describes a rewrite of the body of the user-authored
function (which wraps it in a try-catch block and provides the
initial and final suspend expressions). The exact arrangement of
this was still in flux right up until the DIS and as a consequence
was a bit of a moving target.
The net result was a fragmented implementation of the parts of
the rewrite which is now impeding progress in fixing other issues.
This patch collates the rewrite action into a single function and
carries this out earlier.
gcc/cp/ChangeLog:
* coroutines.cc (expand_one_await_expression): Remove
code dealing with initial suspend.
(build_actor_fn): Remove code special-casing initial
and final suspend. Handle the final suspend and marking
of the coroutine as done.
(coro_rewrite_function_body): New.
(bind_expr_find_in_subtree): Remove.
(coro_body_contains_bind_expr_p): Remove.
(morph_fn_to_coro): Split the rewrite of the original
function into coro_rewrite_function_body and call it.
arm: Fix the failing mve scalar shift execution tests.
In GCC testsuite the MVE scalar shift execution tests (mve_scalar_shifts[1-4].c) are failings
because of executing them on target hardware which doesn't support MVE instructions. This patch
restricts those tests to execute only on target hardware that support MVE instructions.
* config/rs6000/driver-rs6000.c (asm_names): Use -mpwr10 for power10
on AIX, and -mpower10 elsewhere.
* config/rs6000/future.md: Delete.
* config/rs6000/linux64.h: Update comments. Use TARGET_POWER10, not
TARGET_FUTURE.
* config/rs6000/power10.md: New file.
* config/rs6000/rs6000-builtin.def: Update comments.
* config/rs6000/rs6000-call.c: Use P10_BUILTIN_*, not FUTURE_BUILTIN_*.
Update compiler messages.
* config/rs6000/rs6000-cpus.def: Update comments. Use ISA_3_1_*, not
ISA_FUTURE_*. Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE.
* config/rs6000/rs6000-opts.h: Use PROCESSOR_POWER10, not
PROCESSOR_FUTURE.
* config/rs6000/rs6000-string.c: Ditto.
* config/rs6000/rs6000-tables.opt (rs6000_cpu_opt_value): Use "power10"
instead of "future", reorder it to right after "power9".
* config/rs6000/rs6000.c: Update comments. Use OPTION_MASK_POWER10,
not OPTION_MASK_FUTURE. Use TARGET_POWER10, not TARGET_FUTURE. Use
RS6000_BTM_P10, not RS6000_BTM_FUTURE. Update compiler messages.
Use PROCESSOR_POWER10, not PROCESSOR_FUTURE. Use ISA_3_1_MASKS_SERVER,
not ISA_FUTURE_MASKS_SERVER.
(rs6000_opt_masks): Use "power10" instead of "future".
(rs6000_builtin_mask_names): Ditto.
(rs6000_disable_incompatible_switches): Ditto.
* config/rs6000/rs6000.h: Use -mpower10, not -mfuture. Use
-mcpu=power10, not -mcpu=future. Use MASK_POWER10, not MASK_FUTURE.
Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE. Use RS6000_BTM_P10,
not RS6000_BTM_FUTURE.
* config/rs6000/rs6000.md: Use "power10", not "future". Use
TARGET_POWER10, not TARGET_FUTURE. Include "power10.md", not
"future.md".
* config/rs6000/rs6000.opt (mfuture): Delete.
(mpower10): New.
* config/rs6000/t-rs6000: Use "power10.md", not "future.md".
* config/rs6000/vsx.md: Use TARGET_POWER10, not TARGET_FUTURE.
Alex Coplan [Mon, 18 May 2020 15:29:04 +0000 (16:29 +0100)]
arm: Don't generate invalid LDRD insns
This fixes a bug in the arm backend where GCC generates invalid LDRD
instructions. The LDRD instruction requires the first transfer register to be
even, but GCC attempts to use odd registers here. For example, with the
following C code:
struct c {
double a;
} __attribute((aligned)) __attribute((packed));
struct c d;
struct c f(struct c);
void e() { f(d); }
The struct d is passed in registers r1 and r2 to the function f, and GCC
attempted to do this with a LDRD instruction when compiling with -march=armv7-a
on a soft float toolchain.
The fix is analogous to the corresponding one for STRD in the same function:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=52057dc4ac5295caebf83147f688d769c93cbc8d
gcc/:
* config/arm/arm.c (output_move_double): Fix codegen when loading into
a register pair with an odd base register.
gcc/testsuite/:
* gcc.c-torture/compile/packed-aligned-1.c: New test.
* gcc.c-torture/execute/packed-aligned.c: New test.
Thomas Koenig [Mon, 29 Jun 2020 21:11:06 +0000 (23:11 +0200)]
Do not generate recursion check for compiler-generated procedures.
This one-line fix removes a check for recursion for procedures
which are compiler-generated, such as finalizers or deallocation.
These need to be recursive, even if the user code should not be.
gcc/fortran/ChangeLog:
PR fortran/95743
* trans-decl.c (gfc_generate_function_code): Do not generate
recursion check for compiler-generated procedures.
Iain Sandoe [Tue, 30 Jun 2020 07:18:34 +0000 (08:18 +0100)]
coroutines: Handle awaiters that are sub-objects [PR95736]
Move deciding on initializers for awaitables to the build of the
co_await, this allows us to analyse cases that do not need
a temporary at that point.
As the PR shows, the late analysis meant that we were not
checking properly for the case that an awaiter is a sub-object
of an existing variable outside the current function scope (and
therefore does not need to be duplicated in the frame).
gcc/cp/ChangeLog:
PR c++/95736
* coroutines.cc (get_awaitable_var): New helper.
(build_co_await): Check more carefully before
copying an awaitable.
(expand_one_await_expression): No initializer
is required when the awaitable is not a temp.
(register_awaits): Remove handling that is now
completed when the await expression is built.
gcc/testsuite/ChangeLog:
PR c++/95736
* g++.dg/coroutines/pr95736.C: New test.
Iain Sandoe [Tue, 30 Jun 2020 06:54:39 +0000 (07:54 +0100)]
coroutines: Improve diagnostics for one allocator case.
If the user provides operator new and that is noexcept, this
implies that it can fail with a null return. At that point, we expect
to be able to call get_return_object_on_allocation_failure().
This diagnoses the case where such an operator new has been
provided, but the g-r-o-o-a-f is either missing or unusable.
The PR points out that the standard does not restrict promise
expressions to methods, but the current implementation does.
The patch factors out the building of a general promise expression,
and then uses it in a fairly mechanical replacement of each case
that we need such an expressions.
This extends the handling for p.xxxxxx() expressions to cover the
cases where the promise member is some form callable.
Tests are added for each of the promise expressions.
It's somewhat tortuous to find good uses for this for the
get-return-object and get-return-object-on-allocation-failure
cases, but they are included anyway.
PR c++/95519
* coroutines.cc (struct coroutine_info):Add a field
to hold computed p.return_void expressions.
(coro_build_promise_expression): New.
(get_coroutine_return_void_expr): New.
(finish_co_yield_expr): Build the promise expression
using coro_build_promise_expression.
(finish_co_return_stmt): Likewise.
(build_init_or_final_await): Likewise.
(morph_fn_to_coro): Likewise, for several cases.
gcc/testsuite/ChangeLog:
PR c++/95519
* g++.dg/coroutines/torture/pr95519-00-return_void.C: New test.
* g++.dg/coroutines/torture/pr95519-01-initial-suspend.C: New test.
* g++.dg/coroutines/torture/pr95519-02-final_suspend.C: New test.
* g++.dg/coroutines/torture/pr95519-03-return-value.C: New test.
* g++.dg/coroutines/torture/pr95519-04-yield-value.C: New test.
* g++.dg/coroutines/torture/pr95519-05-gro.C: New test.
* g++.dg/coroutines/torture/pr95519-06-grooaf.C: New test.
* g++.dg/coroutines/torture/pr95519-07-unhandled-exception.C: New test.
Iain Sandoe [Mon, 29 Jun 2020 09:52:07 +0000 (10:52 +0100)]
coroutines: Handle bad g-r-o-o-a-f cases.
If we see a get_return_object_on_allocation_failure in the
promise, we expect to be able to use it. If this isn't
possible (because of some error in the declaration) then we
need to handle the erroneous return to allow following code
to complete.
gcc/cp/ChangeLog:
* coroutines.cc (morph_fn_to_coro): Handle error
returns in building g-r-o-o-a-f expressions.
gcc/testsuite/ChangeLog:
* g++.dg/coroutines/coro1-allocators.h (BAD_GROOAF_STATIC):
New.
* g++.dg/coroutines/coro-bad-grooaf-00-static.C: New test.
PR libstdc++/95915
* include/std/variant (_Uninitialized):
Adjust the condition and the comment.
* testsuite/20_util/variant/95915.cc: New.
* testsuite/20_util/variant/compile.cc: Add new test.
Jakub Jelinek [Sat, 27 Jun 2020 10:38:23 +0000 (12:38 +0200)]
c-family: Use TYPE_OVERFLOW_UNDEFINED instead of !TYPE_UNSIGNED in pointer_sum [PR95903]
For lp64 targets and int off ... ptr[off + 1]
is lowered in pointer_sum to *(ptr + ((sizetype) off + (sizetype) 1)).
That is fine when signed integer wrapping is undefined (and is not done
already if off has unsigned type), but changes behavior for -fwrapv, where
overflow is well defined. Runtime test could be:
int
main ()
{
char *p = __builtin_malloc (0x100000000UL);
if (!p) return 0;
char *q = p + 0x80000000UL;
int o = __INT_MAX__;
q[o + 1] = 1;
if (q[-__INT_MAX__ - 1] != 1) __builtin_abort ();
return 0;
}
with -fwrapv or so, not included in the testsuite because it requires 4GB
allocation (with some other test it would be enough to have something
slightly above 2GB, but still...).
2020-06-27 Jakub Jelinek <jakub@redhat.com>
PR middle-end/95903
gcc/c-family/
* c-common.c (pointer_int_sum): Use TYPE_OVERFLOW_UNDEFINED instead of
!TYPE_UNSIGNED check to see if we can apply distributive law and handle
smaller precision intop operands separately.
gcc/testsuite/
* c-c++-common/pr95903.c: New test.
Jakub Jelinek [Wed, 24 Jun 2020 08:40:02 +0000 (10:40 +0200)]
fold-const: Fix A <= 0 ? A : -A folding [PR95810]
We folded A <= 0 ? A : -A into -ABS (A), which is for signed integral types
incorrect - can invoke on INT_MIN UB twice, once on ABS and once on its
negation.
The following patch fixes it by instead folding it to (type)-ABSU (A).
2020-06-24 Jakub Jelinek <jakub@redhat.com>
PR middle-end/95810
* fold-const.c (fold_cond_expr_with_comparison): Optimize
A <= 0 ? A : -A into (type)-absu(A) rather than -abs(A).
* dmd/cond.c (lowerArrayAggregate): Directly use the elements of the
array for TupleExp creation.
(lowerNonArrayAggregate): Inline creation of foreach range indexes.
Iain Sandoe [Sun, 28 Jun 2020 08:48:33 +0000 (09:48 +0100)]
coroutines: Copy attributes to the outlined functions [PR95518,PR95813]
We had omitted the copying of function attributes, we now copy
the used, alignment, section values from the original decal and
the complete set of function attributes. It is likely that
some function attributes don't really make sense for coroutines,
but that can be disgnosed separately. Also mark the outlined
functions as artificial, since they are; some diagnostic
processing tests this.
gcc/cp/ChangeLog:
PR c++/95518
PR c++/95813
* coroutines.cc (act_des_fn): Copy function
attributes onto the outlined coroutine helpers.
gcc/testsuite/ChangeLog:
PR c++/95518
PR c++/95813
* g++.dg/coroutines/pr95518.C: New test.
* g++.dg/coroutines/pr95813.C: New test.
Iain Sandoe [Sun, 28 Jun 2020 07:10:12 +0000 (08:10 +0100)]
coroutines: Update tests for get-return-object errors.
We updated the handling of the errors for cases when the
ramp return cannot be constructed from the user's provided
get-return-object method. This updates the testcases to
cover this.
gcc/testsuite/ChangeLog:
* g++.dg/coroutines/void-gro-non-class-coro.C: Moved to...
* g++.dg/coroutines/coro-bad-gro-01-void-gro-non-class-coro.C: ...here.
* g++.dg/coroutines/coro-bad-gro-00-class-gro-scalar-return.C: New test.
Iain Sandoe [Thu, 25 Jun 2020 13:33:23 +0000 (14:33 +0100)]
coroutines: Add a cleanup expression for g-r-o when needed [PR95477].
The PR reports that we fail to destroy the object initially created from
the get-return-object call. Fixed by adding a cleanup when the DTOR is
non-trivial. In addition, to meet the specific wording that the call to
get_return_object creates the glvalue for the return, we must construct
that in-place in the return object to avoid a second copy/move CTOR.
gcc/cp/ChangeLog:
PR c++/95477
* coroutines.cc (morph_fn_to_coro): Apply a cleanup to
the get return object when the DTOR is non-trivial.
gcc/testsuite/ChangeLog:
PR c++/95477
* g++.dg/coroutines/pr95477.C: New test.
* g++.dg/coroutines/void-gro-non-class-coro.C: New test.
Peter Bergner [Sun, 21 Jun 2020 04:23:02 +0000 (23:23 -0500)]
rs6000: Add MMA built-in function definitions and test cases
Add the Matrix-Multiply Assist (MMA) built-ins. The MMA accumulators are
INOUT operands for most MMA instructions, but they are also very expensive
to move around. For this reason, we have implemented a built-in API where
the accumulators are passed using pass-by-reference/pointers, so the user
won't use one accumulator as input and another as output, which wouldentail
a lot of copies. However, using pointers gives us poor code generation
when we expand the built-ins at normal expand time. We therefore expand
the MMA built-ins early into gimple, converting the pass-by-reference calls
to an internal built-in that uses pass-by-value calling convention, where
we can enforce the input and output accumulators are the same. This gives
us much better code generation.
2020-06-20 Peter Bergner <bergner@linux.ibm.com>
gcc/
* config/rs6000/predicates.md (mma_assemble_input_operand): New.
* config/rs6000/rs6000-builtin.def (BU_MMA_1, BU_MMA_V2, BU_MMA_3,
BU_MMA_5, BU_MMA_6, BU_VSX_1): Add support macros for defining MMA
built-in functions.
(ASSEMBLE_ACC, ASSEMBLE_PAIR, DISASSEMBLE_ACC, DISASSEMBLE_PAIR,
PMXVBF16GER2, PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN,
PMXVBF16GER2PP, PMXVF16GER2, PMXVF16GER2NN, PMXVF16GER2NP,
PMXVF16GER2PN, PMXVF16GER2PP, PMXVF32GER, PMXVF32GERNN,
PMXVF32GERNP, PMXVF32GERPN, PMXVF32GERPP, PMXVF64GER, PMXVF64GERNN,
PMXVF64GERNP, PMXVF64GERPN, PMXVF64GERPP, PMXVI16GER2, PMXVI16GER2PP,
PMXVI16GER2S, PMXVI16GER2SPP, PMXVI4GER8, PMXVI4GER8PP, PMXVI8GER4,
PMXVI8GER4PP, PMXVI8GER4SPP, XVBF16GER2, XVBF16GER2NN, XVBF16GER2NP,
XVBF16GER2PN, XVBF16GER2PP, XVCVBF16SP, XVCVSPBF16, XVF16GER2,
XVF16GER2NN, XVF16GER2NP, XVF16GER2PN, XVF16GER2PP, XVF32GER,
XVF32GERNN, XVF32GERNP, XVF32GERPN, XVF32GERPP, XVF64GER, XVF64GERNN,
XVF64GERNP, XVF64GERPN, XVF64GERPP, XVI16GER2, XVI16GER2PP, XVI16GER2S,
XVI16GER2SPP, XVI4GER8, XVI4GER8PP, XVI8GER4, XVI8GER4PP, XVI8GER4SPP,
XXMFACC, XXMTACC, XXSETACCZ): Add MMA built-ins.
* config/rs6000/rs6000.c (rs6000_emit_move): Use CONST_INT_P.
Allow zero constants.
(print_operand) <case 'A'>: New output modifier.
(rs6000_split_multireg_move): Add support for inserting accumulator
priming and depriming instructions. Add support for splitting an
assemble accumulator pattern.
* config/rs6000/rs6000-call.c (mma_init_builtins, mma_expand_builtin,
rs6000_gimple_fold_mma_builtin): New functions.
(RS6000_BUILTIN_M): New macro.
(def_builtin): Handle RS6000_BTC_QUAD and RS6000_BTC_PAIR attributes.
(bdesc_mma): Add new MMA built-in support.
(htm_expand_builtin): Use RS6000_BTC_OPND_MASK.
(rs6000_invalid_builtin): Add handling of RS6000_BTM_FUTURE and
RS6000_BTM_MMA.
(rs6000_builtin_valid_without_lhs): Handle RS6000_BTC_VOID attribute.
(rs6000_gimple_fold_builtin): Call rs6000_builtin_is_supported_p
and rs6000_gimple_fold_mma_builtin.
(rs6000_expand_builtin): Call mma_expand_builtin.
Use RS6000_BTC_OPND_MASK.
(rs6000_init_builtins): Adjust comment. Call mma_init_builtins.
(htm_init_builtins): Use RS6000_BTC_OPND_MASK.
(builtin_function_type): Handle VSX_BUILTIN_XVCVSPBF16 and
VSX_BUILTIN_XVCVBF16SP.
* config/rs6000/rs6000.h (RS6000_BTC_QUINARY, RS6000_BTC_SENARY,
RS6000_BTC_OPND_MASK, RS6000_BTC_QUAD, RS6000_BTC_PAIR,
RS6000_BTC_QUADPAIR, RS6000_BTC_GIMPLE): New defines.
(RS6000_BTC_PREDICATE, RS6000_BTC_ABS, RS6000_BTC_DST,
RS6000_BTC_TYPE_MASK, RS6000_BTC_ATTR_MASK): Adjust values.
* config/rs6000/mma.md (MAX_MMA_OPERANDS): New define_constant.
(UNSPEC_MMA_ASSEMBLE_ACC, UNSPEC_MMA_PMXVBF16GER2,
UNSPEC_MMA_PMXVBF16GER2NN, UNSPEC_MMA_PMXVBF16GER2NP,
UNSPEC_MMA_PMXVBF16GER2PN, UNSPEC_MMA_PMXVBF16GER2PP,
UNSPEC_MMA_PMXVF16GER2, UNSPEC_MMA_PMXVF16GER2NN,
UNSPEC_MMA_PMXVF16GER2NP, UNSPEC_MMA_PMXVF16GER2PN,
UNSPEC_MMA_PMXVF16GER2PP, UNSPEC_MMA_PMXVF32GER,
UNSPEC_MMA_PMXVF32GERNN, UNSPEC_MMA_PMXVF32GERNP,
UNSPEC_MMA_PMXVF32GERPN, UNSPEC_MMA_PMXVF32GERPP,
UNSPEC_MMA_PMXVF64GER, UNSPEC_MMA_PMXVF64GERNN,
UNSPEC_MMA_PMXVF64GERNP, UNSPEC_MMA_PMXVF64GERPN,
UNSPEC_MMA_PMXVF64GERPP, UNSPEC_MMA_PMXVI16GER2,
UNSPEC_MMA_PMXVI16GER2PP, UNSPEC_MMA_PMXVI16GER2S,
UNSPEC_MMA_PMXVI16GER2SPP, UNSPEC_MMA_PMXVI4GER8,
UNSPEC_MMA_PMXVI4GER8PP, UNSPEC_MMA_PMXVI8GER4,
UNSPEC_MMA_PMXVI8GER4PP, UNSPEC_MMA_PMXVI8GER4SPP,
UNSPEC_MMA_XVBF16GER2, UNSPEC_MMA_XVBF16GER2NN,
UNSPEC_MMA_XVBF16GER2NP, UNSPEC_MMA_XVBF16GER2PN,
UNSPEC_MMA_XVBF16GER2PP, UNSPEC_MMA_XVF16GER2, UNSPEC_MMA_XVF16GER2NN,
UNSPEC_MMA_XVF16GER2NP, UNSPEC_MMA_XVF16GER2PN, UNSPEC_MMA_XVF16GER2PP,
UNSPEC_MMA_XVF32GER, UNSPEC_MMA_XVF32GERNN, UNSPEC_MMA_XVF32GERNP,
UNSPEC_MMA_XVF32GERPN, UNSPEC_MMA_XVF32GERPP, UNSPEC_MMA_XVF64GER,
UNSPEC_MMA_XVF64GERNN, UNSPEC_MMA_XVF64GERNP, UNSPEC_MMA_XVF64GERPN,
UNSPEC_MMA_XVF64GERPP, UNSPEC_MMA_XVI16GER2, UNSPEC_MMA_XVI16GER2PP,
UNSPEC_MMA_XVI16GER2S, UNSPEC_MMA_XVI16GER2SPP, UNSPEC_MMA_XVI4GER8,
UNSPEC_MMA_XVI4GER8PP, UNSPEC_MMA_XVI8GER4, UNSPEC_MMA_XVI8GER4PP,
UNSPEC_MMA_XVI8GER4SPP, UNSPEC_MMA_XXMFACC, UNSPEC_MMA_XXMTACC): New.
(MMA_ACC, MMA_VV, MMA_AVV, MMA_PV, MMA_APV, MMA_VVI4I4I8,
MMA_AVVI4I4I8, MMA_VVI4I4I2, MMA_AVVI4I4I2, MMA_VVI4I4,
MMA_AVVI4I4, MMA_PVI4I2, MMA_APVI4I2, MMA_VVI4I4I4,
MMA_AVVI4I4I4): New define_int_iterator.
(acc, vv, avv, pv, apv, vvi4i4i8, avvi4i4i8, vvi4i4i2,
avvi4i4i2, vvi4i4, avvi4i4, pvi4i2, apvi4i2, vvi4i4i4,
avvi4i4i4): New define_int_attr.
(*movpxi): Add zero constant alternative.
(mma_assemble_pair, mma_assemble_acc): New define_expand.
(*mma_assemble_acc): New define_insn_and_split.
(mma_<acc>, mma_xxsetaccz, mma_<vv>, mma_<avv>, mma_<pv>, mma_<apv>,
mma_<vvi4i4i8>, mma_<avvi4i4i8>, mma_<vvi4i4i2>, mma_<avvi4i4i2>,
mma_<vvi4i4>, mma_<avvi4i4>, mma_<pvi4i2>, mma_<apvi4i2>,
mma_<vvi4i4i4>, mma_<avvi4i4i4>): New define_insn.
* config/rs6000/rs6000.md (define_attr "type"): New type mma.
* config/rs6000/vsx.md (UNSPEC_VSX_XVCVBF16SP): New.
(UNSPEC_VSX_XVCVSPBF16): Likewise.
(XVCVBF16): New define_int_iterator.
(xvcvbf16): New define_int_attr.
(vsx_<xvcvbf16>): New define_insn.
* doc/extend.texi: Document the mma built-ins.
gcc/testsuite/
* gcc.target/powerpc/mma-builtin-1.c: New test.
* gcc.target/powerpc/mma-builtin-2.c: New test.
* gcc.target/powerpc/mma-builtin-3.c: New test.
* gcc.target/powerpc/mma-builtin-4.c: New test.
* gcc.target/powerpc/mma-builtin-5.c: New test.
* gcc.target/powerpc/mma-builtin-6.c: New test.
Peter Bergner [Sun, 21 Jun 2020 03:00:15 +0000 (22:00 -0500)]
rs6000: Add base support and types for defining MMA built-ins
Add the new -mmma option as well as the initial MMA support, which includes
the target specific __vector_pair and __vector_quad types, the POImode and
PXImode partial integer modes they are mapped to, and their associated
move patterns. Support for the restrictions on the registers these modes
can be assigned to as also been added.
2020-06-20 Peter Bergner <bergner@linux.ibm.com>
Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/mma.md: New file.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
__MMA__ for mma.
* config/rs6000/rs6000-call.c (rs6000_init_builtins): Add support
for __vector_pair and __vector_quad types.
* config/rs6000/rs6000-cpus.def (OTHER_FUTURE_MASKS): Add
OPTION_MASK_MMA.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000-modes.def (OI, XI): New integer modes.
(POI, PXI): New partial integer modes.
* config/rs6000/rs6000.c (TARGET_INVALID_CONVERSION): Define.
(rs6000_hard_regno_nregs_internal): Use VECTOR_ALIGNMENT_P.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
Add support for POImode being allowed in VSX registers and PXImode
being allowed in FP registers.
(rs6000_modes_tieable_p): Adjust comment.
Add support for POImode and PXImode.
(rs6000_debug_reg_global) <print_tieable_modes>: Add OImode, POImode
XImode, PXImode, V2SImode, V2SFmode and CCFPmode..
(rs6000_setup_reg_addr_masks): Use VECTOR_ALIGNMENT_P.
Set up appropriate addr_masks for vector pair and vector quad addresses.
(rs6000_init_hard_regno_mode_ok): Add support for vector pair and
vector quad registers. Setup reload handlers for POImode and PXImode.
(rs6000_builtin_mask_calculate): Add support for RS6000_BTM_MMA.
(rs6000_option_override_internal): Error if -mmma is specified
without -mcpu=future.
(rs6000_slow_unaligned_access): Use VECTOR_ALIGNMENT_P.
(quad_address_p): Change size test to less than 16 bytes.
(reg_offset_addressing_ok_p): Add support for ISA 3.1 vector pair
and vector quad instructions.
(avoiding_indexed_address_p): Likewise.
(rs6000_emit_move): Disallow POImode and PXImode moves involving
constants.
(rs6000_preferred_reload_class): Prefer VSX registers for POImode
and FP registers for PXImode.
(rs6000_split_multireg_move): Support splitting POImode and PXImode
move instructions.
(rs6000_mangle_type): Adjust comment. Add support for mangling
__vector_pair and __vector_quad types.
(rs6000_opt_masks): Add entry for mma.
(rs6000_builtin_mask_names): Add RS6000_BTM_MMA and RS6000_BTM_FUTURE.
(rs6000_function_value): Use VECTOR_ALIGNMENT_P.
(address_to_insn_form): Likewise.
(reg_to_non_prefixed): Likewise.
(rs6000_invalid_conversion): New function.
* config/rs6000/rs6000.h (MASK_MMA): Define.
(BIGGEST_ALIGNMENT): Set to 512 if MMA support is enabled.
(VECTOR_ALIGNMENT_P): New helper macro.
(ALTIVEC_VECTOR_MODE): Use VECTOR_ALIGNMENT_P.
(RS6000_BTM_MMA): Define.
(RS6000_BTM_COMMON): Add RS6000_BTM_MMA and RS6000_BTM_FUTURE.
(rs6000_builtin_type_index): Add RS6000_BTI_vector_pair and
RS6000_BTI_vector_quad.
(vector_pair_type_node): New.
(vector_quad_type_node): New.
* config/rs6000/rs6000.md: Include mma.md.
(define_mode_iterator RELOAD): Add POI and PXI.
* config/rs6000/t-rs6000 (MD_INCLUDES): Add mma.md.
* config/rs6000/rs6000.opt (-mmma): New.
* doc/invoke.texi: Document -mmma.
Jason Merrill [Wed, 24 Jun 2020 01:25:21 +0000 (21:25 -0400)]
c++: Fix ICE with using and virtual function. [PR95719]
conversion_path points to the base where we found the using-declaration, not
where the function is actually a member; look up the actual base. And then
maybe look back to the derived class if the base is primary.
gcc/cp/ChangeLog:
PR c++/95719
* call.c (build_over_call): Look up the overrider in base_binfo.
* class.c (lookup_vfn_in_binfo): Look through BINFO_PRIMARY_P.
gcc/testsuite/ChangeLog:
PR c++/95719
* g++.dg/tree-ssa/final4.C: New test.
Jonathan Wakely [Wed, 24 Jun 2020 10:45:01 +0000 (11:45 +0100)]
libstdc++: Fix std::from_chars to ignore leading zeros in base 2
The parser for binary numbers returned an error if the entire string
contains more digits than the result type. Leading zeros should be
ignored.
libstdc++-v3/ChangeLog:
* include/std/charconv (__from_chars_binary): Ignore leading zeros.
* testsuite/20_util/from_chars/1.cc: Check "0x1" for all bases,
not just 10 and 16.
* testsuite/20_util/from_chars/3.cc: New test.
The __detail::__to_chars_2 function assumes it won't be called with zero
values. However, when the output buffer is empty the caller doesn't
handle zero values correctly, and calls __to_chars_2 with a zero value,
resulting in an overflow of the empty buffer.
The __detail::__to_chars_i function should just return immediately for
an empty buffer, and otherwise ensure zero values are handled properly.
libstdc++-v3/ChangeLog:
PR libstdc++/95851
* include/std/charconv (__to_chars_i): Check for zero-sized
buffer unconditionally.
* testsuite/20_util/to_chars/95851.cc: New test.
Richard Biener [Wed, 17 Jun 2020 12:57:59 +0000 (14:57 +0200)]
tree-optimization/95717 - fix SSA update for vectorizer epilogue
This fixes yet another issue with the custom SSA updating in the
vectorizer when we copy from the non-if-converted loop. We must
not mess with current defs before we updated the BB copies.
2020-06-17 Richard Biener <rguenther@suse.de>
PR tree-optimization/95717
* tree-vect-loop-manip.c (slpeel_tree_duplicate_loop_to_edge_cfg):
Move BB SSA updating before exit/latch PHI current def copying.
Thomas Koenig [Tue, 23 Jun 2020 19:59:47 +0000 (21:59 +0200)]
Make forall statement in testsuite conforming.
The recent patch for dependency checking introduced one failing test
case for pointer assignments in a forall statement. This test case
was invalid because of an interdependency in a forall statement.
This patch fixes that by removing that dependency.
gcc/testsuite/ChangeLog:
2020-06-23 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/95812
* gfortran.fortran-torture/execute/forall_5.f90: Make forall
statement conforming.
Eric Botcazou [Tue, 23 Jun 2020 16:33:28 +0000 (18:33 +0200)]
Fix memory corruption with vector and variant record
The problem is that Has_Constrained_Partial_View must be tested on the
base type of the designated type of an allocator.
gcc/ada/ChangeLog:
* gcc-interface/trans.c (gnat_to_gnu) <N_Allocator>: Minor tweaks.
Call Has_Constrained_Partial_View on base type of designated type.
Richard Biener [Thu, 4 Jun 2020 11:44:58 +0000 (13:44 +0200)]
middle-end/95493 - bogus MEM_ATTRS for variable array access
The following patch avoids keeping the inherited MEM_ATTRS when
set_mem_attributes_minus_bitpos is called with a variable ARRAY_REF.
The inherited ones may not reflect the correct offset and neither
does the updated alias-set match the inherited MEM_EXPR. This all
ends up confusing path-based alias-analysis, causing wrong-code.
The fix is to stop not adopting a MEM_EXPR for certain kinds of
expressions and instead handle everything we can. There's still
the constant kind trees case which I'm too lazy to look into right
now. I did refrain from adding SSA_NAME there and instead avoided
calling set_mem_attributes_minus_bitpos when debug expression
expansion ended up expanding a SSA definition RHS which should
already have taken care of setting the appropriate MEM_ATTRS.
It also avoids calling set_mem_attributes on the
DECL_INITIAL of a CONST_DECL which seems pointless since there
cannot be a sensible MEM_EXPR derived from that. We're overwriting
both other possibly useful info, alias-set and alignment immediately
so the following patch simply removes the call instead of making
the function deal with even more (unexpected) trees that are not
memory accesses.
2020-06-23 Richard Biener <rguenther@suse.de>
PR middle-end/95493
PR middle-end/95690
* cfgexpand.c (expand_debug_expr): Avoid calling
set_mem_attributes_minus_bitpos when we were expanding
an SSA name.
* emit-rtl.c (set_mem_attributes_minus_bitpos): Remove
ARRAY_REF special-casing, add CONSTRUCTOR to the set of
special-cases we do not want MEM_EXPRs for. Assert
we end up with reasonable MEM_EXPRs.
* varasm.c (build_constant_desc): Remove set_mem_attributes call.
* g++.dg/torture/pr95493.C: New testcase.
* g++.dg/torture/pr95493-1.C: Likewise.
* gfortran.dg/pr95690.f90: Likewise.
Thomas Koenig [Tue, 23 Jun 2020 06:14:51 +0000 (08:14 +0200)]
Handle AR_FULL vs. AR_FULL in dependency checking.
Previously, handling of full vs. full references failed to take
AR_FULL vs. AR_FULL into account. A change in dependency
checking in gcc 10 created a code path that could lead there;
with this patch, this is now correctly handled.
gcc/fortran/ChangeLog:
2020-06-23 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/95812
* dependency.c (ref_same_as_full_array): Handle case of AR_FULL
vs. AR_FULL.
gcc/testsuite/ChangeLog:
2020-06-23 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/95812
* gfortran.dg/dependency_59.f90: New test.
Richard Biener [Tue, 19 May 2020 05:58:33 +0000 (07:58 +0200)]
c/95141 - fix bogus integer overflow warning
This fixes an integer overflow warning that ultimatively happens because
of TREE_OVERFLOW propagating through transforms and the existing guard
against this,
being insufficient. Rather than trying to use sth like walk_tree to
exhaustively walk operands (with the possibility of introducing
quadraticness when folding larger expressions recursively) the
following amends the above with an ad-hoc test for a binary op0
with a possibly constant op1.
2020-05-30 Richard Biener <rguenther@suse.de>
PR c/95141
gcc/c
* c-fold.c (c_fully_fold_internal): Enhance guard on
overflow_warning.
Richard Biener [Fri, 15 May 2020 07:38:54 +0000 (09:38 +0200)]
tree-optimization/95133 - avoid abnormal edges in path splitting
When path splitting tries to detect a CFG diamond make sure it
is composed of normal (non-EH, not abnormal) edges. Otherwise
CFG manipulation later may fail.
2020-05-15 Richard Biener <rguenther@suse.de>
PR tree-optimization/95133
* gimple-ssa-split-paths.c
(find_block_to_duplicate_for_splitting_paths): Check for
normal edges.
Richard Biener [Thu, 14 May 2020 06:53:03 +0000 (08:53 +0200)]
middle-end/95118 - fix printing of denormal zero
This fixes printing a REAL_CST generated from value-numbering
punning some bits to a real which turns out as zero with big
negative exponent. This causes the loop in real_to_decimal_for_mode to
never terminate.
2020-05-14 Richard Biener <rguenther@suse.de>
PR middle-end/95118
* real.c (real_to_decimal_for_mode): Make sure we handle
a zero with nonzero exponent.
Richard Biener [Wed, 6 May 2020 08:23:15 +0000 (10:23 +0200)]
middle-end/94964 - avoid EH loop entry with CP_SIMPLE_PREHEADERS
Loop optimizers expect to be able to insert on the preheader
edge w/o splitting it thus avoid ending up with a preheader
that enters the loop via an EH edge (or an abnormal edge).
Mark Eggleston [Mon, 22 Jun 2020 12:35:01 +0000 (13:35 +0100)]
Fortran : ICE in resolve_fl_procedure PR95708
Now issues an error "Intrinsic procedure 'num_images' not
allowed in PROCEDURE" instead of an ICE.
2020-06-22 Steven G. Kargl <kargl@gcc.gnu.org>
gcc/fortran/
PR fortran/95708
* intrinsic.c (add_functions): Replace CLASS_INQUIRY with
CLASS_TRANSFORMATIONAL for intrinsic num_images.
(make_generic): Replace ACTUAL_NO with ACTUAL_YES for
intrinsic team_number.
* resolve.c (resolve_fl_procedure): Check pointer ts.u.derived
exists before using it.
2020-06-22 Mark Eggleston <markeggleston@gcc.gnu.org>
gcc/testsuite/
PR fortran/95708
* gfortran.dg/pr95708.f90: New test.
Jason Merrill [Fri, 12 Jun 2020 03:58:54 +0000 (23:58 -0400)]
c++: Refinements to "more constrained".
P2113 from the last C++ meeting clarified that we only compare constraints
on functions or function templates that have equivalent template parameters
and function parameters.
I'm not currently implementing the complicated handling of reversed
comparison operators here; thinking about it now, it seems like a lot of
complexity to support a very weird usage. If I write two similar comparison
operators to be distinguished by their constraints, why would I write one
reversed? If they're two unrelated operators, they're very unlikely to be
similar enough for the complexity to help. I've started a discussion on the
committee reflector about changing these rules.
This change breaks some greedy_ops tests in libstdc++ that were relying on
comparing constraints on unrelated templates, which seems pretty clearly
wrong, so I'm removing those tests for now.
gcc/cp/ChangeLog:
* call.c (joust): Only compare constraints for non-template
candidates with matching parameters.
* pt.c (tsubst_pack_expansion): Fix getting a type parameter
pack.
(more_specialized_fn): Only compare constraints for candidates with
matching parameters.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/concepts-return-req1.C: Expect error.
* g++.dg/cpp2a/concepts-p2113a.C: New test.
* g++.dg/cpp2a/concepts-p2113b.C: New test.
Jason Merrill [Mon, 15 Jun 2020 21:11:38 +0000 (17:11 -0400)]
c++: implicit operator== adjustments from P2002.
P2002R1, adopted at the February C++ meeting, made several refinements to
the wording for operator<=>. This implements clarifications in how the
implicit operator== is declared: as a duplicate of the operator<=>, with
only the return type and name changed. To that end I factored out the
declaration copying from build_clone. For GCC 10 I'm leaving build_clone
alone, to reduce the chance of non-C++20-mode regressions.
The decl.c changes are a hack to avoid complaining about constraints on a
non-template friend that isn't defined in the class. In this case the
defaulted comparison operator should be considered defined, but we weren't
setting funcdef_flag properly. For GCC 11 I fixed it properly.
gcc/cp/ChangeLog:
* cp-tree.h (copy_fndecl_with_name): Declare.
* class.c (copy_fndecl_with_name): Copy from build_clone.
(add_implicitly_declared_members): Add op== to TYPE_FIELDS.
* method.c (implicitly_declare_fn): Use copy_fndecl_with_name.
* decl.c (grokfndecl): Add initialized parm.
(grokdeclarator): Pass it down.
Harald Anlauf [Sat, 20 Jun 2020 14:15:16 +0000 (16:15 +0200)]
PR fortran/95707 - ICE in finish_equivalences, at fortran/trans-common.c:1319
With submodules and equivalence declarations, name mangling may result in
long internal symbols overflowing internal buffers. We now check that
we do not exceed the enlarged buffer sizes.
gcc/fortran/
PR fortran/95707
* gfortran.h (gfc_common_head): Enlarge buffer.
* trans-common.c (gfc_sym_mangled_common_id): Enlarge temporary
buffers, and add check on length on mangled name to prevent
overflow.
Harald Anlauf [Sat, 20 Jun 2020 14:14:00 +0000 (16:14 +0200)]
PR fortran/95688 - ICE in gfc_get_string, at fortran/iresolve.c:70
With submodules, name mangling of character pointer declarations produces long
internal symbols that overflowed a static internal buffer. Adjust the buffer
size.
Harald Anlauf [Sat, 20 Jun 2020 14:11:48 +0000 (16:11 +0200)]
PR fortran/95687 - ICE in get_unique_hashed_string, at fortran/class.c:508
With submodules and PDTs, name mangling of interfaces may result in long
internal symbols overflowing a previously static internal buffer. We now
set the buffer size dynamically.
gcc/fortran/
PR fortran/95687
* class.c (get_unique_type_string): Return a string with dynamic
length.
(get_unique_hashed_string, gfc_hash_value): Use dynamic result
from get_unique_type_string instead of static buffer.
Harald Anlauf [Sat, 20 Jun 2020 14:09:45 +0000 (16:09 +0200)]
PR fortran/95689 - ICE in check_sym_interfaces, at fortran/interface.c:2015
With submodules, name mangling of interfaces may result in long internal
symbols overflowing an internal buffer. We now check that we do not
exceed the enlarged buffer size.
gcc/fortran/
PR fortran/95689
* interface.c (check_sym_interfaces): Enlarge temporary buffer,
and add check on length on mangled name to prevent overflow.
Harald Anlauf [Sat, 20 Jun 2020 14:05:13 +0000 (16:05 +0200)]
PR fortran/95587 - ICE in gfc_target_encode_expr, at fortran/target-memory.c:362
EQUIVALENCE objects are subject to constraints listed in the Fortran 2018
standard, section 8.10.1.1. These constraints are to be checked
also for CLASS variables.
gcc/fortran/
PR fortran/95587
* match.c (gfc_match_equivalence): Check constraints on
EQUIVALENCE objects also for CLASS variables.
H.J. Lu [Tue, 12 May 2020 17:39:42 +0000 (10:39 -0700)]
Enable CET in cross compiler if possible
Don't perform CET run-time check for host when cross compiling. Instead,
enable CET in cross compiler if possible so that it will run on both CET
and non-CET hosts.
config/
PR bootstrap/94998
* cet.m4 (GCC_CET_HOST_FLAGS): Enable CET in cross compiler if
possible.
Iain Sandoe [Sun, 21 Jun 2020 18:11:23 +0000 (19:11 +0100)]
coroutines: Update handling and failure for g-r-o-o-a-f [PR95505]
The actual issue is that (in the testcase) std::nothrow is not
available. So update the handling of the get-return-on-alloc-fail
to include the possibility that std::nothrow might not be
available.
gcc/cp/ChangeLog:
PR c++/95505
* coroutines.cc (morph_fn_to_coro): Update handling of
get-return-object-on-allocation-fail and diagnose missing
std::nothrow.
gcc/testsuite/ChangeLog:
PR c++/95505
* g++.dg/coroutines/pr95505.C: New test.
Bin Cheng [Sat, 20 Jun 2020 06:24:31 +0000 (14:24 +0800)]
Add missing unit dependence vector in data dependence analysis
Current data dependence analysis misses unit distant vector if DRs in
DDR have the same invariant access functions. This adds the vector as
the constant access function case.
Also fix typo in testcase.
Backport from master.
2020-06-20 Bin Cheng <bin.cheng@linux.alibaba.com>
gcc/
PR tree-optimization/94969
* tree-data-ref.c (constant_access_functions): Rename to...
(invariant_access_functions): ...this. Add parameter. Check for
invariant access function, rather than constant.
(build_classic_dist_vector): Call above function.
* tree-loop-distribution.c (pg_add_dependence_edges): Add comment.
gcc/testsuite/
PR tree-optimization/94969
* gcc.dg/tree-ssa/pr94969.c: New test.
Jason Merrill [Thu, 18 Jun 2020 21:41:43 +0000 (17:41 -0400)]
c++: Allow defaulted comparison outside class.
Implementing P2085, another refinement to the operator<=> specification from
the Prague meeting. It was deemed desirable to be able to have a non-inline
defaulted definition of a comparison operator just like you can with other
defaulted functions.
gcc/cp/ChangeLog:
* method.c (early_check_defaulted_comparison): Allow defaulting
comparison outside class. Complain if non-member operator isn't a
friend.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/spaceship-friend1.C: New test.
* g++.dg/cpp2a/spaceship-err4.C: Adjust diagnostic.
guojiufu [Thu, 28 May 2020 05:42:23 +0000 (13:42 +0800)]
Introduce flag_cunroll_grow_size for cunroll and avoid enable it at -O2
Currently GIMPLE complete unroller(cunroll) is checking
flag_unroll_loops and flag_peel_loops to see if allow size growth.
Beside affects curnoll, flag_unroll_loops also controls RTL unroler.
To have more freedom to control cunroll and RTL unroller, this patch
introduces flag_cunroll_grow_size. With this patch, we can control
cunroll and RTL unroller indepently. And enable flag_cunroll_grow_size
only if -funroll-loops or -fpeel-loops or -O3 is specified explicitly.
Aaron Sawdey [Wed, 17 Jun 2020 20:35:55 +0000 (15:35 -0500)]
identify lfs prefixed case PR95347
The same problem also arises for plfs where prefixed_load_p()
doesn't recognize it so we get just lfs in the asm output
with an @pcrel address.
Backport from master
2020-06-03 Aaron Sawdey <acsawdey@linux.ibm.com>
PR target/95347
* config/rs6000/rs6000.c (is_stfs_insn): Rename to
is_lfs_stfs_insn and make it recognize lfs as well.
(prefixed_store_p): Use is_lfs_stfs_insn().
(prefixed_load_p): Use is_lfs_stfs_insn() to recognize lfs.
Aaron Sawdey [Wed, 17 Jun 2020 20:32:53 +0000 (15:32 -0500)]
Correctly identify stfs if prefixed
Because reg_to_non_prefixed() only looks at the register being used, it
doesn't get the right answer for stfs, which leads to us not seeing
that it has a PCREL symbol ref. This patch works around this by
introducing a helper function that inspects the insn to see if it is in
fact a stfs. Then if we use NON_PREFIXED_DEFAULT, address_to_insn_form()
can see that it has the PCREL symbol ref.
Backport from master
2020-06-02 Aaron Sawdey <acsawdey@linux.ibm.com>
PR target/95347
* config/rs6000/rs6000.c (prefixed_store_p): Add special case
for stfs.
(is_stfs_insn): New helper function.
As the following testcase shows, the exception for the aarch64
vec_pack_trunc_di is not sufficient on x86, the halfvectype
"vectors" have SImode but the x86 vec_pack_trunc_si meant for
the bool bitmasks combines 2x SImode into DImode, while in the
testcase the halfvectype is 1x SImode "vector" with SImode and
result is 2x HImode "vector" with SImode.
Richard Sandiford's reply:
FWIW, since the aarch64 case was only found by inspection and might
not be useful, personally I'd prefer to drop that case after all.
2020-06-18 Jakub Jelinek <jakub@redhat.com>
PR target/95713
* tree-ssa-forwprop.c (simplify_vector_constructor): Don't allow
scalar mode halfvectype other than vector boolean for
VEC_PACK_TRUNC_EXPR.
[PATCH][GCC] arm: Fix the MVE ACLE vaddq_m polymorphic variants.
Hello,
This patch fixes the MVE ACLE vaddq_m polymorphic variants by modifying the corresponding
intrinsic parameters and vaddq_m polymorphic variant's _Generic case entries in "arm_mve.h"
header file.
This patch modifies the MVE scalar shift RTL patterns. The current patterns
have wrong constraints and predicates due to which the values returned from
MVE scalar shift instructions are overwritten in the code-gen.
+FAIL: libgomp.c/target-39.c (internal compiler error)
+FAIL: libgomp.c/target-39.c (test for excess errors)
+UNRESOLVED: libgomp.c/target-39.c compilation failed to produce executable
This is in a '--enable-offload-targets=[...],hsa' build, with '-foffload=hsa'
enabled (by default).
during GIMPLE pass: hsagen
source-gcc/libgomp/testsuite/libgomp.c/target-39.c: In function ‘main._omp_fn.0.hsa.0’:
source-gcc/libgomp/testsuite/libgomp.c/target-39.c:23:11: internal compiler error: Segmentation fault
23 | #pragma omp target map(from:err)
| ^~~
[...]
GDB:
Program received signal SIGSEGV, Segmentation fault.
fndecl_built_in_p (node=0x0, name=BUILT_IN_PREFETCH) at [...]/source-gcc/gcc/tree.h:6267
6267 return (fndecl_built_in_p (node, BUILT_IN_NORMAL)
(gdb) bt
#0 fndecl_built_in_p (node=0x0, name=BUILT_IN_PREFETCH) at [...]/source-gcc/gcc/tree.h:6267
#1 0x0000000000b19739 in gen_hsa_insns_for_call (stmt=stmt@entry=0x7ffff693b200, hbb=hbb@entry=0x2b152c0) at [...]/source-gcc/gcc/hsa-gen.c:5304
#2 0x0000000000b1aca7 in gen_hsa_insns_for_gimple_stmt (stmt=0x7ffff693b200, hbb=hbb@entry=0x2b152c0) at [...]/source-gcc/gcc/hsa-gen.c:5770
#3 0x0000000000b1bd21 in gen_body_from_gimple () at [...]/source-gcc/gcc/hsa-gen.c:5999
#4 0x0000000000b1dbd2 in generate_hsa (kernel=<optimized out>) at [...]/source-gcc/gcc/hsa-gen.c:6596
#5 0x0000000000b1de66 in (anonymous namespace)::pass_gen_hsail::execute (this=0x2a2aac0) at [...]/source-gcc/gcc/hsa-gen.c:6680
#6 0x0000000000d06f90 in execute_one_pass (pass=pass@entry=0x2a2aac0) at [...]/source-gcc/gcc/passes.c:2502
[...]
(gdb) up
#1 0x0000000000b19739 in gen_hsa_insns_for_call (stmt=stmt@entry=0x7ffff693b200, hbb=hbb@entry=0x2b152c0) at /home/thomas/tmp/source/gcc/build/track-slim-omp/source-gcc/gcc/hsa-gen.c:5304
5304 if (fndecl_built_in_p (function_decl, BUILT_IN_PREFETCH))
(gdb) print function_decl
$1 = (tree) 0x0
(gdb) list
5299 if (!gimple_call_builtin_p (stmt, BUILT_IN_NORMAL))
5300 {
5301 tree function_decl = gimple_call_fndecl (stmt);
5302 /* Prefetch pass can create type-mismatching prefetch builtin calls which
5303 fail the gimple_call_builtin_p test above. Handle them here. */
5304 if (fndecl_built_in_p (function_decl, BUILT_IN_PREFETCH))
5305 return;
5306
5307 if (function_decl == NULL_TREE)
5308 {
The problem is present already since 2016-11-23 commit 56b1c60e412fcf1245b4780871553cbdebb956a3 (r242761) "Merge from HSA branch to
trunk", and the fix obvious enough.
Harald Anlauf [Sun, 14 Jun 2020 14:12:47 +0000 (16:12 +0200)]
PR fortran/95088 - Buffer overflows with PDTs, submodules and long symbols
With PDTs (parameterized derived types) and submodules, name mangling
results in variably long internal symbols. Instead of using a fixed-size
intermediate buffer, which is actually not really needed, just use a
pointer to strings.
2020-06-14 Harald Anlauf <anlauf@gmx.de>
gcc/fortran/
PR fortran/95088
* class.c (get_unique_type_string): Replace use of fixed size
buffer by internally passing a pointer to strings.
Marek Polacek [Wed, 17 Jun 2020 18:38:05 +0000 (14:38 -0400)]
c++: ICE with IMPLICIT_CONV_EXPR in array subscript [PR95508]
Since r10-7096 convert_like, when called in a template, creates an
IMPLICIT_CONV_EXPR when we're converting to/from array type.
In this test, we have e[f], and we're converting f (of type class A) to
int, so convert_like in build_new_op_1 created the IMPLICIT_CONV_EXPR
that got into cp_build_array_ref which calls maybe_constant_value. My
patch above failed to adjust this spot to call fold_non_dependent_expr
instead, which can handle codes like I_C_E in a template. Fixed by
using a new function maybe_fold_non_dependent_expr, which, if the expr
can't be evaluated to a constant, returns the original expression.
arm: Correct the grouping of operands in MVE vector scatter store intrinsics (PR94735).
The operands in RTL patterns of MVE vector scatter store intrinsics are
wrongly grouped, because of which few vector loads and stores instructions
are wrongly getting optimized out with -O2.
A new predicate "mve_scatter_memory" is defined in this patch, this predicate
returns TRUE on matching: (mem(reg)) for MVE scatter store intrinsics.
This patch fixes the issue by adding define_expand pattern with
"mve_scatter_memory" predicate and calls the corresponding define_insn by
passing register_operand as first argument. This register_operand is extracted
from the operand with "mve_scatter_memory" predicate in define_expand pattern.
Backported from mainline
2020-06-04 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
arm: Fix the wrong code-gen generated by MVE vector load/store intrinsics (PR94959).
Few MVE intrinsics like vldrbq_s32, vldrhq_s32 etc., the assembler instructions
generated by current compiler are wrong.
eg: vldrbq_s32 generates an assembly instructions `vldrb.s32 q0,[ip]`.
But as per Arm-arm second argument in above instructions must also be a low
register (<= r7). This patch fixes this issue by creating a new predicate
"mve_memory_operand" and constraint "Ux" which allows low registers as arguments
to the generated instructions depending on the mode of the argument. A new constraint
"Ul" is created to handle loading to PC-relative addressing modes for vector
store/load intrinsiscs.
All the corresponding MVE intrinsic generating wrong code-gen as vldrbq_s32
are modified in this patch.
Backported from mainline
2020-05-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
gcc/
PR target/94959
* config/arm/arm-protos.h (arm_mode_base_reg_class): Function
declaration.
(mve_vector_mem_operand): Likewise.
* config/arm/arm.c (thumb2_legitimate_address_p): For MVE target check
the load from memory to a core register is legitimate for give mode.
(mve_vector_mem_operand): Define function.
(arm_print_operand): Modify comment.
(arm_mode_base_reg_class): Define.
* config/arm/arm.h (MODE_BASE_REG_CLASS): Modify to add check for
TARGET_HAVE_MVE and expand to arm_mode_base_reg_class on TRUE.
* config/arm/constraints.md (Ux): Likewise.
(Ul): Likewise.
* config/arm/mve.md (mve_mov): Replace constraint Us with Ux and also
add support for missing Vector Store Register and Vector Load Register.
Add a new alternative to support load from memory to PC (or label) in
vector store/load.
(mve_vstrbq_<supf><mode>): Modify constraint Us to Ux.
(mve_vldrbq_<supf><mode>): Modify constriant Us to Ux, predicate to
mve_memory_operand and also modify the MVE instructions to emit.
(mve_vldrbq_z_<supf><mode>): Modify constraint Us to Ux.
(mve_vldrhq_fv8hf): Modify constriant Us to Ux, predicate to
mve_memory_operand and also modify the MVE instructions to emit.
(mve_vldrhq_<supf><mode>): Modify constriant Us to Ux, predicate to
mve_memory_operand and also modify the MVE instructions to emit.
(mve_vldrhq_z_fv8hf): Likewise.
(mve_vldrhq_z_<supf><mode>): Likewise.
(mve_vldrwq_fv4sf): Likewise.
(mve_vldrwq_<supf>v4si): Likewise.
(mve_vldrwq_z_fv4sf): Likewise.
(mve_vldrwq_z_<supf>v4si): Likewise.
(mve_vld1q_f<mode>): Modify constriant Us to Ux.
(mve_vld1q_<supf><mode>): Likewise.
(mve_vstrhq_fv8hf): Modify constriant Us to Ux, predicate to
mve_memory_operand.
(mve_vstrhq_p_fv8hf): Modify constriant Us to Ux, predicate to
mve_memory_operand and also modify the MVE instructions to emit.
(mve_vstrhq_p_<supf><mode>): Likewise.
(mve_vstrhq_<supf><mode>): Modify constriant Us to Ux, predicate to
mve_memory_operand.
(mve_vstrwq_fv4sf): Modify constriant Us to Ux.
(mve_vstrwq_p_fv4sf): Modify constriant Us to Ux and also modify the MVE
instructions to emit.
(mve_vstrwq_p_<supf>v4si): Likewise.
(mve_vstrwq_<supf>v4si): Likewise.Modify constriant Us to Ux.
* config/arm/predicates.md (mve_memory_operand): Define.
git://gcc.gnu.org / gcc.git / log