Jakub Jelinek [Sat, 29 Oct 2016 20:22:36 +0000 (22:22 +0200)]
re PR rtl-optimization/77919 (ICE converting DC to V2DF mode)
PR rtl-optimization/77919
* expr.c (expand_expr_real_1) <normal_inner_ref>: Only avoid forcing
into memory if both modes are complex and their inner modes have the
same precision. If the two modes are different complex modes, convert
each part separately and generate a new CONCAT.
Jakub Jelinek [Sat, 29 Oct 2016 15:55:50 +0000 (17:55 +0200)]
re PR tree-optimization/78148 (r241649 causes -fcompare-debug failure on ppc64le)
PR target/78148
* gimple-ssa-store-merging.c
(imm_store_chain_info::output_merged_store): Use build_aligned_type
instead of SET_TYPE_ALIGN on shared integral type.
Ian Lance Taylor [Fri, 28 Oct 2016 22:34:47 +0000 (22:34 +0000)]
compiler, runtime: copy slice code from Go 1.7 runtime
Change the compiler handle append as the gc compiler does: call a
function to grow the slice, but otherwise assign the new elements
directly to the final slice.
For the current gccgo memory allocator the slice code has to call
runtime_newarray, not mallocgc directly, so that the allocator sets the
TypeInfo_Array bit in the type pointer.
Rename the static function cnew to runtime_docnew, so that the stack
trace ignores it when ignoring runtime functions. This was needed to
fix the runtime/pprof tests on 386.
This improves a few things in change_zero_ext. Firstly, it should use
the passed in pattern in recog_for_combine, not the pattern of the insn
(they are not the same if the whole pattern was replaced). Secondly,
it handled zero_ext of a subreg, but with hard registers we do not get
a subreg, instead the mode of the reg is changed. So this handles that.
Thirdly, after changing a zero_ext to an AND, the resulting RTL may become
non-canonical, like (ior (ashift ..) (and ..)); the AND should be first,
it is commutative. And lastly, zero_extract as a set_dest wasn't handled
at all, but now it is.
This fixes the testcase in PR71847, and improves code generation in some
other edge cases too.
PR target/71847
* combine.c (change_zero_ext): Handle zero_ext of hard registers.
Swap commutative operands in new RTL if needed. Handle zero_ext
in the set_dest.
(recog_for_combine): Pass *pnewpat to change_zero_ext instead of
PATTERN (insn).
Ian Lance Taylor [Fri, 28 Oct 2016 20:21:52 +0000 (20:21 +0000)]
re PR go/78144 (FAIL: time on systems with tzdata2016g installed)
PR go/78144
libgo: incorporate fix for timezone test
This brings over the test-only fix for issue 17276 into gccgo/libgo
(with tzdata-2016g there is a new zone abbreviation). This is a
copy of https://golang.org/cl/29995.
Jonathan Wakely [Fri, 28 Oct 2016 18:48:43 +0000 (19:48 +0100)]
Make filesystem::path work with basic_string_view (P0392R0)
* include/experimental/bits/fs_path.h (__is_path_src)
(_S_range_begin, _S_range_end): Overload to treat string_view as a
Source object.
(path::operator+=, path::compare): Overload for basic_string_view.
* testsuite/experimental/filesystem/path/construct/string_view.cc:
New test.
* testsuite/experimental/filesystem/path/construct/
string_view_cxx17.cc: New test.
Eric Botcazou [Fri, 28 Oct 2016 18:10:14 +0000 (18:10 +0000)]
dojump.c (do_jump_by_parts_greater_rtx): Invert probability when swapping the arms of the branch.
* dojump.c (do_jump_by_parts_greater_rtx): Invert probability when
swapping the arms of the branch.
* internal-fn.c (expand_addsub_overflow): Use a straight-line code
sequence for the generic signed-signed-signed case.
Jonathan Wakely [Fri, 28 Oct 2016 17:47:57 +0000 (18:47 +0100)]
Fix filesystem::path for iterators with const value_type
* include/experimental/bits/fs_path.h
(path::_S_convert<_Iter>(_Iter, _Iter)): Remove cv-qualifiers from
iterator's value_type.
(path::_S_convert<_Iter>(_Iter __first, __null_terminated)): Likewise.
Do not use operation not supported by input iterators.
(path::__is_path_iter_src): Add partial specialization for const
encoded character types.
* testsuite/experimental/filesystem/path/construct/range.cc: Test
construction from input iterators with const value types.
and sched swaps them (when compiling for power6, it tries to put memory
stores together, so insn 310 is moved up past 300 to go together with
some other store). But the REG_CFA_RESTORE and REG_CFA_OFFSET cannot be
swapped (they both say where the orig value of LR now lives).
PR rtl-optimization/78029
* function.c (prologue_contains, epilogue_contains): New functions.
(record_prologue_seq, record_epilogue_seq): New functions.
* function.h (prologue_contains, epilogue_contains,
record_prologue_seq, record_epilogue_seq): New declarations.
* sched-deps.c (sched_analyze_insn): Make dependencies to prevent
mixing prologue and epilogue insns.
(init_deps): Initialize the new fields in struct deps_desc.
* sched-int.h (struct deps_desc): New fields last_prologue,
last_epilogue, and last_logue_was_epilogue.
* shrink-wrap.c (emit_common_heads_for_components): Record all
emitted prologue and epilogue insns.
(emit_common_tails_for_components): Ditto.
(insert_prologue_epilogue_for_components): Ditto.
Andreas Krebbel [Fri, 28 Oct 2016 12:31:37 +0000 (12:31 +0000)]
S/390: Add static OSC breaker if necessary.
This patch adds a magic OSC (operand store compare) break instruction
which is necessary if a store is followed closely by a load with same
base+indx+displ while either base or index get modified in between.
The patch improves several SpecCPU testcases running on IBM z13.
gcc/testsuite/ChangeLog:
2016-10-28 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gcc.target/s390/oscbreak-1.c: New test.
gcc/ChangeLog:
2016-10-28 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/s390.c (s390_adjust_loop_scan_osc): New function.
(s390_adjust_loops): New function.
(s390_reorg): Invoke s390_adjust_loops.
* config/s390/s390.md: (UNSPEC_OSC_BREAK): New constant.
("osc_break"): New insn definition.
Andreas Krebbel [Fri, 28 Oct 2016 12:28:24 +0000 (12:28 +0000)]
S/390: Add support for arch<n> arch/tune options.
This patch adds an alternate CPU level naming following the
architecture level number in the Principles of Operations manual. So
instead of having z196, zEC12, and z13 you can use arch9, arch10, and
arch11. The old cpu names stay valid and should preferably be used.
The alternate names are supposed to improve compatibility with the IBM
XL compiler toolchain which uses the arch numbering.
gcc/testsuite/ChangeLog:
2016-10-28 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gcc.target/s390/target-attribute/tattr-m64-33.c: New test.
gcc/ChangeLog:
2016-10-28 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/s390.opt: Support alternate cpu level naming (archXX).
* config.gcc: Support alternate archXX cpu levels with
--with-arch= and --with-tune=.
* config/s390/linux.h: Translate new archXX cpu levels to the
original names when calling GAS.
* config/s390/tpf.h: Likewise.
* doc/invoke.texi: Document the alternate cpu level names.
Michael Meissner [Thu, 27 Oct 2016 20:52:07 +0000 (20:52 +0000)]
constraints.md (wH constraint): Add new constraints for allowing 32-bit integers (and eventually 8/16-bit...
[gcc]
2016-10-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/constraints.md (wH constraint): Add new
constraints for allowing 32-bit integers (and eventually 8/16-bit
integers) into the vector registers.
(wI constraint): Likewise.
(wJ constraint): Likewise.
(wK constraint): Likewise.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add
-mvsx-small-integer as a default option for ISA 2.07
(i.e. power8).
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.opt (-mvsx-small-integer): Add new debug
switch to turn off small integer support in vector registers.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Eliminate
test for -mupper-regs-di, since it is already done with the
reg_add[mode].scalar_in_vsx_p. Add support for the switch
-mvsx-small-integer.
(rs6000_debug_reg_global): Add support for wH, wI, wJ, and wK
constraints.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_option_override_internal): Add consistency checks for
-mvsx-small-integer.
(rs6000_secondary_reload_simple_move): SImode is a simple move if
-mvsx-small-integer.
(rs6000_secondary_reload): Use std::swap.
(rs6000_preferred_reload_class): Don't prefer FLOAT_REGS over
VSX_REGS for small integers in vector registers, since there is no
D-FORM address mode for such types.
(rs6000_register_move_cost): Use FIRST_FPR_REGNO instead of 32.
(rs6000_opt_masks): Add -mvsx-small-integer.
* config/rs6000/vsx.md (VSINT_84): Add SImode for small integer
support.
(VSX_EXTRACT_I2): Clone VSX_EXTRACT_I, but drop V4SI since SImode
extracts can be done on ISA 2.07.
(vsx_extract_<mode>): Add support for small integers in vsx
registers.
(vsx_extract_<mode>_p9): Use 'v' instead of VSX_EX, since we no
longer support V4SImode in this pattern.
(vsx_extract_si): New insn to support extraction of SImode in ISA
2.07 using either xxextractuw or vspltw.
(vsx_extract_<mode>_p8): Use 'v' instead of VSX_EX, since we no
longer support V4SImode in this pattern.
* config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wH, wI,
wJ, and wK constraints.
* config/rs6000/rs6000.md (f32_sv): Use correct instruction for
storing SDmode with VSX instructions.
(zero_extendsi<mode>2): Reorder pattern, so RLDICL comes after the
GPR load and before the FPR and VSX loads. Remove ??, ! from the
constraints. Add MFVSRWZ and XXEXTRACTUW instructions to support
small integers in vector registers.
(extendsi<mode>2): Reorder pattern, so EXTSW comes after the GPR
load and before the FPR and VSX loads. Remove ??, ! from the
constraints. Add VEXTSW2D support for small integers in vector
registers.
(lfiwax): Remove ! constraint. Add VEXTSW2D support for small
integers in vector registers.
(floatsi<mode>2_lfiwax): If -mvsx-small-integer issue a normal
move instead of using an UNSPEC.
(lfiwzx): Remove ! constraint. Add XXEXTRACTUW support for small
integers in vector registers.
(floatunssi<mode>2_lfiwzx): If -mvsx-small-integer issue a normal
move instead of using an UNSPEC.
(movsi_internal1): Add support for -mvsx-small-integer. Align
columns so that it is more readable.
(SImode splitter for ISA 3.0 constants): Add splitter for
-128..127 constants that can easily be constructed on ISA 3.0.
* doc/md.texi (PowerPC Constraints): Document wH, wI, wJ, and wK
constraints.
[gcc/testsuite]
2016-10-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vsx-simode.c: New test.
* gcc.target/powerpc/vsx-simode2.c: Likewise.
* gcc.target/powerpc/vsx-simode3.c: Likewise.
Jakub Jelinek [Thu, 27 Oct 2016 19:55:12 +0000 (21:55 +0200)]
re PR fortran/78026 (ICE in gfc_resolve_omp_declare_simd, at fortran/openmp.c:5190)
PR fortran/78026
* parse.c (decode_statement): Don't create namespace for possible
select type here and destroy it afterwards.
(parse_select_type_block): Set gfc_current_ns to new_st.ext.block.ns.
(parse_executable, gfc_parse_file): Formatting fixes.
* match.c (gfc_match_select_type): Create namespace for select type
here, only after matching select type. Formatting fixes. Free that
namespace if not returning MATCH_YES, after gfc_undo_symbols,
otherwise remember it in new_st.ext.block.ns and switch to parent
namespace anyway.
* gfortran.dg/gomp/pr78026.f03: New test.
* gfortran.dg/select_type_38.f03: New test.
Jonathan Wakely [Thu, 27 Oct 2016 11:01:49 +0000 (12:01 +0100)]
Adjust precision of filesystem::last_write_time tests
* testsuite/experimental/filesystem/iterators/directory_iterator.cc:
Use end() function to get end iterator.
* testsuite/experimental/filesystem/iterators/pop.cc: Remove printf
statements that were present for debugging.
* testsuite/experimental/filesystem/iterators/
recursive_directory_iterator.cc: Use end() function to get end
iterator.
* testsuite/experimental/filesystem/operations/last_write_time.cc:
Only require file timestamps to be accurate to one second.
2016-10-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm.c (arm_split_atomic_op): Add function comment. Add
logic to to decide whether to copy over old value to register for new
value.
* config/arm/sync.md: Add comments explaning why mode and code
attribute are not defined in iterators.md
(thumb1_atomic_op_str): New code attribute.
(thumb1_atomic_newop_str): Likewise.
(thumb1_atomic_fetch_op_str): Likewise.
(thumb1_atomic_fetch_newop_str): Likewise.
(thumb1_atomic_fetch_oldop_str): Likewise.
(atomic_exchange<mode>): Add new ARMv8-M Baseline only alternatives to
mirror the more restrictive constraints of the Thumb-1 insns after
split compared to Thumb-2 counterpart insns.
(atomic_<sync_optab><mode>): Likewise. Add comment to keep constraints
in sync with non atomic version.
(atomic_nand<mode>): Likewise.
(atomic_fetch_<sync_optab><mode>): Likewise.
(atomic_fetch_nand<mode>): Likewise.
(atomic_<sync_optab>_fetch<mode>): Likewise.
(atomic_nand_fetch<mode>): Likewise.
* config/arm/thumb1.md (thumb1_addsi3): Add comment to keep contraint
in sync with atomic version.
(thumb1_subsi3_insn): Likewise.
(thumb1_andsi3_insn): Likewise.
(thumb1_iorsi3_insn): Likewise.
(thumb1_xorsi3_insn): Likewise.
Kelvin Nilsen [Wed, 26 Oct 2016 20:19:39 +0000 (20:19 +0000)]
re PR target/78056 (build failure on Power7)
gcc/ChangeLog:
2016-10-26 Kelvin Nilsen <kelvin@gcc.gnu.org>
PR target/78056
* config/rs6000/rs6000.c (spe_init_builtins): Modify loops to not
define builtin functions from the bdesc_spe_predicates or
bdesc_spe_evsel arrays if the builtin mask is not compatible with
the current compiler configuration.
(paired_init_builtins): Modify loop to not define define builtin
functions from the bdesc_paried_preds array if the builtin mask is
not compatible with the current compiler configuration.
(altivec_init_builtins): Modify loops to not define the
__builtin_altivec_stxvl function nor the builtin functions from
the bdesc_dst or bdesc_altivec_preds, or bdesc_abs arrays if the
builtin mask is not compatible with the current compiler
configuration.
Jakub Jelinek [Wed, 26 Oct 2016 16:21:56 +0000 (18:21 +0200)]
re PR fortran/77973 (ICE in scan_omp_1_op, at omp-low.c:3841)
PR fortran/77973
* gimplify.c (gimplify_adjust_omp_clauses_1): For all added map
clauses with OMP_CLAUSE_SIZE being a decl, call omp_notice_variable
on outer context if any.
* gfortran.dg/gomp/pr77973.f90: New test.
Co-Authored-By: Martin Liska <mliska@suse.cz>
From-SVN: r241581
Jakub Jelinek [Wed, 26 Oct 2016 16:20:54 +0000 (18:20 +0200)]
gen-pass-instances.awk (adjust_linenos): INcrement pass_lines[p] by increment rather than double it.
* gen-pass-instances.awk (adjust_linenos): INcrement pass_lines[p]
by increment rather than double it.
(insert_remove_pass): Strip leading whitespace from args[3]. Don't
emit a space before args[4].
(END): Don't emit a space before with_arg.
2016-10-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/sync.md (atomic_compare_and_swap<mode>_1): Add new ARMv8-M
Baseline only alternatives to (i) hold store atomic success value in a
return register rather than a scratch register, (ii) use a low register
for it and to (iii) ensure the cbranchsi insn generated by the split
respect the constraints of Thumb-1 cbranchsi4_insn and
cbranchsi4_scratch.
* config/arm/thumb1.md (cbranchsi4_insn): Add comment to indicate
constraints must match those in atomic_compare_and_swap.
(cbranchsi4_scratch): Likewise.
Refactor atomic compare_and_swap to make it fit for ARMv8-M Baseline
2016-10-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm.c (arm_expand_compare_and_swap): Add new bdst local
variable. Add the new parameter to the insn generator. Set that
parameter to be CC flag for 32-bit targets, bval otherwise. Set the
return value from the negation of that parameter for Thumb-1, keeping
the logic unchanged otherwise except for using bdst as the destination
register of the compare_and_swap insn.
(arm_split_compare_and_swap): Add explanation about how is the value
returned to the function comment. Rename scratch variable to
neg_bval. Adapt initialization of variables holding operands to the
new operand numbers. Use return register to hold result of store
exclusive for Thumb-1, scratch register otherwise. Construct the
appropriate cbranch for Thumb-1 targets, keeping the logic unchanged
for 32-bit targets. Guard Z flag setting to restrict to 32bit targets.
Use gen_cbranchsi4 rather than hand-written conditional branch to loop
for strongly ordered compare_and_swap.
* config/arm/predicates.md (cc_register_operand): New predicate.
* config/arm/sync.md (atomic_compare_and_swap<mode>_1): Use a
match_operand with the new predicate to accept either the CC flag or a
destination register for the boolean return value, restricting it to
CC flag only via constraint. Adapt operand numbers accordingly.
Paul Thomas [Wed, 26 Oct 2016 14:48:02 +0000 (14:48 +0000)]
re PR fortran/78108 (Generic type-bound operator conflicts)
2016-10-26 Paul Thomas <pault@gcc.gnu.org>
PR fortran/78108
* resolve.c (resolve_typebound_intrinsic_op): For submodules
suppress the error and return if the same procedure symbol
is added more than once to the interface.
2016-10-26 Paul Thomas <pault@gcc.gnu.org>
PR fortran/78108
* gfortran.dg/submodule_18.f08: New test.
* gfortran.dg/submodule_19.f08: New test.
Jonathan Wakely [Wed, 26 Oct 2016 13:34:34 +0000 (14:34 +0100)]
Fix error handling in recursive_directory_iterator::increment
* src/filesystem/dir.cc (recursive_directory_iterator::increment):
Reset state on error.
* testsuite/experimental/filesystem/iterators/
recursive_directory_iterator.cc: Check state after increment error.
Michael Matz [Wed, 26 Oct 2016 12:54:30 +0000 (12:54 +0000)]
fix pr78060 pr78061 pr78088
PR tree-optimization/78060
PR tree-optimization/78061
PR tree-optimization/78088
* tree-ssa-loop-split.c (easy_exit_values): New function.
(tree_ssa_split_loops): Use it.
(compute_new_first_bound): Change order of operations,
fix invalid use of types.
testsuite/
* g++.dg/pr78060.C: New test.
* gfortran.dg/pr78061.f: New test.
* g++.dg/pr78088.C: New test.
libgfortran/io/
* libgfortran.h (IOPARM_OPEN_HAS_READONLY, IOPARM_OPEN_HAS_SHARE,
IOPARM_OPEN_HAS_CC): New for READONLY, SHARE, and CARRIAGECONTROL.
* close.c (st_close): Support READONLY.
* io.h (st_parameter_open, unit_flags): Support SHARE, CARRIAGECONTROL,
and READONLY.
* open.c (st_open): Ditto.
* transfer.c (data_transfer_init): Ditto.
* io.h (st_parameter_dt): New member 'cc' for CARRIAGECONTROL.
* write.c (write_check_cc, write_cc): New functions for CARRIAGECONTROL.
* transfer.c (next_record_cc): Ditto.
* file_pos.c (st_endfile): Support SHARE and CARRIAGECONTROL.
* io.h (st_parameter_inquire): Ditto.
* open.c (edit_modes, new_unit): Ditto.
* inquire.c (inquire_via_unit, inquire_via_filename): Ditto.
* io.h (unit_share, unit_cc, cc_fortran, IOPARM_INQUIRE_HAS_SHARE,
IOPARM_INQUIRE_HAS_CC): New for SHARE and CARRIAGECONTROL.
* open.c (share_opt, cc_opt): Ditto.
* read.c (read_x): Support CARRIAGECONTROL.
* transfer.c (read_sf, next_record_r, next_record_w): Ditto.
* write.c (list_formatted_write_scalar, write_a): Ditto.
* unix.h (close_share): New prototype.
* unix.c (open_share, close_share): New functions to handle SHARE.
* unix.c (open_external): Handle READONLY. Call open_share.
* close.c (st_close): Call close_share.
gcc/testsuite/
* dec_io_1.f90: New test.
* dec_io_2.f90: New test.
* dec_io_3.f90: New test.
* dec_io_4.f90: New test.
* dec_io_5.f90: New test.
* dec_io_6.f90: New test.
Georg-Johann Lay [Wed, 26 Oct 2016 09:46:44 +0000 (09:46 +0000)]
gen-pass-instances.awk is sensitive to the order in which passes are added...
gen-pass-instances.awk is sensitive to the order in which
passes are added; passes that appear later have to be added first.
PR target/71676
PR target/71678
* config/avr/avr-passes.def: Swap order of directives for
gen-pass-instances.awk.