Janne Blomqvist [Mon, 19 Dec 2016 16:20:09 +0000 (18:20 +0200)]
Remove unused functions, take 2.
2016-12-19 Janne Blomqvist <jb@gcc.gnu.org>
* Actually remove files that should have been removed by r243799.
This line, and those below, will be ignored--
M libgfortran/ChangeLog
D libgfortran/generated/exponent_r10.c
D libgfortran/generated/exponent_r16.c
D libgfortran/generated/exponent_r4.c
D libgfortran/generated/exponent_r8.c
D libgfortran/generated/fraction_r10.c
D libgfortran/generated/fraction_r16.c
D libgfortran/generated/fraction_r4.c
D libgfortran/generated/fraction_r8.c
D libgfortran/generated/nearest_r10.c
D libgfortran/generated/nearest_r16.c
D libgfortran/generated/nearest_r4.c
D libgfortran/generated/nearest_r8.c
D libgfortran/generated/rrspacing_r10.c
D libgfortran/generated/rrspacing_r16.c
D libgfortran/generated/rrspacing_r4.c
D libgfortran/generated/rrspacing_r8.c
D libgfortran/generated/set_exponent_r10.c
D libgfortran/generated/set_exponent_r16.c
D libgfortran/generated/set_exponent_r4.c
D libgfortran/generated/set_exponent_r8.c
D libgfortran/generated/spacing_r10.c
D libgfortran/generated/spacing_r16.c
D libgfortran/generated/spacing_r4.c
D libgfortran/generated/spacing_r8.c
D libgfortran/generated/transpose_c10.c
D libgfortran/generated/transpose_c16.c
D libgfortran/generated/transpose_c4.c
D libgfortran/generated/transpose_c8.c
D libgfortran/generated/transpose_i16.c
D libgfortran/generated/transpose_i4.c
D libgfortran/generated/transpose_i8.c
D libgfortran/generated/transpose_r10.c
D libgfortran/generated/transpose_r16.c
D libgfortran/generated/transpose_r4.c
D libgfortran/generated/transpose_r8.c
D libgfortran/intrinsics/malloc.c
D libgfortran/intrinsics/transpose_generic.c
D libgfortran/m4/exponent.m4
D libgfortran/m4/fraction.m4
D libgfortran/m4/nearest.m4
D libgfortran/m4/rrspacing.m4
D libgfortran/m4/set_exponent.m4
D libgfortran/m4/spacing.m4
D libgfortran/m4/transpose.m4
Janne Blomqvist [Mon, 19 Dec 2016 15:32:17 +0000 (17:32 +0200)]
Remove unused libgfortran functions
Now that the libgfortran ABI major version has been bumped, we can
remove functions for which the frontend nowadays generates inline
code.
This removes the malloc, free, exponent, fraction, nearest, rrspacing,
spacing, set_exponent and transpose intrinsics. Also the unused
store_exe_path function is removed.
David Malcolm [Mon, 19 Dec 2016 15:24:47 +0000 (15:24 +0000)]
print-rtl.c: use '<' and '>' rather than % for pseudos in compact mode
gcc/ChangeLog:
* print-rtl.c (rtx_writer::print_rtx_operand_code_r): For
non-virtual pseudos in compact mode, wrap the regno in '<' and '>'
rather than using a '%' prefix.
* rtl-tests.c (selftest::test_dumping_regs): Update for above change.
Make the perfect-forwarding constructor of a two-element tuple sfinae away when the first argument is an allocator_arg.
Make the perfect-forwarding constructor of a two-element tuple
sfinae away when the first argument is an allocator_arg.
* include/std/tuple (tuple(_U1&&, _U2&&)): Constrain.
* testsuite/20_util/tuple/cons/allocator_with_any.cc: New.
* testsuite/20_util/tuple/element_access/get_neg.cc: Adjust.
Janus Weil [Mon, 19 Dec 2016 10:26:04 +0000 (11:26 +0100)]
re PR fortran/78545 (Possible correction to online LTIME documentation)
2016-12-19 Janus Weil <janus@gcc.gnu.org>
PR fortran/78545
* intrinsic.texi: Minor documentation fixes for non-standard
time-related intrinsics. Add references to standard intrinsics and
linkify some existing references.
* lra-constraints.c (process_address): Add forward declaration.
(simplify_operand_subreg): In the MEM case, if the adjusted memory
reference is not sufficient aligned and the address was invalid,
reload the address before reloading the original memory reference.
Fix long lines and add a final return for the sake of clarity.
Jakub Jelinek [Sat, 17 Dec 2016 19:10:39 +0000 (20:10 +0100)]
re PR sanitizer/78832 (-fcompare-debug failure (length) with -fsanitize=address)
PR sanitizer/78832
* sanopt.c (sanitize_asan_mark_unpoison): Remove next variable, use
continue if gsi_next should be skipped.
(sanitize_asan_mark_poison): Remove prev variable, use continue if
gsi_prev should be skipped. When removing ASAN_MARK, do gsi_prev
first and gsi_remove on a previously made copy of the iterator.
Uros Bizjak [Sat, 17 Dec 2016 11:05:46 +0000 (12:05 +0100)]
i386.md (*tzcnt<mode>_1): Merge *tzcnt<mode>_1_falsedep_1 and *tzcnt<mode>_1 to define_insn_and_split pattern.
* config/i386/i386.md (*tzcnt<mode>_1): Merge *tzcnt<mode>_1_falsedep_1
and *tzcnt<mode>_1 to define_insn_and_split pattern. Adjust split
condition to split after epilogue_completed.
(ctz<mode>2): Remove expander.
(ctz<mode>2): Merge *ctz<mode>2_falsedep_1 and *ctz<mode>2 to
define_insn_and_split pattern. Adjust split condition to split
after epilogue_completed.
(clz<mode>2_lznct): Remove expander.
(clz<mode>2_lzcnt): Merge *clz<mode>2_lzcnt_falsedep_1 and
*clz<mode>2 to define_insn_and_split pattern. Adjust split
condition to split after epilogue_completed.
(<lt_zcnt>_<mode>): Remove expander.
(<lt_zcnt>_<mode>): Merge *<lt_zcnt>_<mode>_falsedep_1 and
*<lt_zcnt>_<mode> to define_insn_and_split pattern. Adjust split
condition to split after epilogue_completed.
(<lt_zcnt>_hi): New insn pattern.
(popcount<mode>2): Remove expander.
(popcount<mode>2): Merge *popcount<mode>2_falsedep_1 and
*popcount<mode>2 to define_insn_and_split pattern. Adjust split
condition to split after epilogue_completed.
(popcounthi2): New insn pattern.
Kelvin Nilsen [Sat, 17 Dec 2016 00:18:32 +0000 (00:18 +0000)]
byte-in-either-range-0.c: New test.
gcc/testsuite/ChangeLog:
2016-12-16 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/byte-in-either-range-0.c: New test.
* gcc.target/powerpc/byte-in-either-range-1.c: New test.
* gcc.target/powerpc/byte-in-range-0.c: New test.
* gcc.target/powerpc/byte-in-range-1.c: New test.
* gcc.target/powerpc/byte-in-set-0.c: New test.
* gcc.target/powerpc/byte-in-set-1.c: New test.
* gcc.target/powerpc/byte-in-set-2.c: New test.
gcc/ChangeLog:
2016-12-16 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/altivec.md (UNSPEC_CMPRB): New unspec value.
(UNSPEC_CMPRB2): New unspec value.
(UNSPEC_CMPEQB): New unspec value.
(cmprb): New expansion.
(*cmprb_internal): New insn.
(*setb_internal): New insn.
(cmprb2): New expansion.
(*cmprb2_internal): New insn.
(cmpeqb): New expansion.
(*cmpeqb_internal): New insn.
* config/rs6000/rs6000-builtin.def (BU_P9_2): New macro.
(BU_P9_64BIT_2): Likewise.
(BU_P9_OVERLOAD_2): Likewise.
(CMPRB): Add byte-in-range built-in function.
(CMBRB2): Add byte-in-either-range built-in function.
(CMPEQB): Add byte-in-set built-in function.
(CMPRB): Add overload support for byte-in-range function.
(CMPRB2): Add overload support for byte-in-either-range function.
(CMPEQB): Add overload support for byte-in-set built-in function.
* config/rs6000/rs6000-c.c (P9_BUILTIN_CMPRB): Macro expansion to
define argument types for new builtin.
(P9_BUILTIN_CMPRB2): Likewise.
(P9_BUILTIN_CMPEQB): Likewise.
* doc/extend.texi (PowerPC AltiVec Built-in Functions): Rearrange
the order of presentation for certain built-in functions
(scalar_extract_exp, scalar_extract_sig, scalar_insert_exp)
(scalar_cmp_exp_gt, scalar_cmp_exp_lt, scalar_cmp_exp_eq)
(scalar_cmp_exp_unordered, scalar_test_data_class)
(scalar_test_neg) to improve locality and flow. Document
the new __builtin_scalar_byte_in_set,
__builtin_scalar_byte_in_range, and
__builtin_scalar_byte_in_either_range functions.
Than McIntosh [Fri, 16 Dec 2016 22:11:28 +0000 (22:11 +0000)]
compiler: add containing Bfunction to some backend interfaces.
Change the interfaces for backend methods that create statements to
always pass in the enclosing Bfunction for the statement. Having the
function available simplifies things if a temporary variable has to be
created during the construction of a statement.
This also includes a change to the Mark_lvalue_varexprs helper
class to handle indirections on the left hand side of assignments
(e.g. "*x.y = ...").
Jerry DeLisle [Fri, 16 Dec 2016 20:27:51 +0000 (20:27 +0000)]
re PR fortran/78662 ([F03] Incorrect parsing of quotes in the char-literal-constant of the DT data descriptor)
2016-12-16 Jerry DeLisle <jvdelisle@gcc.gnu.org>
PR fortran/78622
* io.c (format_lex): Continue of string delimiter seen.
* io/transfer.c (get_dt_format): New static function to alloc
and set the DT iotype string, handling doubled quotes.
(formatted_transfer_scalar_read,
formatted_transfer_scalar_write): Use new function.
Jakub Jelinek [Fri, 16 Dec 2016 15:57:43 +0000 (16:57 +0100)]
re PR c/78408 (C loop initial declarations generate wrong code)
PR c/78408
* tree-ssa-ccp.c: Include tree-dfa.h.
(optimize_memcpy): New function.
(pass_fold_builtins::execute): Use it. Remove useless conditional
break after BUILT_IN_VA_*.
* gcc.dg/pr78408-1.c: New test.
* gcc.dg/pr78408-2.c: New test.
Marek Polacek [Fri, 16 Dec 2016 14:19:44 +0000 (14:19 +0000)]
re PR tree-optimization/78819 (Wrong code with VRP caused by register assertions along default switch labels)
PR tree-optimization/78819
* tree-vrp.c (find_switch_asserts): Return if the insertion limit is 0.
Don't register an assertion if the default case shares a label with
another case.
Wilco Dijkstra [Fri, 16 Dec 2016 13:14:46 +0000 (13:14 +0000)]
The negdi2 patterns for ARM and Thumb-2 are duplicated because Thumb-2 doesn't support RSC with an immediate.
The negdi2 patterns for ARM and Thumb-2 are duplicated because Thumb-2
doesn't support RSC with an immediate. We can however emulate RSC with
zero using a shifted SBC. If we add this to subsi3_carryin the negdi
patterns can be merged, simplifying things a bit. This should generate
identical code in all cases.
gcc/
* config/arm/arm.md (subsi3_carryin): Add Thumb-2 RSC #0.
(arm_negdi2) Rename to negdi2_insn, allow on Thumb-2.
* config/arm/thumb2.md (thumb2_negdi2): Remove pattern.
Wilco Dijkstra [Fri, 16 Dec 2016 12:59:41 +0000 (12:59 +0000)]
Thumb uses a special register allocation order to increase the use of low registers.
Thumb uses a special register allocation order to increase the use of low
registers. Oddly enough, LR appears before R12, which means that LR must
be saved and restored even if R12 is available. Swapping R12 and LR means
this simple example now uses R12 as a temporary (just like ARM):
int f(long long a, long long b)
{
if (a < b) return 1;
return a + b;
}
gcc/
* config/arm/arm.c (thumb_core_reg_alloc_order): Swap R12 and R14.
Previously users of mulsidi_600 and umulsidi_600 had to take care of
moving the multiplication result into the final destination themselves
(from the MUL64_OUT_REG register). This commit converts these two
instruction patterns into insn_and_split patterns that now take the
final destination as an extra operand. The insn_and_split patterns
generate the multiplication using two new multiplication instruction
patterns, then generate the move of the result from the MUL64_OUT_REG
register into the final destination.
This is a clean up commit, there should be no user visible changes
after this commit.
* config/arc/arc.md (mulsidi_600): Change to insn_and_split,
generate new mul64 insn for core multiplication work.
(umulsidi_600): Likewise, but use mulu64 insn.
(mul64): New pattern, content taken from old mulsidi_600 insn
pattern.
(mulu64): Likewise, but using umulsidi_600.
(mulsidi3): Remove move to destination, this is now handled by
mulsidi_600 insn_and_split.
(umulsidi3): Likewise, but using umulsidi_600.
Implement LWG 2769, Redundant const in the return type of any_cast(const any&).
Implement LWG 2769, Redundant const in the return type of
any_cast(const any&).
* include/std/any (_AnyCast): New.
(any_cast(const any&)): Use it and add an explicit cast for return.
(any_cast(any&)): Likewise.
(any_cast(any&&)): Likewise.
* testsuite/20_util/any/misc/any_cast.cc: Add a test for a type
that has an explicit copy constructor.
*testsuite/20_util/any/misc/any_cast_neg.cc: Adjust.
Ian Lance Taylor [Fri, 16 Dec 2016 00:34:37 +0000 (00:34 +0000)]
compiler: fix comments + fieldnames to match libgo source
A couple of the comments in the type descriptor code were out of date
with respect to the names in libgo/go/runtime/type.go. Fix up the
comments and field names to bring them into sync.
Ian Lance Taylor [Thu, 15 Dec 2016 23:44:13 +0000 (23:44 +0000)]
compiler: fix off-by-1 array type len in Type::gc_symbol_constructor
Array type being built to hold GC var initializer was being created
with an extra/unneeded slot. Fix up the code to insure that the array
length matches the length of the initializer list.
Ian Lance Taylor [Thu, 15 Dec 2016 22:47:43 +0000 (22:47 +0000)]
re PR go/78763 (go1: internal compiler error: in do_get_backend, at go/gofrontend/expressions.cc:8352)
PR go/78763
compiler: call determine_types even for constant expressions
We need to call determine_types even for constant expressions, since a
constant expression may include code like unsafe.Sizeof(0). Something
needs to determine the type of the untyped 0, and that should be the
determine_types pass.
Implementing that triggered a compiler crash on test/const1.go because
it permitted some erroneous constants to make it all the way to the
backend. Catch that case by checking whether we get a constant
overflow error, and marking the expression invalid if we do. This is
a good change in any case, as previously we reported the same constant
overflow error multiple times, and now we only report it once.
Uros Bizjak [Thu, 15 Dec 2016 22:23:46 +0000 (23:23 +0100)]
i386.md (ffs<mode>2): Generate CCCmode flags register for TARGET_BMI.
* config/i386/i386.md (ffs<mode>2): Generate CCCmode flags register
for TARGET_BMI.
(ffssi2_no_cmove): Ditto.
(*tzcnt<mode>_1_falsedep_1): New insn_and_split pattern.
(*tzcnt<mode>_1_falsedep): New insn pattern.
(LT_ZCNT): New mode iterator.
(lt_zcnt): New mode attribute.
(lt_zcnt_type): New mode attribute.
(<lt_zcnt>_<mode>): Macroize expander from bmi_tzcnt_<mode> and
lzcnt_<mode> using LT_ZCNT mode iterator.
(*<lt_zcnt>_<mode>_falsedep_1): Macroize insn from
*bmi_tzcnt_<mode>_falsedep_1 and *lzcnt_<mode>_falsedep_1
using LT_ZCNT mode iterator.
(*<lt_zcnt>_<mode>_falsedep): Macroize insn from
*bmi_tzcnt_<mode>_falsedep and *lzcnt_<mode>_falsedep
using LT_ZCNT mode iterator.
(*<lt_zcnt>_<mode>): Macroize insn from *bmi_tzcnt_<mode>
and *lzcnt_<mode> using LT_ZCNT mode iterator.
* config/i386/i386-builtin.def (__builtin_ia32_tzcnt_u16)
(__builtin_ia32_tzcnt_u32, __builtin_ia32_tzcnt_u64, __builtin_ctzs):
Update for rename.
Jakub Jelinek [Thu, 15 Dec 2016 20:42:11 +0000 (21:42 +0100)]
P0490R0 GB 20: decomposition declaration should commit to tuple interpretation early
P0490R0 GB 20: decomposition declaration should commit to tuple
interpretation early
* decl.c (get_tuple_size): Make static. If inst is error_mark_node
or non-complete type, return NULL_TREE, otherwise if
lookup_qualified_name fails or doesn't fold into INTEGER_CST, return
error_mark_node.
(get_tuple_element_type, get_tuple_decomp_init): Make static.
(cp_finish_decomp): Pass LOC to get_tuple_size. If it returns
error_mark_node, complain and fail.
David Malcolm [Thu, 15 Dec 2016 18:05:05 +0000 (18:05 +0000)]
Fix use-after-free lexing unterminated raw strings (PR preprocessor/78811)
gcc/ChangeLog:
PR preprocessor/78680
PR preprocessor/78811
* input.c (struct selftest::lexer_test): Add field
m_implicitly_expect_EOF.
(selftest::lexer_error_sink): New class.
(selftest::lexer_error_sink::s_singleton): New global.
(selftest::lexer_test::lexer_test): Initialize new field
"m_implicitly_expect_EOF".
(selftest::lexer_test::~lexer_test): Conditionalize the
check for the EOF token on the new field.
(selftest::test_lexer_string_locations_raw_string_unterminated):
New function.
(selftest::input_c_tests): Call the new test.
libcpp/ChangeLog:
PR preprocessor/78680
PR preprocessor/78811
* lex.c (_cpp_lex_direct): Only determine the end-location of
the token and build a range for non-reserved start locations.
Do not do it for EOF tokens.
Wilco Dijkstra [Thu, 15 Dec 2016 17:51:46 +0000 (17:51 +0000)]
Using leaf_function_p in a backend is dangerous as it incorrectly returns false...
Using leaf_function_p in a backend is dangerous as it incorrectly returns
false if it is called while in a sequence (for example during prolog/epilog
generation). Replace all uses with crtl->is_leaf as this is now initialized
early enough in ira.c. This typically causes no code generation differences
unless there was a bug due to leaf_function_p returning the wrong value.
gcc/
* config/arm/arm.h (TARGET_BACKTRACE): Use crtl->is_leaf.
* config/arm/arm.c (arm_option_check_internal): Improve comment.
(thumb_force_lr_save): Use crtl->is_leaf.
(arm_get_frame_offsets): Remove comment. Use crtl->is_leaf.
(thumb_far_jump_used_p): Remove comment.
(arm_frame_pointer_required): Use crtl->is_leaf.
Richard Earnshaw [Thu, 15 Dec 2016 16:04:08 +0000 (16:04 +0000)]
[arm] Permit 'auto' in -mfpu
Now we finally have the infrastructure in place we can now derive
details of the FPU from a CPU entry. This patch enables this for the
existing cores that already have an explicit FPU in their product names.
* arm-fpus.def: Add CNAME field to all FPU definitions.
* genopt.sh: Use explicit enumeration tags for FPU entries.
* arm-tables.opt: Regenerated.
* arm.opt (mfpu): Provide initial value.
* arm-opts.h (enum fpu_type): Build the enumeration from the list of
available FPUs. Add 'auto' entry on the end.
* arm.c (arm_configure_build_target): Only do explicit configuration
of the FPU features if the selected FPU is not 'auto'.
(arm_option_override): Adjust initialization of arm_fpu_index.
Emit an error if we have a hard float ABI request, but the processor
does not support floating-point.
(arm_option_print): Handle -mfpu=auto.
(arm_valid_target_attribute_rec): Don't permit fpu=auto in pragmas
or function attributes.
(arm_identify_fpu_from_isa): Handle effective soft-float when
the FPU is automatically detected.
* arm-cores.def (arm1136jf-s): Add feature ISA_FP_DBL.
(arm1176jzf-s): Likewise.
(mpcore): Likewise.
(arm1156t2f-s): Likewise.
Richard Earnshaw [Thu, 15 Dec 2016 16:03:06 +0000 (16:03 +0000)]
[arm] Remove FEATURES field from FPU descriptions
Now that everything uses the new ISA features, we can remove the
FEATURES field from the FPU descriptions, along with all the macros
and definitions associated with it.
Richard Earnshaw [Thu, 15 Dec 2016 16:01:55 +0000 (16:01 +0000)]
[arm] Use ISA feature sets for determining inlinability
Now that we can construct the build target isa from the cl_target_options
data we can use this to determine inlinability. This eliminates the
final remaining use of the FPU features field.
* arm.c (arm_can_inline_p): Use ISA features for determining
inlinability.
Richard Earnshaw [Thu, 15 Dec 2016 16:00:30 +0000 (16:00 +0000)]
[arm] Use cl_target_options for configuring the active target
It now becomes apparent that it would be better to use the the
cl_target_options as the basis for calling arm_configure_build_target;
it already contains exactly the same fields that we need. I chose not
to rewrite the earlier patches as that would make the progression of
changes seem less logical than it currently is, with several early
changes having no immediate justification.
* arm-protos.h (arm_configure_build_target): Change second argument
to cl_target_options.
* arm.c (arm_configure_build_target): Likewise.
(arm_option_restore): Update accordingly.
(arm_option_override): Create the target_option_default_node before
calling arm_configure_build_target. Use it in call of latter.
Resynchronize after all other overrides have been calculated.
(arm_valid_target_attribute_tree): Use the target options for
reconfiguration. Resynchronize after performing override checks.
* arm-c.c (arm_pragma_target_parse): Use target optiosn from cur_tree
to reconfigure the build target.
Richard Earnshaw [Thu, 15 Dec 2016 15:58:02 +0000 (15:58 +0000)]
[arm] Eliminate TARGET_FPU_NAME
Rather than assuming a specific fpu name has been selected, we work
out the FPU from the ISA properties. This is necessary since once we
have default FPUs selected by the processor, there will be no explicit
entry in the table of fpus to refer to.
This also fixes a bug with the code I added recently to permit new
aliases for existing FPU names: the new names cannot be passed to the
assembler since it does not recognize them. By mapping the ISA
features back to the canonical names we avoid having to teach the
assembler about the new names.
* arm.h (TARGET_FPU_NAME): Delete.
* arm.c (arm_identify_fpu_from_isa): New function.
(arm_declare_function_name): Use it to get the name for the FPU.
Richard Earnshaw [Thu, 15 Dec 2016 15:56:29 +0000 (15:56 +0000)]
[arm] Initialize fpu capability bits in arm_active_target
Now that we can describe the FPU with the standard ISA bits we need to
initialize them. However, the FPU settings can be changed with target build
attributes, so we also need to reset them if things change. This requires
a bit of juggling about with the existing code to ensure that the active
target is reconfigured after each change to the target options.
* arm-protos.h: Include sbitmap.h
(arm_configure_build_target): Make public.
* arm.c (arm_configure_build_target): Now not static.
(arm_valid_target_attribute_rec): Move internal option check to...
(arm_valid_target_attribute_tree0: ... here. Also reconfingure the
active target.
(arm_override_options_after_change): Call arm_configure_build_target.
(isa_all_fpubits): Renamed from isa_fpubits.
(arm_option_restore): New function.
(TARGET_OPTION_RESTORE): Register it.
(arm_configure_build_target): Initialize the FPU capability bits in
the isa.
(arm_option_override): Move the code that forces the setting of the
FPU option before the call to arm_configure_build_target.
* arm.opt (march): Mark as Save.
(mcpu, mtune): Likewise.
* arm-c.c (arm_pragma_target_parse): Reconfigure the build target
after pragmas change the target options.
Richard Earnshaw [Thu, 15 Dec 2016 15:54:53 +0000 (15:54 +0000)]
[arm] Add isa features to FPU descriptions
Similar to the new CPU and architecture ISA feature lists, we now add
similar capabilities to each FPU description. We don't use these yet,
that will come in later patches. These follow the same style as the
newly modified flag sets, but use slightly different defaults that
more accurately reflect the ISA specifications.
* arm-isa.h (isa_feature): Add bits for VFPv4, FPv5, fp16conv,
fP_dbl, fp_d32 and fp_crypto.
(ISA_ALL_FPU): Add all the new bits.
(ISA_VFPv2, ISA_VFPv3, ISA_VFPv4, ISA_FPv5): New macros.
(ISA_FP_ARMv8, ISA_FP_DBL, ISA_FP_D32, ISA_NEON, ISA_CRYPTO): Likewise.
* arm-fpus.def: Add ISA features to all FPUs.
* arm.h: (arm_fpu_desc): Add new field for ISA bits.
* arm.c (all_fpus): Initialize it.
* arm-tables.opt: Regenerated.
Richard Earnshaw [Thu, 15 Dec 2016 15:53:50 +0000 (15:53 +0000)]
[arm] Remove FPU rev field
Similar to the main ISA, we convert the FPU revision into a set of feature
bits. This permits a more complex set of capability relationships to be
expressed more easily. For now we continue to use the traditional bitmasks.
* arm.h (FPU_FL_VFPv2) New feature bit.
(FPU_FL_VFPv3, FPU_FL_VFPv4, FPU_FL_VFPv5, FPU_FL_ARMv8): Likewise.
(FPU_VFPv2, FPU_VFPv3, FPU_VFPv4, FPU_VFPv5, FPU_ARMv8): New helper
macros.
(FPU_DBL, FPU_D32, FPU_NEON, FPU_CRYPTO, FPU_FP16): Likewise.
(TARGET_FPU_REV): Delete.
(TARGET_VFP3): Use feature bits.
(TARGET_VFP5): Likewise.
(TARGET_FMA): Likewise.
(TARGET_FPU_ARMV8): Likewise.
(struct arm_fpu_desc): Delete rev field.
* arm-fpus.def: Delete REV entry, use new feature bits and macros.
* arm.c (all_fpus): Delete rev field.
Richard Earnshaw [Thu, 15 Dec 2016 15:52:42 +0000 (15:52 +0000)]
[arm] Eliminate vfp_reg_type
Remove the VFP_REGS field by converting its meanings into flag
attributes. The new flag attributes build on each other describing
increasing capabilities. This allows us to do a better job when
inlining functions with differing requiremetns on the fpu environment:
we can now inline A into B if B has at least the same register set
properties as B (previously we required identical register set
properties).
* arm.h (vfp_reg_type): Delete.
(TARGET_FPU_REGS): Delete.
(arm_fpu_desc): Delete regs field.
(FPU_FL_NONE, FPU_FL_NEON, FPU_FL_FP16, FPU_FL_CRYPTO): Use unsigned
values.
(FPU_FL_DBL, FPU_FL_D32): Define.
(TARGET_VFPD32): Use feature test.
(TARGET_VFP_SINGLE): Likewise.
(TARGET_VFP_DOUBLE): Likewise.
* arm-fpus.def: Update all entries for new feature bits.
* arm.c (all_fpus): Update initializer macro.
(arm_can_inline_p): Remove test on fpu regs.
Richard Earnshaw [Thu, 15 Dec 2016 15:51:35 +0000 (15:51 +0000)]
[arm] Delete unused arm_fp_model
The arm_fp_model enumeration type has only had one useful value since
the FPA support was removed, and it's no-longer used anywhere. This
patch just cleans that up by removing it.
Richard Earnshaw [Thu, 15 Dec 2016 15:49:13 +0000 (15:49 +0000)]
[arm] Rework arm-common to use new feature bits.
This converts the recently added implicit -mthumb support code to use
the new data structures. Since we have a very simple query and no
initialized copies of the sbitmaps, for now we simply scan the list of
features to look for the one of interest.
* arm-opts.h (struct arm_arch_core_flag): Add new field ISA.
Initialize it.
(arm_arch_core_flag): Delete flags field.
(arm_arch_core_flags): Don't initialize flags field.
* common/config/arm/arm-common.c (check_isa_bits_for): New function.
(arm_target_thumb_only): Use new isa bits arrays.
Richard Earnshaw [Thu, 15 Dec 2016 15:47:58 +0000 (15:47 +0000)]
[arm] Remove insn_flags.
This patch finishes the job of removing insn_flags and moves the logic
over to using the new data structures. I've added a new boolean
variable to detect when we have ARMv7ve-like capabilities and thus
have 64-bit atomic operations since that would be a complex query and
expensive to do in full. It might be better to add a specific bit to
the ISA data structures to indicate this capability directly.
* arm-protos.h (insn_flags): Delete declaration.
(arm_arch7ve): Declare.
* arm.c (insn_flags): Delete.
(arm_arch7ve): New variable.
(arm_selected_cpu): Delete.
(arm_option_check_internal): Use new ISA bitmap.
(arm_option_override_internal): Likewise.
(arm_configure_build_target): Declare arm_selected_cpu locally.
(arm_option_override): Use new ISA bitmap. Initialize arm_arch7ve.
Rearrange variable intialization by general function.
* arm.h (TARGET_HAVE_LPAE): Use arm_arch7ve.
Richard Earnshaw [Thu, 15 Dec 2016 15:46:41 +0000 (15:46 +0000)]
[arm] Use arm_active_target when configuring builtins
This patch uses the new ISA data structure to determine which builtins
to add. It entirely eliminates the need for insn_flags to be a global
variable, but we're about to delete that in the following patches, so
for now we leave it as a global.
* arm-builtins.c: Include sbitmap.h.
(def_mbuiltin): Change first parameter to a flag bit. Use it to test
available features in the current target.
(struct builtin_description): Change type of feature field.
(IWMMXT_BUILTIN): Use the isa_features types.
(IWMMXT2_BUILTIN): Likewise.
(IWMMXT_BUILTIN2): Likewise.
(IWMMXT2_BUILTIN2): Likewise.
(CRC32_BUILTIN): Likewise.
(CRYPTO_BUILTIN): Likewise.
(iwmmx_builtin): Likewise.
(iwmmx2_builtin): Likewise.
(arm_iwmmxt_builtin): Check for specific feature bits.
Richard Earnshaw [Thu, 15 Dec 2016 15:45:23 +0000 (15:45 +0000)]
[arm] Add new isa quirk bit for Cortex-M3 ldrd issue.
With the new data structures it is trivial to add a new field and we
aren't (too) limited as to the number we have. This patch adds a new
bit to describe the need for a particular compiler behaviour
modification: in this case a quirk in the cortex-m3.
* arm-isa.h (enum isa_feature): Add isa_quirk_cm3_ldrd.
(ISA_ALL_QUIRKS): New macro.
* arm-cores.def (cortex-m3): Add isa_quirk_cm3_ldrd to isa feature list.
* arm.c (isa_quirkbits): New feature-list bitmap.
(arm_configure_build_target): Ignore quirk bits when comparing an
architecture feature list with a CPU feature list.
(arm_option_override): Initialize_isa_quirkbits. If the user has
not specified -m[no-]fix-cortex-m3-ldrd, automatically enable the
feature if isa_quirk_cm3_ldrd appears in the isa feature list.
Richard Earnshaw [Thu, 15 Dec 2016 15:44:01 +0000 (15:44 +0000)]
[arm] Reduce usage of arm_selected_cpu.
Make more use of the new data structure for initializing existing
variables.
* arm.c (arm_option_override): Use arm_active_target as source of
information for arm_base_arch and arm_arch_name.
* (arm_file_start): Use arm_active_target for core name.
Richard Earnshaw [Thu, 15 Dec 2016 15:42:43 +0000 (15:42 +0000)]
[arm] Use arm_active_target for architecture and tune
We now start to make more use of the new data structure. This allows
us to eliminate two of the existing static variables,
arm_selected_arch and arm_selected tune.
* arm.c (arm_selected_tune): Delete static variable.
(arm_selected_arch): Likewise.
(arm_configure_build_target): Declare local versions of arm_selected
target and arm_selected_arch. Initialize more fields in target
data structure.
(arm_option_override): Use arm_active_target instead of
arm_selected_tune and arm_selected_arch.
(asm_file_start): Use arm_active_target.
Richard Earnshaw [Thu, 15 Dec 2016 15:41:26 +0000 (15:41 +0000)]
[arm] Introduce arm_active_target.
This patch creates a new data structure for carrying around the data
relating to the current compilation target. The idea behind this is
that this data structure can be updated to reflect the overall
compilation target as new information is gathered (from command line
options) or architectural extensions. We will no-longer have to grub
around looking in multiple places for this information.
There are some small behaviour changes around how we handle selecting
a default CPU if thumb or interworking are specified on the command
line and the default CPU does not support thumb, but I believe the
existing code was broken in that respect. This code will go away once
we obsolete pre-armv4t devices.
* arm-protos.h (arm_build_target): New structure.
(arm_active_target): Declare it.
* arm.c (arm_active_target): New variable.
(bitmap_popcount): New function.
(feature_count): Delete.
(arm_initialize_isa): New function.
isa_fpubits): New variable.
(arm_configure_build_target): New function.
(arm_option_override): Initialize isa_fpubits and arm_active_target.isa.
Use arm_configure_build_target.
Richard Earnshaw [Thu, 15 Dec 2016 15:39:40 +0000 (15:39 +0000)]
This patch adds the new ISA data structures.
This patch adds the new ISA data structures. The idea is to use an
sbitmap for carrying these around internally. We don't make much use
of this yet, but will increasingly migrate over to this in the
following patches. All cores and architectures currently have both
old and new encodings for now.
For simplicity and clarity we introduce internally the concept of
ARMv7ve. It doesn't change any visible behaviour.
There's also a bit of tidying up of the various supported cores,
sorting them by profile.
* arm-isa.h: New file.
* arm-protos.h: Include it.
* arm-arches.def: Add new ISA field to all entries. Drop bogus
armv8.1-a+crc architecture.
* arm-cores.def: Similarly. Group ARMv8 cores by profile.
* arm-opts.h (enum processor_type): Adjust for new field.
* arm.c (struct processors): New field 'isa_bits'.
(all_cores, all_architectures): Initialize new field.
* arm-tables.opt: Regenerated.
* arm-tune.md: Regenerated.
Richard Earnshaw [Thu, 15 Dec 2016 15:38:21 +0000 (15:38 +0000)]
We start out by separating the 'tuning flags' in a CPU or architecture...
We start out by separating the 'tuning flags' in a CPU or architecture
specification into a new field in the data structures. Because there
aren't very many of these (and we'd like to get rid of them entirely,
eventually, moving to entries in the tuning tables), we just use a
simple unsigned word. This frees up a number of bits in the main
flags data structure, but we don't consolidate them as we'll be
getting rid of them entirely shortly.
There's one small user-visible change, the slow multiply flag is moved
from being treated as an architectural flag to a tuning flag. This
has two consequences: it's now ignored for architectural matching to a
CPU and specifying a -mtune option will now correctly apply the
multiply performance to the decision as to which sequences to
synthesise.
* arm-arches.def (ARM_ARCH): Add extra field TUNE_FLAGS, move
tuning properties from architectural FLAGS field.
* arm-cores.def (ARM_CORE): Likewise.
* arm-protos.h (TF_LDSCHED, TF_WBUF, TF_CO_PROC): New macros.
(TF_SMALLMUL, TF_STRONG, TF_SCALE, TF_NOMODE32): New macros.
(FL_LDSCHED, FL_STRONG, FL_WBUF, FL_SMALLMUL): Delete.
(FL_TUNE): Remove deleted elements.
(tune_flags): Convert type to unsigned int.
* arm.c (struct processors): Add new field tune_flags.
(all_cores, all_arches): Initialize it.
(arm_option_override): Adapt uses of tune_flags. Use tune_flags
for deciding when we should have slow multiply operations.
Janus Weil [Thu, 15 Dec 2016 14:07:51 +0000 (15:07 +0100)]
re PR fortran/78800 ([OOP] ICE in compare_parameter, at fortran/interface.c:2246)
2016-12-15 Janus Weil <janus@gcc.gnu.org>
PR fortran/78800
* interface.c (compare_allocatable): Avoid additional errors on bad
class declarations.
(compare_parameter): Put the result of gfc_expr_attr into a variable,
in order to avoid calling it multiple times. Exit early on bad class
declarations to avoid ICE.
2016-12-15 Janus Weil <janus@gcc.gnu.org>
PR fortran/78800
* gfortran.dg/unlimited_polymorphic_27.f90: New test case.
Jonathan Wakely [Thu, 15 Dec 2016 12:45:42 +0000 (12:45 +0000)]
Add GDB XMethods for shared_ptr and unique_ptr<T[]>
* python/libstdcxx/v6/xmethods.py (UniquePtrGetWorker.__init__): Use
correct element type for unique_ptr<T[]>.
(UniquePtrGetWorker._supports, UniquePtrDerefWorker._supports): New
functions to disable unsupported operators for unique_ptr<T[]>.
(UniquePtrSubscriptWorker): New worker for operator[].
(UniquePtrMethodsMatcher.__init__): Register UniquePtrSubscriptWorker.
(UniquePtrMethodsMatcher.match): Call _supports on the chosen worker.
(SharedPtrGetWorker, SharedPtrDerefWorker, SharedPtrSubscriptWorker)
(SharedPtrUseCountWorker, SharedPtrUniqueWorker): New workers.
(SharedPtrMethodsMatcher): New matcher for shared_ptr.
(register_libstdcxx_xmethods): Register SharedPtrMethodsMatcher.
* testsuite/libstdc++-xmethods/unique_ptr.cc: Test arrays.
* testsuite/libstdc++-xmethods/shared_ptr.cc: New test.
Ian Lance Taylor [Thu, 15 Dec 2016 02:14:40 +0000 (02:14 +0000)]
compiler: remove unneeded zero-length slice value init
Prune away a bit of unnecessary code from the helper routine
Slice_construction_expression::create_array_val() that was adding
an extra NULL value to empty slices (no longer needed).