Haochen Jiang [Thu, 17 Aug 2023 06:13:28 +0000 (14:13 +0800)]
Emit a warning when disabling AVX512 with AVX10 enabled or disabling AVX10 with AVX512 enabled
gcc/ChangeLog:
* common/config/i386/i386-common.cc
(ix86_check_avx10): New function to check isa_flags and
isa_flags_explicit to emit warning when AVX10 is enabled
by "-m" option.
(ix86_check_avx512): New function to check isa_flags and
isa_flags_explicit to emit warning when AVX512 is enabled
by "-m" option.
(ix86_handle_option): Do not change the flags when warning
is emitted.
* config/i386/driver-i386.cc (host_detect_local_cpu):
Do not append -mno-avx10.1 for -march=native.
Andrew Pinski [Sat, 12 Aug 2023 01:19:01 +0000 (18:19 -0700)]
Add support for vector conitional not
Like the support conditional neg (r12-4470-g20dcda98ed376cb61c74b2c71),
this just adds conditional not too.
Also we should be able to turn `(a ? -1 : 0) ^ b` into a conditional
not.
OK? Bootstrapped and tested on x86_64-linux-gnu and aarch64-linux-gnu.
gcc/ChangeLog:
* internal-fn.def (COND_NOT): New internal function.
* match.pd (UNCOND_UNARY, COND_UNARY): Add bit_not/not
to the lists.
(`vec (a ? -1 : 0) ^ b`): New pattern to convert
into conditional not.
* optabs.def (cond_one_cmpl): New optab.
(cond_len_one_cmpl): Likewise.
gcc/testsuite/ChangeLog:
PR target/110986
* gcc.target/aarch64/sve/cond_unary_9.c: New test.
Harald Anlauf [Wed, 16 Aug 2023 20:00:49 +0000 (22:00 +0200)]
Fortran: fix memleak for character,value dummy of bind(c) procedure [PR110360]
Testcase gfortran.dg/bind_c_usage_13.f03 exhibited a memleak in the frontend
occuring when passing a character literal to a character,value dummy of a
bind(c) procedure, due to a missing cleanup in the conversion of the actual
argument expression. Reduced testcase:
program p
interface
subroutine val_c (c) bind(c)
use iso_c_binding, only: c_char
character(len=1,kind=c_char), value :: c
end subroutine val_c
end interface
call val_c ("A")
end
gcc/fortran/ChangeLog:
PR fortran/110360
* trans-expr.cc (conv_scalar_char_value): Use gfc_replace_expr to
avoid leaking replaced gfc_expr.
The callable used for resize_and_overwrite was being passed the string's
expanded capacity, which might be greater than the new size being
requested. This is not conforming, as the standard requires the same n
to be passed to the callable that the user passed to
resize_and_overwrite.
The existing tests didn't catch this because they all used a value which
was more than twice the existing capacity, so the _M_create call
allocated exactly what was requested, and the value passed to the
callable was correct. But when the requested size is greater than the
current capacity but smaller than twice the current capacity, _M_create
will allocate twice the current capacity and then that value was being
passed to the callable.
I noticed this because std::format(L"{}", 0.25) was producing L"0.25XX"
where the XX characters were whatever happened to be on the stack before
the call. When std::format used resize_and_overwrite to widen a string
it was copying too many characters into the destination and setting the
result's length too long. I've added a test for this case, and a new
test that doesn't hardcode -std=gnu++20 so can be used to test
std::format in C++23 and C++26 modes.
libstdc++-v3/ChangeLog:
* include/bits/basic_string.tcc (resize_and_overwrite): Invoke
the callable with the same size as resize_and_overwrite was
called with.
* testsuite/21_strings/basic_string/capacity/char/resize_and_overwrite.cc:
Check with small values for the new size.
* testsuite/std/format/functions/format.cc: Check wide
formatting of double values that produce small strings.
* testsuite/std/format/functions/format_c++23.cc: New test.
ira: update allocated_hardreg_p[] in improve_allocation() [PR110254]
The improve_allocation() routine does not update the
allocated_hardreg_p[] array after an allocno is assigned a register.
If the register chosen in improve_allocation() is one that already has
been assigned to a conflicting allocno, then allocated_hardreg_p[]
already has the corresponding bit set to TRUE, so nothing needs to be
done.
But improve_allocation() can also choose a register that has not been
assigned to a conflicting allocno, and also has not been assigned to any
other allocno. In this case, allocated_hardreg_p[] has to be updated.
Jonathan Wakely [Wed, 16 Aug 2023 11:24:35 +0000 (12:24 +0100)]
libstdc++: Fix comment naming upstream PSTL test file
These tests were derived from set.pass.cpp not set.pass.cc, specifically
pstl/test/std/algorithms/alg.sorting/alg.set.operations/set.pass.cpp in
the LLVM repo.
libstdc++-v3/ChangeLog:
* testsuite/25_algorithms/pstl/alg_sorting/set_difference.cc:
Fix name of upstream file this was derived from.
* testsuite/25_algorithms/pstl/alg_sorting/set_intersection.cc:
Likewise.
* testsuite/25_algorithms/pstl/alg_sorting/set_symmetric_difference.cc:
Likewise.
* testsuite/25_algorithms/pstl/alg_sorting/set_union.cc:
Likewise.
* testsuite/25_algorithms/pstl/alg_sorting/set_util.h: Likewise.
[LRA]: Spill pseudos assigned to fp when fp->sp elimination became impossible
Porting LRA to AVR revealed that creating a stack slot can make fp->sp
elimination impossible. The previous patches undoes fp assignment after
the stack slot creation but calculated wrongly live info after this. This
resulted in wrong generation by deleting some still alive insns. This
patch fixes this problem.
gcc/ChangeLog:
* lra-int.h (lra_update_fp2sp_elimination): Change the prototype.
* lra-eliminations.cc (spill_pseudos): Record spilled pseudos.
(lra_update_fp2sp_elimination): Ditto.
(update_reg_eliminate): Adjust spill_pseudos call.
* lra-spills.cc (lra_spill): Assign stack slots to pseudos spilled
in lra_update_fp2sp_elimination.
Arsen Arsenović [Mon, 27 Mar 2023 13:29:08 +0000 (15:29 +0200)]
libstdc++: Implement more maintainable <version> header
This commit replaces the ad-hoc logic in <version> with an AutoGen
database that (mostly) declaratively generates a version.h bit which
combines all of the FTM logic across all headers together.
This generated header defines macros of the form __glibcxx_foo,
equivalent to their __cpp_lib_foo variants, according to rules specified
in version.def and, optionally, if __glibcxx_want_foo or
__glibcxx_want_all are defined, also defines __cpp_lib_foo forms with
the same definition.
libstdc++-v3/ChangeLog:
* include/Makefile.am (bits_freestanding): Add version.h.
(allcreated): Add version.h.
(${bits_srcdir}/version.h): New rule. Regenerates
version.h out of version.{def,tpl}.
* include/Makefile.in: Regenerate.
* include/bits/version.def: New file. Declares a list of
all feature test macros, their values and their preconditions.
* include/bits/version.tpl: New file. Turns version.def
into a sequence of #if blocks.
* include/bits/version.h: New file. Generated from
version.def.
* include/std/version: Replace with a __glibcxx_want_all define
and bits/version.h include.
If there is no direct support, the vectorizer can synthesize the pattern
but, presumably, due to lack of narrowing operation support, won't try a
narrowing shift. Therefore, this patch implements the expanders
instead.
* gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c: New test.
* gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/widen/vec-avg-template.h: New test.
Robin Dapp [Tue, 15 Aug 2023 09:43:43 +0000 (11:43 +0200)]
internal-fn: Fix vector extraction into promoted subreg.
This patch fixes the case where vec_extract gets passed a promoted
subreg (e.g. from a return value). This is achieved by using
expand_convert_optab_fn instead of a separate expander function.
gcc/ChangeLog:
* internal-fn.cc (vec_extract_direct): Change type argument
numbers.
(expand_vec_extract_optab_fn): Call convert_optab_fn.
(direct_vec_extract_optab_supported_p): Use
convert_optab_supported_p.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-runu.c: New test.
For this case the index 2 in sel is ambiguous for len 2 + 2x:
if x = 0, runtime vector length = 2 and sel[i] will choose arg1[0]
if x > 0, runtime vector length > 2 and sel[i] choose arg0[2].
So we return NULL_TREE for this case.
This leads us to defining a constraint that a stepped sequence in sel,
should only select a particular pattern from a particular input vector.
sel contains a single pattern with stepped sequence: {0, 2, ...}.
Let, a1 = the first element of stepped part of sequence, which is 0.
Let esel = number of total elements in stepped sequence.
Thus,
esel = len / sel_npatterns
= (4 + 4x) / 1
= 4 + 4x
Let S = step of the sequence, which is 2 in this case.
Let ae = last element of the stepped sequence.
Thus,
ae = a1 + (esel - 2) * S
= 0 + (4 + 4x - 2) * 2
= 4 + 8x
To ensure that we select elements from the same input vector,
a1 /trunc len = ae /trunc len.
Let, q1 = a1 /trunc len = 0 / (4 + 4x) = 0
Let, qe = ae /trunc len = (4 + 8x) / (4 + 4x) = 1
Since q1 != qe, we cross input vectors, and return NULL_TREE for this case.
However, if sel was:
sel = {len, 0, 1, ...}
The only change in this case is S = 1.
So,
ae = a1 + (esel - 2) * S
= 0 + (4 + 4x - 2) * 1
= 2 + 4x
In this case, a1/len == ae/len == 0, and the stepped sequence chooses all elements
from arg0.
Thus,
res = {arg1[0], arg0[0], arg0[1], ...}
For VLA folding, sel has to conform to constraints imposed in
valid_mask_for_fold_vec_perm_cst_p.
test_fold_vec_perm_cst defines several unit-tests for VLA folding.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(BASE): New declaration.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwcvt_xu_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-wcvt-xu.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(BASE): New declaration.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwcvt_x_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-wcvt-x.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (BASE): New declaration.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfcvt_f_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-cvt-f.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(BASE): New declaration.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfcvt_xu_frm): New intrinsic function def..
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-cvt-xu.c: New test.
Haochen Gui [Wed, 16 Aug 2023 06:29:36 +0000 (14:29 +0800)]
rs6000: Skip unnecessary vector extract for certain elements.
If the extracted element index is:
- for byte, 7 on BE while 8 on LE;
- for half word, 3 on BE while 4 on LE;
the element to be stored is already in the corresponding place for
stxsi[hb]x. We don't need a redundant vector extraction at all.
gcc/
PR target/110429
* config/rs6000/vsx.md (*vsx_extract_<mode>_store_p9): Skip vector
extract when the element is 7 on BE while 8 on LE for byte or 3 on
BE while 4 on LE for halfword.
Haochen Gui [Wed, 16 Aug 2023 06:21:09 +0000 (14:21 +0800)]
rs6000: Generate mfvsrwz for all platforms and remove redundant zero extend
mfvsrwz has lower latency than xxextractuw or vextuw[lr]x. So it should be
generated even with p9 vector enabled. Also the instruction is already
zero extended. A combine pattern is needed to eliminate redundant zero
extend instructions.
gcc/
PR target/106769
* config/rs6000/vsx.md (expand vsx_extract_<mode>): Set it only
for V8HI and V16QI.
(vsx_extract_v4si): New expand for V4SI extraction.
(vsx_extract_v4si_w1): New insn pattern for V4SI extraction on
word 1 from BE order.
(*mfvsrwz): New insn pattern for mfvsrwz.
(*vsx_extract_<mode>_di_p9): Assert that it won't be generated on
word 1 from BE order.
(*vsx_extract_si): Remove.
(*vsx_extract_v4si_w023): New insn and split pattern on word 0, 2,
3 from BE order.
* config/riscv/autovec.md (vec_mask_len_load_lanes<mode><vsingle>):
New pattern.
(vec_mask_len_store_lanes<mode><vsingle>): Ditto.
* config/riscv/riscv-protos.h (expand_lanes_load_store): New function.
* config/riscv/riscv-v.cc (get_mask_mode): Add tuple mask mode.
(expand_lanes_load_store): New function.
* config/riscv/vector-iterators.md: New iterator.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c:
Adapt test.
* gcc.target/riscv/rvv/autovec/partial/slp-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-16.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-17.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-18.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-19.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-6.c: Ditto.
* gcc.target/riscv/rvv/rvv.exp: Add lanes tests.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c: New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c: New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c: New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c: New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c: New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c: New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c: New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c:
New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c:
New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c:
New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c:
New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c:
New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c:
New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c:
New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c: New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c: New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c: New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c: New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c: New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c: New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c: New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c:
New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c:
New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c:
New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c:
New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c:
New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c:
New test.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c:
New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c: New test.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c: New test.
Step 1 - Modifiy the LANES LOAD/STORE support function (vect_load_lanes_supported/vect_store_lanes_supported):
+/* Return FN if vec_{masked_,mask_len,}load_lanes is available for COUNT
+ vectors of type VECTYPE. MASKED_P says whether the masked form is needed. */
Instead of returning TRUE or FALSE whether target support the LANES LOAD/STORE.
I change it into return internal_fn of the LANES LOAD/STORE that target support,
If target didn't support any LANE LOAD/STORE optabs, return IFN_LAST.
if (!STMT_VINFO_STRIDED_P (first_stmt_info)
&& (can_overrun_p || !would_overrun_p)
&& compare_step_with_zero (vinfo, stmt_info) > 0)
{
/* First cope with the degenerate case of a single-element
vector. */
if (known_eq (TYPE_VECTOR_SUBPARTS (vectype), 1U))
;
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(enum frm_op_type): New type for frm.
(BASE): New declaration.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfcvt_x_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-cvt-x.c: New test.
liuhongt [Thu, 10 Aug 2023 08:26:13 +0000 (16:26 +0800)]
Support -m[no-]gather -m[no-]scatter to enable/disable vectorization for all gather/scatter instructions
Rename original use_gather to use_gather_8parts, Support
-mtune-ctrl={,^}use_gather to set/clear tune features
use_gather_{2parts, 4parts, 8parts}. Support the new option -mgather
as alias of -mtune-ctrl=, use_gather, ^use_gather.
Similar for use_scatter.
gcc/ChangeLog:
* config/i386/i386-builtins.cc
(ix86_vectorize_builtin_gather): Adjust for use_gather_8parts.
* config/i386/i386-options.cc (parse_mtune_ctrl_str):
Set/Clear tune features use_{gather,scatter}_{2parts, 4parts,
8parts} for -mtune-crtl={,^}{use_gather,use_scatter}.
* config/i386/i386.cc (ix86_vectorize_builtin_scatter): Adjust
for use_scatter_8parts
* config/i386/i386.h (TARGET_USE_GATHER): Rename to ..
(TARGET_USE_GATHER_8PARTS): .. this.
(TARGET_USE_SCATTER): Rename to ..
(TARGET_USE_SCATTER_8PARTS): .. this.
* config/i386/x86-tune.def (X86_TUNE_USE_GATHER): Rename to
(X86_TUNE_USE_GATHER_8PARTS): .. this.
(X86_TUNE_USE_SCATTER): Rename to
(X86_TUNE_USE_SCATTER_8PARTS): .. this.
* config/i386/i386.opt: Add new options mgather, mscatter.
liuhongt [Thu, 10 Aug 2023 03:41:39 +0000 (11:41 +0800)]
Software mitigation: Disable gather generation in vectorization for GDS affected Intel Processors.
For more details of GDS (Gather Data Sampling), refer to
https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/gather-data-sampling.html
After microcode update, there's performance regression. To avoid that,
the patch disables gather generation in autovectorization but uses
gather scalar emulation instead.
gcc/ChangeLog:
* config/i386/i386-options.cc (m_GDS): New macro.
* config/i386/x86-tune.def (X86_TUNE_USE_GATHER_2PARTS): Don't
enable for m_GDS.
(X86_TUNE_USE_GATHER_4PARTS): Ditto.
(X86_TUNE_USE_GATHER): Ditto.
Generate vmovapd instead of vmovsd for moving DFmode between SSE_REGS.
vmovapd can enable register renaming and have same code size as
vmovsd. Similar for vmovsh vs vmovaps, vmovaps is 1 byte less than
vmovsh.
When TARGET_AVX512VL is not available, still generate
vmovsd/vmovss/vmovsh to avoid vmovapd/vmovaps zmm16-31.
gcc/ChangeLog:
* config/i386/i386.md (movdf_internal): Generate vmovapd instead of
vmovsd when moving DFmode between SSE_REGS.
(movhi_internal): Generate vmovdqa instead of vmovsh when
moving HImode between SSE_REGS.
(mov<mode>_internal): Use vmovaps instead of vmovsh when
moving HF/BFmode between SSE_REGS.
David Faust [Tue, 15 Aug 2023 17:54:17 +0000 (10:54 -0700)]
bpf: fix pseudoc w regs for small modes [PR111029]
In the BPF pseudo-c assembly dialect, registers treated as 32-bits
rather than the full 64 in various instructions ought to be printed as
"wN" rather than "rN". But bpf_print_register () was only doing this
for specifically SImode registers, meaning smaller modes were printed
incorrectly.
This caused assembler errors like:
Error: unrecognized instruction `w2 =(s8)r1'
for a 32-bit sign-extending register move instruction, where the source
register is used in QImode.
Fix bpf_print_register () to print the "w" version of register when
specified by the template for any mode 32-bits or smaller.
PR target/111029
gcc/
* config/bpf/bpf.cc (bpf_print_register): Print 'w' registers
for any mode 32-bits or smaller, not just SImode.
gcc/testsuite/
* gcc.target/bpf/smov-2.c: New test.
* gcc.target/bpf/smov-pseudoc-2.c: New test.
Martin Jambor [Tue, 15 Aug 2023 15:26:13 +0000 (17:26 +0200)]
Feed results of IPA-CP into tree value numbering
PRs 68930 and 92497 show that when IPA-CP figures out constants in
aggregate parameters or when passed by reference but the loads happen
in an inlined function the information is lost. This happens even
when the inlined function itself was known to have - or even cloned to
have - such constants in incoming parameters because the transform
phase of IPA passes is not run on them. See discussion in the bugs
for reasons why.
Honza suggested that we can plug the results of IPA-CP analysis into
value numbering, so that FRE can figure out that some loads fetch
known constants. This is what this patch attempts to do. The patch
does not attempt to populate partial_defs with information from
IPA-CP, this can be hopefully added as a follow-up.
gcc/ChangeLog:
2023-08-11 Martin Jambor <mjambor@suse.cz>
PR ipa/68930
PR ipa/92497
* ipa-prop.h (ipcp_get_aggregate_const): Declare.
* ipa-prop.cc (ipcp_get_aggregate_const): New function.
(ipcp_transform_function): Do not deallocate transformation info.
* tree-ssa-sccvn.cc: Include alloc-pool.h, symbol-summary.h and
ipa-prop.h.
(vn_reference_lookup_2): When hitting default-def vuse, query
IPA-CP transformation info for any known constants.
Iain Buclaw [Tue, 15 Aug 2023 15:10:45 +0000 (17:10 +0200)]
d: Add test case for PR110959.
This ICE is specific to the D front-end language version in GDC 12,
however a test has been added to mainline to catch the unlikely event of
a regression.
Martin Jambor [Tue, 15 Aug 2023 15:13:44 +0000 (17:13 +0200)]
Fortran: Avoid accessing gfc_charlen when not looking at BT_CHARACTER (PR 110677)
This patch addresses an issue uncovered by the undefined behavior
sanitizer. In function resolve_structure_cons in resolve.cc there is
a test starting with:
and UBSAN complained of loads from comp->ts.u.cl->length->expr_type of
integer value 1818451807 which is outside of the value range expr_t
enum. If I understand the code correctly it the entire load was
unwanted because comp->ts.type in those cases is BT_CLASS and not
BT_CHARACTER. This patch simply adds a check to make sure it is only
accessed in those cases.
During review, Harald Anlauf noticed that length types also need to be
checked and so I added also checks that he suggested to the condition.
Co-authored-by: Harald Anlauf <anlauf@gmx.de>
gcc/fortran/ChangeLog:
2023-08-14 Martin Jambor <mjambor@suse.cz>
PR fortran/110677
* resolve.cc (resolve_structure_cons): Check comp->ts is character
type before accessing stuff through comp->ts.u.cl.
Chung-Lin Tang [Tue, 6 Jun 2023 10:46:29 +0000 (03:46 -0700)]
OpenACC 2.7: default clause support for data constructs
This patch implements the OpenACC 2.7 addition of default(none|present) support
for data constructs.
Now, specifying "default(none|present)" on a data construct turns on same
default clause behavior for all lexically enclosed compute constructs (which
don't already themselves have a default clause).
gcc/ChangeLog:
* gimplify.cc (oacc_region_type_name): New function.
(oacc_default_clause): If no 'default' clause appears on this
compute construct, see if one appears on a lexically containing
'data' construct.
(gimplify_scan_omp_clauses): Upon OMP_CLAUSE_DEFAULT case, set
ctx->oacc_default_clause_ctx to current context.
Richard Biener [Tue, 15 Aug 2023 12:39:15 +0000 (14:39 +0200)]
Cleanup BB vectorization roots handling
The following moves CONSTRUCTOR handling into the generic BB
vectorization roots handling, removing a special case and finally
renaming the function now consisting of more than just constructor
detection.
* tree-vect-slp.cc (vect_analyze_slp_instance): Remove
slp_inst_kind_ctor handling.
(vect_analyze_slp): Simplify.
(vect_build_slp_instance): Dump when we analyze a CTOR.
(vect_slp_check_for_constructors): Rename to ...
(vect_slp_check_for_roots): ... this. Register a
slp_root for CONSTRUCTORs instead of shoving them to
the set of grouped stores.
(vect_slp_analyze_bb_1): Adjust.
Richard Biener [Tue, 15 Aug 2023 11:05:32 +0000 (13:05 +0200)]
Support constants and externals in BB reduction vectorization
The following supports vectorizing BB reductions involving a
constant or an invariant.
* tree-vectorizer.h (_slp_instance::remain_stmts): Change
to ...
(_slp_instance::remain_defs): ... this.
(SLP_INSTANCE_REMAIN_STMTS): Rename to ...
(SLP_INSTANCE_REMAIN_DEFS): ... this.
(slp_root::remain): New.
(slp_root::slp_root): Adjust.
* tree-vect-slp.cc (vect_free_slp_instance): Adjust.
(vect_build_slp_instance): Get extra remain parameter,
adjust former handling of a cut off stmt.
(vect_analyze_slp_instance): Adjust.
(vect_analyze_slp): Likewise.
(_bb_vec_info::~_bb_vec_info): Likewise.
(vectorizable_bb_reduc_epilogue): Dump something if we fail.
(vect_slp_check_for_constructors): Handle non-internal
defs as remain defs of a reduction.
(vectorize_slp_instance_root_stmt): Adjust.
Richard Biener [Tue, 15 Aug 2023 08:31:07 +0000 (10:31 +0200)]
Use find_loop_location from unrolling
The following uses the common find_loop_location as implemented
by the vectorizer to query a loop location also for unrolling.
That results in a more consistent reporting of locations.
* tree-ssa-loop-ivcanon.cc: Include tree-vectorizer.h
(canonicalize_loop_induction_variables): Use find_loop_location.
Richard Biener [Thu, 10 Aug 2023 11:55:36 +0000 (13:55 +0200)]
tree-optimization/110963 - more PRE when optimizing for size
The following adjusts the heuristic when we perform PHI insertion
during GIMPLE PRE from requiring at least one edge that is supposed
to be optimized for speed to also doing insertion when the expression
is available on all edges (but possibly with different value) and
we'd at most have one copy from a constant. The first ensures
we optimize two computations on all paths to one plus a possible
copy due to the PHI, the second makes sure we do not need to insert
many possibly large copies from constants, disregarding the
cummulative size cost of the register copies when they are not
coalesced.
If we want to consider the cost of the register copies I think the
only simplistic enough way would be to restrict the special-case to
two incoming edges - we'd assume one register copy is coalesced
leaving one copy from a register or from a constant.
As with every optimization the downstream effects are probably
bigger than what we can locally estimate.
PR tree-optimization/110963
* tree-ssa-pre.cc (do_pre_regular_insertion): Also insert
a PHI node when the expression is available on all edges
and we insert at most one copy from a constant.
Richard Biener [Mon, 14 Aug 2023 07:31:18 +0000 (09:31 +0200)]
tree-optimization/110991 - unroll size estimate after vectorization
The following testcase shows that we are bad at identifying inductions
that will be optimized away after vectorizing them because SCEV doesn't
handle vectorized defs. The following rolls a simpler identification
of SSA cycles covering a PHI and an assignment with a binary operator
with a constant second operand.
PR tree-optimization/110991
* tree-ssa-loop-ivcanon.cc (constant_after_peeling): Handle
VIEW_CONVERT_EXPR <op>, handle more simple IV-like SSA cycles
that will end up constant.
Kewen Lin [Tue, 15 Aug 2023 08:01:20 +0000 (03:01 -0500)]
Makefile.in: Make recog.h depend on $(TREE_H) [PR111021]
Commit r14-3093 introduced a random build failure on
build/gencondmd.cc building. Since r14-3093 make recog.h
include tree.h, which further includes (depends on) some
files that are generated during the building, such as:
all-tree.def, tree-check.h etc, when building file
build/gencondmd.cc, the build can fail if these dependences
are not ready. So this patch is to teach this dependence.
Thank Jan-Benedict Glaw for testing this!
PR bootstrap/111021
gcc/ChangeLog:
* Makefile.in (RECOG_H): Add $(TREE_H) as dependence.
Kewen Lin [Tue, 15 Aug 2023 06:36:33 +0000 (01:36 -0500)]
vect: Move VMAT_LOAD_STORE_LANES handlings from final loop nest
Following Richi's suggestion [1], this patch is to move the
handlings on VMAT_LOAD_STORE_LANES in the final loop nest
of function vectorizable_load to its own loop. Basically
it duplicates the final loop nest, clean up some useless
set up code for the case of VMAT_LOAD_STORE_LANES, remove
some unreachable code. Also remove the corresponding
handlings in the final loop nest.
* tree-vect-stmts.cc (vectorizable_load): Move the handlings on
VMAT_LOAD_STORE_LANES in the final loop nest to its own loop,
and update the final nest accordingly.
Kewen Lin [Tue, 15 Aug 2023 06:36:23 +0000 (01:36 -0500)]
vect: Remove several useless VMAT_INVARIANT checks
In function vectorizable_load, there is one hunk which is
dedicated for the handlings on VMAT_INVARIANT and return
early, it means we shouldn't encounter any cases with
memory_access_type VMAT_INVARIANT in the following code
after that. This patch is to clean up several useless
checks on VMAT_INVARIANT. There should be no functional
changes.
gcc/ChangeLog:
* tree-vect-stmts.cc (vectorizable_load): Remove some useless checks
on VMAT_INVARIANT.
Unfortunately, SET_SRC requires at least 2 operands and then Segment
Fault here. For SH4 part result in Segment Fault, it looks like only
valid when the return_copy_pat is load or something like that. Thus,
this patch try to fix it by restrict the SET insn for SET_SRC.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* mode-switching.cc (create_pre_exit): Add SET insn check.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfrec7_frm): New class for frm.
(vfrec7_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfrec7_frm): New intrinsic function definition.
* config/riscv/vector-iterators.md
(VFMISC): Remove VFREC7.
(misc_op): Ditto.
(float_insn_type): Ditto.
(VFMISC_FRM): New int iterator.
(misc_frm_op): New op for frm.
(float_frm_insn_type): New type for frm.
* config/riscv/vector.md (@pred_<misc_frm_op><mode>):
New pattern for misc frm.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-rec7.c: New test.
[LRA]: Process output stack pointer reloads before emitting reload insns
Previous patch setting up asserts for processing stack pointer reloads
caught an error in code moving sp offset. This resulted in failure of
building aarch64 port. The code wrongly processed insns beyond the
output reloads of the current insn. This patch fixes it.
gcc/ChangeLog:
* lra-constraints.cc (curr_insn_transform): Process output stack
pointer reloads before emitting reload insns.
Mikael Morin [Mon, 14 Aug 2023 19:51:54 +0000 (21:51 +0200)]
fortran: Fix length one character dummy arg type [PR110419]
Revision r14-2171-g8736d6b14a4dfdfb58c80ccd398981b0fb5d00aa
changed the argument passing convention for length 1 value dummy
arguments to pass just the single character by value. However, the
procedure declarations weren't updated to reflect the change in the
argument types.
This change does the missing argument type update.
The change of argument types generated an internal error in
gfc_conv_string_parameter with value_9.f90. Indeed, that function is
not prepared for bare character type, so it is updated as well.
The condition guarding the single character argument passing code
is loosened to not exclude non-interoperable kind (this fixes
a regression with c_char_tests_2.f03).
Finally, the constant string argument passing code is updated as well
to extract the single char and pass it instead of passing it as
a length one string. As the code taking care of non-constant arguments
was already doing this, the condition guarding it is just removed.
With these changes, value_9.f90 passes on 32 bits big-endian powerpc.
PR fortran/110360
PR fortran/110419
gcc/fortran/ChangeLog:
* trans-types.cc (gfc_sym_type): Use a bare character type for length
one value character dummy arguments.
* trans-expr.cc (gfc_conv_string_parameter): Handle single character
case.
(gfc_conv_procedure_call): Don't exclude interoperable kinds
from single character handling. For single character dummy arguments,
extend the existing handling of non-constant expressions to constant
expressions.
gcc/testsuite/ChangeLog:
* gfortran.dg/bind_c_usage_13.f03: Update tree dump patterns.
benjamin priour [Mon, 14 Aug 2023 15:36:21 +0000 (17:36 +0200)]
analyzer: New option fanalyzer-show-events-in-system-headers [PR110543]
This patch introduces -fanalyzer-show-events-in-system-headers,
disabled by default.
This option reduces the noise of the analyzer emitted diagnostics
when dealing with system headers.
The new option only affects the display of the diagnostics,
but doesn't hinder the actual analysis.
Given a diagnostics path diving into a system header in the form
[
prefix events...,
system header call,
system header entry,
events within system headers...,
system header return,
suffix events...
]
then disabling the option (either by default or explicitly)
will shorten the path into:
[
prefix events...,
system header call,
system header return,
suffix events...
]
Signed-off-by: benjamin priour <priour.be@gmail.com>
gcc/analyzer/ChangeLog:
PR analyzer/110543
* analyzer.opt: Add new option.
* diagnostic-manager.cc
(diagnostic_manager::prune_path): Call prune_system_headers.
(prune_frame): New function that deletes all events in a frame.
(diagnostic_manager::prune_system_headers): New function.
* diagnostic-manager.h: Add prune_system_headers declaration.
gcc/ChangeLog:
PR analyzer/110543
* doc/invoke.texi: Add documentation of
fanalyzer-show-events-in-system-headers
gcc/testsuite/ChangeLog:
PR analyzer/110543
* g++.dg/analyzer/fanalyzer-show-events-in-system-headers-default.C:
New test.
* g++.dg/analyzer/fanalyzer-show-events-in-system-headers-no.C:
New test.
* g++.dg/analyzer/fanalyzer-show-events-in-system-headers.C:
New test.
gnaggnoyil [Sat, 12 Aug 2023 08:16:52 +0000 (16:16 +0800)]
c++: follow DR 2386 and update implementation of get_tuple_size [PR110216]
DR 2386 updated the tuple_size requirements for structured binding and
it now requires tuple_size to be considered only if
std::tuple_size<TYPE> names a complete class type with member value. GCC
before this patch does not follow the updated requrements, and this
patch is intended to implement it.
(jason) Accepting pseudonym sign-off because a change this small is not
legally significant for copyright.
DR 2386
PR c++/110216
gcc/cp/ChangeLog:
* decl.cc (get_tuple_size): Update implementation for DR 2386.
gcc/testsuite/ChangeLog:
* g++.dg/cpp1z/decomp10.C: Update expected error for DR 2386.
* g++.dg/cpp1z/pr110216.C: New test.
Signed-off-by: gnaggnoyil <gnaggnoyil@gmail.com> Reviewed-by: Jason Merrill <jason@redhat.com>
Jason Merrill [Fri, 23 Jun 2023 17:54:07 +0000 (13:54 -0400)]
c++: -fconcepts and __cpp_concepts
Since -fconcepts no longer implies -fconcepts-ts, we shouldn't advertise TS
support with __cpp_concepts=201507L. Also fix one case where -std=c++14
-fconcepts wasn't working (as found by range-v3 calendar). Fixing other
cases is not a priority, probably better to reject that flag combination if
there are further issues.
Paul Dreik [Mon, 14 Aug 2023 14:42:33 +0000 (15:42 +0100)]
libstdc++: Avoid problematic use of log10 in std::format [PR110860]
If abs(__v) is smaller than one, the result will be of the
form 0.xxxxx. It is only if the magnitude is large that more digits
are needed before the decimal dot.
This uses frexp instead of log10 which should be less expensive
and have sufficient precision for the desired purpose.
It removes the problematic cases where log10 will be negative or not
fit in an int.
Signed-off-by: Paul Dreik <gccpatches@pauldreik.se>
libstdc++-v3/ChangeLog:
PR libstdc++/110860
* include/std/format (__formatter_fp::format): Use frexp instead
of log10.
Jiawei [Wed, 7 Jun 2023 12:56:39 +0000 (20:56 +0800)]
RISC-V: Minimal support for ZC* extensions.
This patch is the minimal support for ZC* extensions, include the extension
name, mask and target defination. Also define the dependencies with Zca
and Zce extension. Notes that all ZC* extensions depend on the Zca extension.
Zce includes all relevant ZC* extensions for microcontrollers using. Zce
will imply zcf when 'f' extension enabled in rv32.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class unop_frm): New class for frm.
(vfsqrt_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfsqrt_frm): New intrinsic function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-sqrt.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfwnmsac_frm): New class for frm.
(vfwnmsac_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwnmsac_frm): New intrinsic function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-wnmsac.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfwmsac_frm): New class for frm.
(vfwmsac_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwmsac_frm): New intrinsic function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-wmsac.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfwnmacc_frm): New class for frm.
(vfwnmacc_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwnmacc_frm): New intrinsic function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-wnmacc.c: New test.
When LRA is in progress, it can try and validate insns
half-way through frame-pointer (FP) to stack-pointer (SP)
elimination. Operands have then been substituted where the
offset is from the SP elimination but the register is the
(hard) frame-pointer:
lra-eliminations.cc:lra_eliminate_regs_1:370:
rtx to = subst_p ? ep->to_rtx : ep->from_rtx;
In this regard reload played nicely. Unfortunately, the
frame_pointer_operand predicate in mmix/predicates.md barfs
on such an address. This broke the use of the MMIX
frame_pointer_operand predicate (and the Yf constraint),
used only in the nonlocal_goto_receiver expansion (which is
used in e.g. code generated for C++ "catch").
Force MMIX frame_pointer_operand to accept an FP+offset for
the duration of lra_in_progress.
* config/mmix/predicates.md (frame_pointer_operand): Handle FP+offset
when lra_in_progress.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfwmacc_frm): New class for vfwmacc frm.
(vfwmacc_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwmacc_frm): Function definition for vfwmacc.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_widen_ternop_insn): Add frm support.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-fwmacc.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfnmsub_frm): New class for vfnmsub frm.
(vfnmsub_frm): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfnmsub_frm): New function declaration.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-nmsub.c: New test.
Gaius Mulley [Sat, 12 Aug 2023 17:17:41 +0000 (18:17 +0100)]
PR modula2/110779 SysClock can not read the clock (Darwin portability fixes)
This patch adds corrections to defensively check against glibc functions,
structures and contains fallbacks. These fixes were required under Darwin.
gcc/m2/ChangeLog:
PR modula2/110779
* gm2-libs-iso/SysClock.mod (EpochTime): New procedure.
(GetClock): Call EpochTime if the C time functions are
unavailable.
* gm2-libs-iso/wrapclock.def (istimezone): New function
definition.
libgm2/ChangeLog:
PR modula2/110779
* configure: Regenerate.
* configure.ac: Provide special case test for Darwin cross
configuration.
(GLIBCXX_CONFIGURE): New statement.
(GLIBCXX_CHECK_GETTIMEOFDAY): New statement.
(GLIBCXX_ENABLE_LIBSTDCXX_TIME): New statement.
* libm2iso/wrapclock.cc: New sys/time.h conditional include.
(sys/syscall.h): Conditional include.
(unistd.h): Conditional include.
(GetTimeRealtime): Re-implement.
(SetTimeRealtime): Re-implement.
(timezone): Re-implement.
(istimezone): New function.
(daylight): Re-implement.
(isdst): Re-implement.
(tzname): Re-implement.
Gaius Mulley [Sat, 12 Aug 2023 12:43:14 +0000 (13:43 +0100)]
PR modula2/108119 disable m2rte plugin by default
This patch disables the m2rte plugin by default. The driver
will only append the -fplugin=m2rte command line option for cc1gm2
if -fm2-plugin is present. It only enabled providing ENABLE_PLUGIN
is defined. gcc/m2/Make-file.in will only build and install m2rte
if enable_plugin is yes.
gcc/m2/ChangeLog:
PR modula2/108119
* Make-lang.in (M2RTE_PLUGIN_SO): Assigned to
plugin/m2rte$(exeext).so if enable_plugin is yes.
(m2.all.cross): Replace plugin/m2rte$(soext) with
$(M2RTE_PLUGIN_SO).
(m2.all.encap): Replace plugin/m2rte$(soext) with
$(M2RTE_PLUGIN_SO).
(m2.install-plugin): Add dummy rule when enable_plugin
is not yes.
(plugin/m2rte$(exeext).so): Add dummy rule when enable_plugin
is not yes.
(m2/stage2/cc1gm2$(exeext)): Replace plugin/m2rte$(soext) with
$(M2RTE_PLUGIN_SO).
(m2/stage1/cc1gm2$(exeext)): Replace plugin/m2rte$(soext) with
$(M2RTE_PLUGIN_SO).
* gm2spec.cc (lang_specific_driver): Set need_plugin to false
by default.
Jakub Jelinek [Sat, 12 Aug 2023 07:42:58 +0000 (09:42 +0200)]
Add stdckdint.h header for C23
This patch adds <stdckdint.h> header, which defines ckd_{add,sub,mul}
using __builtin_{add,sub,mul}_overflow. As requested, it doesn't
pedantically diagnose things which work just fine, e.g. inputs with
plain char, bool, bit-precise integer or enumerated types and
result pointer to plain char or bit-precise integer.
The header will #include_next <stdckdint.h> so that C library can supply
its part if the header implementation in the future needs to be split
between parts under the control of the compiler and parts under the
control of C library.
2023-08-12 Jakub Jelinek <jakub@redhat.com>
* Makefile.in (USER_H): Add stdckdint.h.
* ginclude/stdckdint.h: New file.
* gcc.dg/stdckdint-1.c: New test.
* gcc.dg/stdckdint-2.c: New test.
Patrick Palka [Sat, 12 Aug 2023 01:13:52 +0000 (21:13 -0400)]
tree-pretty-print: delimit TREE_VEC with braces
This makes the generic pretty printer print braces around a TREE_VEC,
like we do for CONSTRUCTOR. This should improve readability of nested
TREE_VECs in particular.
gcc/ChangeLog:
* tree-pretty-print.cc (dump_generic_node) <case TREE_VEC>:
Delimit output with braces.
Patrick Palka [Sat, 12 Aug 2023 01:13:23 +0000 (21:13 -0400)]
c++: bogus warning w/ deduction guide in anon ns [PR106604]
Here we're unintentionally issuing a "declared static but never defined"
warning from wrapup_namespace_globals for a deduction guide declared in
an anonymous namespace. This patch fixes this by giving deduction guides
a dummy DECL_INITIAL, which suppresses the warning and also allows us to
simplify redeclaration checking for them.
Co-authored-by: Jason Merrill <jason@redhat.com>
PR c++/106604
gcc/cp/ChangeLog:
* decl.cc (redeclaration_error_message): Remove special handling
for deduction guides.
(grokfndecl): Give deduction guides a dummy DECL_INITIAL.
gcc/testsuite/ChangeLog:
* g++.dg/cpp1z/class-deduction74.C: Expect "defined" instead
of "declared" in the repeated deduction guide diagnostics.
* g++.dg/cpp1z/class-deduction116.C: New test.
Ken Matsui [Sat, 15 Jul 2023 02:55:35 +0000 (19:55 -0700)]
libstdc++: Use __bool_constant entirely
This patch uses __bool_constant entirely instead of integral_constant<bool>
in the type_traits header, specifically for true_type, false_type,
and bool_constant.
libstdc++-v3/ChangeLog:
* include/std/type_traits (true_type): Use __bool_constant
instead.
(false_type): Likewise.
(bool_constant): Likewise.
Signed-off-by: Ken Matsui <kmatsui@gcc.gnu.org> Reviewed-by: Jonathan Wakely <jwakely@redhat.com>
* gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS CONST_VECTOR tests.
* gcc.target/riscv/rvv/autovec/vls/const-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/const-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/const-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/const-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/const-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/series-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/series-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/series-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/series-4.c: New test.
Jonathan Wakely [Fri, 11 Aug 2023 22:02:44 +0000 (23:02 +0100)]
libstdc++: Fix std::format_to_n return value [PR110990]
When writing to a contiguous iterator, std::format_to_n(out, n, ...)
always returns out + n, even if it wrote fewer than n characters to the
iterator.
The problem is in the _M_finish() member function of the _Iter_sink
specialization for contiguous iterators. _M_finish() calls _M_overflow()
to update its count of characters written, so it can return the count of
characters that would be written if there was room. But _M_overflow()
assumes it's only called when the buffer is full, and so switches to the
internal buffer. _M_finish() then thinks that if the internal buffer is
in use, we already wrote at least n characters and so returns out+n as
the output position.
We can fix the problem by adding a check in _M_overflow() so that we
don't update the count and switch to the internal buffer unless we've
run out of room, i.e. _M_unused().size() is zero. The caller then needs
to be prepared for _M_count not being the final total, and so add
_M_used.size() to it.
However, there's not actually any need for _M_finish() to call
_M_overflow() to get the count. We now need to use _M_count and
_M_used.size() to get the total anyway so _M_overflow() doesn't help
with that. And we don't need to use _M_overflow() to flush unwritten
characters to the output, because the specialization for contiguous
iterators always writes directly to the output without buffering (except
when we've exceeded the maximum number of characters, in which case we
want to discard the buffered characters anyway). So _M_finish() can be
simplified and can avoid calling _M_overflow().
This change also fixes some member functions of other sink classes to
only call _M_overflow() when there are characters in the buffer, which
is needed to meet _M_overflow's precondition that _M_used().size()!=0.
libstdc++-v3/ChangeLog:
PR libstdc++/110990
* include/std/format (_Seq_sink::get): Only call _M_overflow if
its precondition is met.
(_Iter_sink::_M_finish): Likewise.
(_Iter_sink<C, ContigIter>::_M_overflow): Only switch to the
internal buffer after running out of space.
(_Iter_sink<C, ContigIter>::_M_finish): Do not use _M_overflow.
(_Counting_sink::count): Likewise.
* testsuite/std/format/functions/format_to_n.cc: Check cases
where the output fits into the buffer.
David Malcolm [Fri, 11 Aug 2023 22:05:48 +0000 (18:05 -0400)]
analyzer: new warning: -Wanalyzer-unterminated-string [PR105899]
This patch adds new functions to the analyzer for checking that
an argument at a callsite is a pointer to a valid null-terminated
string, and uses this for the following known functions:
- error (param 3, the format string)
- error_at_line (param 5, the format string)
- putenv
- strchr (1st param)
- strcpy (2nd param)
- strdup
Currently the check merely detects pointers to unterminated string
constants, and adds a new -Wanalyzer-unterminated-string to complain
about that. I'm experimenting with detecting other ways in which
a buffer can fail to be null-terminated, and for other problems with
such buffers, but this patch at least adds the framework for wiring
up the check to specific parameters of known_functions.
gcc/analyzer/ChangeLog:
PR analyzer/105899
* analyzer.opt (Wanalyzer-unterminated-string): New.
* call-details.cc
(call_details::check_for_null_terminated_string_arg): New.
* call-details.h
(call_details::check_for_null_terminated_string_arg): New decl.
* kf-analyzer.cc (class kf_analyzer_get_strlen): New.
(register_known_analyzer_functions): Register it.
* kf.cc (kf_error::impl_call_pre): Check that format arg is a
valid null-terminated string.
(kf_putenv::impl_call_pre): Likewise for the sole param.
(kf_strchr::impl_call_pre): Likewise for the first param.
(kf_strcpy::impl_call_pre): Likewise for the second param.
(kf_strdup::impl_call_pre): Likewise for the sole param.
* region-model.cc (get_strlen): New.
(struct call_arg_details): New.
(inform_about_expected_null_terminated_string_arg): New.
(class unterminated_string_arg): New.
(region_model::check_for_null_terminated_string_arg): New.
* region-model.h
(region_model::check_for_null_terminated_string_arg): New decl.
Jeff Law [Fri, 11 Aug 2023 21:52:57 +0000 (15:52 -0600)]
[committed] Fix subdi3 synthesis on rx port
Some of Andrew's recent match.pd changes triggered a regression in my tester
for the rx processor for c-torture/execute/pr66940.c which would be exposed
only during an LTO compilation.
Specifically the subdi3_internal pattern had the wrong idiom to detect a carry
from the high word into the low word. It had the wrong opcode and the operands
were reversed.
This resulted in combine doing a simplification that was valid according to the
presented RTL, but which ultimately got the wrong result.
I would often say this was a latent bug. But the testsuite shows
builtin-arith-overflow-14 and builtin-arith-overflow-p18 failures are fixed as
well. So it's been visible indefinitely, but nobody's ever looked into those
failures.
Committed to the trunk.
gcc/
* config/rx/rx.md (subdi3): Fix test for borrow.
The MASK_LEN_LOAD is using real MASK which is produced by the EQ comparison wheras the LEN
is the dummy LEN which is the vectorization factor.
In this situation, we didn't enter 'vect_record_loop_len' since there is no LEN loop control.
Then 'LOOP_VINFO_RGROUP_IV_TYPE' is not suitable type for 'build_int_cst' used for producing
LEN argument for 'MASK_LEN_LOAD', so use sizetype instead which is perfectly matching
RVV length requirement.
I've implemented my proposed resolutions to LWG issues 3960, 3961, and
3962. There are some unimplemented flags such as %OI which I think are
not implementable in general. It might be possible to use na_llanginfo
with ALT_DIGITS, but that isn't available on all targets. I intend to
file another LWG issue about that.
libstdc++-v3/ChangeLog:
PR libstdc++/104167
* include/bits/chrono_io.h (operator|=, operator|): Add noexcept
to _ChronoParts operators.
(from_stream, parse): Define new functions.
(__detail::_Parse, __detail::_Parser): New class templates.
* include/std/chrono (__cpp_lib_chrono): Define to 201907L for
C++20.
* include/std/version (__cpp_lib_chrono): Likewise.
* testsuite/20_util/duration/arithmetic/constexpr_c++17.cc:
Adjust expected value of feature test macro.
* testsuite/20_util/duration/io.cc: Test parsing.
* testsuite/std/time/clock/file/io.cc: Likewise.
* testsuite/std/time/clock/gps/io.cc: Likewise.
* testsuite/std/time/clock/system/io.cc: Likewise.
* testsuite/std/time/clock/tai/io.cc: Likewise.
* testsuite/std/time/clock/utc/io.cc: Likewise.
* testsuite/std/time/day/io.cc: Likewise.
* testsuite/std/time/month/io.cc: Likewise.
* testsuite/std/time/month_day/io.cc: Likewise.
* testsuite/std/time/weekday/io.cc: Likewise.
* testsuite/std/time/year/io.cc: Likewise.
* testsuite/std/time/year_month/io.cc: Likewise.
* testsuite/std/time/year_month_day/io.cc: Likewise.
* testsuite/std/time/syn_c++20.cc: Check value of macro and for
the existence of parse and from_stream in namespace chrono.
* testsuite/std/time/clock/local/io.cc: New test.
* testsuite/std/time/parse.cc: New test.
Jose E. Marchesi [Thu, 10 Aug 2023 19:17:53 +0000 (21:17 +0200)]
bpf: liberate R9 for general register allocation
We were reserving one of the hard registers in BPF in order to
implement dynamic stack allocation: alloca and VLAs. However, there is
kernel code that has inline assembly that requires all the non-fixed
registers to be available for register allocation.
This patch:
1. Liberates r9 that is now available for register allocation.
2. Adds a check to GCC so it errors out if the user tries to do
dynamic stack allocation. A couple of tests are added for this.
3. Changes xbpf so it no longer saves and restores callee-saved
registers. A couple of tests for this have been removed.
4. Adds bpf-*-* to the list of targets that do not support alloca in
target-support.exp.
Tested in host x86_64-linux-gnu and target bpf-unknown-none.
gcc/ChangeLog
* config/bpf/bpf.md (allocate_stack): Define.
* config/bpf/bpf.h (FIRST_PSEUDO_REGISTER): Make room for fake
stack pointer register.
(FIXED_REGISTERS): Adjust accordingly.
(CALL_USED_REGISTERS): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(REGISTER_NAMES): Likewise.
* config/bpf/bpf.cc (bpf_compute_frame_layout): Do not reserve
space for callee-saved registers.
(bpf_expand_prologue): Do not save callee-saved registers in xbpf.
(bpf_expand_epilogue): Do not restore callee-saved registers in
xbpf.
gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_effective_target_alloca): BPF
target does not support alloca.
* gcc.target/bpf/diag-alloca-1.c: New test.
* gcc.target/bpf/diag-alloca-2.c: Likewise.
* gcc.target/bpf/xbpf-callee-saved-regs-1.c: Remove test.
* gcc.target/bpf/xbpf-callee-saved-regs-2.c: Likewise.
* gcc.target/bpf/regs-availability-1.c: Likewise.
Jose E. Marchesi [Thu, 10 Aug 2023 08:53:16 +0000 (10:53 +0200)]
bpf: allow exceeding max num of args in BPF when always_inline
BPF currently limits the number of registers used to pass arguments to
functions to five registers. There is a check for this at function
expansion time. However, if a function is guaranteed to be always
inlined (and its body never generated) by virtue of the always_inline
attribute, it can "receive" any number of arguments.
Tested in host x86_64-linux-gnu and target bpf-unknown-none.
gcc/ChangeLog
* config/bpf/bpf.cc (bpf_function_arg_advance): Do not complain
about too many arguments if function is always inlined.
gcc/testsuite/ChangeLog
* gcc.target/bpf/diag-funargs-inline-1.c: New test.
* gcc.target/bpf/diag-funargs.c: Adapt test.
Eric Feng [Fri, 11 Aug 2023 16:30:43 +0000 (12:30 -0400)]
analyzer: More features for CPython analyzer plugin [PR107646]
This patch adds known function subclasses for Python/C API functions
PyList_New, PyLong_FromLong, and PyList_Append. It also adds new
optional parameters for
region_model::get_or_create_region_for_heap_alloc, allowing for the
newly allocated region to immediately transition from the start state to
the assumed non-null state in the malloc state machine if desired.
Finally, it adds a new procedure, dg-require-python-h, intended as a
directive in Python-related analyzer tests, to append necessary Python
flags during the tests' build process.
The main warnings we gain in this patch with respect to the known function
subclasses mentioned are leak related. For example:
Some concessions were made to
simplify the analysis process when comparing kf_PyList_Append with the
real implementation. In particular, PyList_Append performs some
optimization internally to try and avoid calls to realloc if
possible. For simplicity, we assume that realloc is called every time.
Also, we grow the size by just 1 (to ensure enough space for adding a
new element) rather than abide by the heuristics that the actual implementation
follows.
gcc/analyzer/ChangeLog:
PR analyzer/107646
* call-details.h: New function.
* region-model.cc (region_model::get_or_create_region_for_heap_alloc):
New optional parameters.
* region-model.h (class region_model): New optional parameters.
* sm-malloc.cc (on_realloc_with_move): New function.
(region_model::transition_ptr_sval_non_null): New function.
gcc/testsuite/ChangeLog:
PR analyzer/107646
* gcc.dg/plugin/analyzer_cpython_plugin.c: Analyzer support for
PyList_New, PyList_Append, PyLong_FromLong
* gcc.dg/plugin/plugin.exp: New test.
* lib/target-supports.exp: New procedure.
* gcc.dg/plugin/cpython-plugin-test-2.c: New test.
git://gcc.gnu.org / gcc.git / log