From: Jan Hubicka Date: Fri, 16 Mar 2001 13:51:49 +0000 (+0100) Subject: i386.c (ix86_expand_fp_movcc): Do not attempt to construct SSE based conditional... X-Git-Tag: prereleases/libstdc++-2.92~385 X-Git-Url: https://gcc.gnu.org/git/?a=commitdiff_plain;h=fa9f36a17be531a83a102a9562613c698566ce05;p=gcc.git i386.c (ix86_expand_fp_movcc): Do not attempt to construct SSE based conditional moves on LTGT/UNEQ conditions... * i386.c (ix86_expand_fp_movcc): Do not attempt to construct SSE based conditional moves on LTGT/UNEQ conditions; Canonicalize EQ to NE. * i386.md (sse_mov?fcc): Disallow EQ and NE in IEEE mode. (sse_mov?fcc_ne): New. * i386-protos.h (sign_extended_value, zero_extended_value): Declare. From-SVN: r40554 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7d3d804e43c7..27699c80f23d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +Fri Mar 16 14:47:57 CET 2001 Jan Hubicka + + * i386.c (ix86_expand_fp_movcc): Do not attempt to construct + SSE based conditional moves on LTGT/UNEQ conditions; + Canonicalize EQ to NE. + * i386.md (sse_mov?fcc): Disallow EQ and NE in IEEE mode. + (sse_mov?fcc_ne): New. + + * i386-protos.h (sign_extended_value, zero_extended_value): Declare. + 2001-03-16 Alexandre Oliva * config/sh/sh.c (sh_expand_prologue): Insns that set up the PIC diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h index 60b2998100e8..e4639a34b61b 100644 --- a/gcc/config/i386/i386-protos.h +++ b/gcc/config/i386/i386-protos.h @@ -128,6 +128,9 @@ extern int ix86_sched_reorder PARAMS ((FILE *, int, rtx *, int, int)); extern int ix86_variable_issue PARAMS ((FILE *, int, rtx, int)); extern enum machine_mode ix86_fp_compare_mode PARAMS ((enum rtx_code)); +extern int x86_64_sign_extended_value PARAMS ((rtx)); +extern int x86_64_zero_extended_value PARAMS ((rtx)); + extern rtx ix86_force_to_memory PARAMS ((enum machine_mode, rtx)); extern void ix86_free_from_memory PARAMS ((enum machine_mode)); extern void ix86_split_fp_branch PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx)); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 16dfe454b397..20b7eca7eb57 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1844,7 +1844,7 @@ x86_64_sign_extended_value (value) else { HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (value), DImode); - return (HOST_WIDE_INT)(int)val == val; + return trunc_int_for_mode (val, SImode) == val; } break; @@ -6312,6 +6312,9 @@ ix86_expand_fp_movcc (operands) if (((TARGET_SSE && GET_MODE (operands[0]) == SFmode) || (TARGET_SSE2 && GET_MODE (operands[0]) == DFmode)) && GET_MODE (ix86_compare_op0) == GET_MODE (operands[0]) + /* The SSE comparisons does not support the LTGT/UNEQ pair. */ + && (!TARGET_IEEE_FP + || (GET_CODE (operands[1]) != LTGT && GET_CODE (operands[1]) != UNEQ)) /* We may be called from the post-reload splitter. */ && (!REG_P (operands[0]) || SSE_REG_P (operands[0]) @@ -6371,8 +6374,10 @@ ix86_expand_fp_movcc (operands) ix86_compare_op1); } /* Similary try to manage result to be first operand of conditional - move. */ - if (rtx_equal_p (operands[0], operands[3])) + move. We also don't support the NE comparison on SSE, so try to + avoid it. */ + if (rtx_equal_p (operands[0], operands[3]) + || GET_CODE (operands[1]) == NE) { rtx tmp = operands[2]; operands[2] = operands[3]; diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index c700f2317b02..1f36c5fd78eb 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -12830,6 +12830,9 @@ ;; based moves emulation or to usual cmove sequence. Little bit unfortunate ;; fact is that compares supported by the cmp??ss instructions are exactly ;; swapped of those supported by cmove sequence. +;; The EQ/NE comparisons also needs bit care, since they are not directly +;; supported by i387 comparisons and we do need to emit two conditional moves +;; in tandem. (define_insn "sse_movsfcc" [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf") @@ -12840,6 +12843,20 @@ (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx"))) (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X")) (clobber (reg:CC 17))] + "TARGET_SSE + && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM) + && (!TARGET_IEEE_FP + || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))" + "#") + +(define_insn "sse_movsfcc_eq" + [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf") + (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f") + (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f")) + (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx") + (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx"))) + (clobber (match_scratch:SF 5 "=1,&4,X,X,X,X")) + (clobber (reg:CC 17))] "TARGET_SSE && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" "#") @@ -12854,6 +12871,20 @@ (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X")) (clobber (reg:CC 17))] "TARGET_SSE2 + && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM) + && (!TARGET_IEEE_FP + || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))" + "#") + +(define_insn "sse_movdfcc_eq" + [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf") + (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f") + (match_operand:DF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f")) + (match_operand:DF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx") + (match_operand:DF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx"))) + (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X")) + (clobber (reg:CC 17))] + "TARGET_SSE && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" "#")