From: Segher Boessenkool Date: Mon, 20 May 2019 00:11:34 +0000 (+0200) Subject: rs6000: Delete "wJ" and "wK" constraints X-Git-Tag: misc/cutover-git~5414 X-Git-Url: https://gcc.gnu.org/git/?a=commitdiff_plain;h=0c8ac746d1ccfaa429693c4869b08222e447ceed;p=gcc.git rs6000: Delete "wJ" and "wK" constraints This replaces "wJ" by "wI", and "wK by "wH", both with isa "p9v". * config/rs6000/constraints.md (define_register_constraint "wJ"): Delete. (define_register_constraint "wK"): Delete. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete RS6000_CONSTRAINT_wJ and RS6000_CONSTRAINT_wK. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. (rs6000_init_hard_regno_mode_ok): Adjust. * config/rs6000/rs6000.md: Replace "wJ" constraint by "wI" with "p9v". Replace "wK" constraint by "wH" with "p9v". * config/rs6000/vsx.md: Ditto. * doc/md.texi (Machine Constraints): Adjust. From-SVN: r271387 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 19a683c276dc..ae997cb23ff5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2019-05-19 Segher Boessenkool + + * config/rs6000/constraints.md (define_register_constraint "wJ"): + Delete. + (define_register_constraint "wK"): Delete. + * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete + RS6000_CONSTRAINT_wJ and RS6000_CONSTRAINT_wK. + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. + (rs6000_init_hard_regno_mode_ok): Adjust. + * config/rs6000/rs6000.md: Replace "wJ" constraint by "wI" with "p9v". + Replace "wK" constraint by "wH" with "p9v". + * config/rs6000/vsx.md: Ditto. + * doc/md.texi (Machine Constraints): Adjust. + 2019-05-19 Segher Boessenkool * config/rs6000/constraints.md (define_register_constraint "wb"): diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 1bbfe714c21d..38a4307c2920 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -157,12 +157,6 @@ (define_register_constraint "wI" "rs6000_constraints[RS6000_CONSTRAINT_wI]" "FPR register to hold 32-bit integers or NO_REGS.") -(define_register_constraint "wJ" "rs6000_constraints[RS6000_CONSTRAINT_wJ]" - "FPR register to hold 8/16-bit integers or NO_REGS.") - -(define_register_constraint "wK" "rs6000_constraints[RS6000_CONSTRAINT_wK]" - "Altivec register to hold 8/16-bit integers or NO_REGS.") - (define_constraint "wL" "Int constant that is the element number mfvsrld accesses in a vector." (and (match_code "const_int") diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index f89a86ff5b74..1a43a8d0c282 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2532,8 +2532,6 @@ rs6000_debug_reg_global (void) "wA reg_class = %s\n" "wH reg_class = %s\n" "wI reg_class = %s\n" - "wJ reg_class = %s\n" - "wK reg_class = %s\n" "\n", reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]], @@ -2562,9 +2560,7 @@ rs6000_debug_reg_global (void) reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wH]], - reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]], - reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wJ]], - reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wK]]); + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]]); nl = "\n"; for (m = 0; m < NUM_MACHINE_MODES; ++m) @@ -3192,9 +3188,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) wy - Register class to do ISA 2.07 SF operations. wz - Float register if we can do 32-bit unsigned int loads. wH - Altivec register if SImode is allowed in VSX registers. - wI - Float register if SImode is allowed in VSX registers. - wJ - Float register if QImode/HImode are allowed in VSX registers. - wK - Altivec register if QImode/HImode are allowed in VSX registers. */ + wI - Float register if SImode is allowed in VSX registers. */ if (TARGET_HARD_FLOAT) { @@ -3271,11 +3265,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) { rs6000_constraints[RS6000_CONSTRAINT_wH] = ALTIVEC_REGS; rs6000_constraints[RS6000_CONSTRAINT_wI] = FLOAT_REGS; - if (TARGET_P9_VECTOR) - { - rs6000_constraints[RS6000_CONSTRAINT_wJ] = FLOAT_REGS; - rs6000_constraints[RS6000_CONSTRAINT_wK] = ALTIVEC_REGS; - } } /* Set up the reload helper and direct move functions. */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 2f2e45fd67ff..85dd8411d5b7 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1273,8 +1273,6 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ RS6000_CONSTRAINT_wH, /* Altivec register for 32-bit integers. */ RS6000_CONSTRAINT_wI, /* VSX register for 32-bit integers. */ - RS6000_CONSTRAINT_wJ, /* VSX register for 8/16-bit integers. */ - RS6000_CONSTRAINT_wK, /* Altivec register for 16/32-bit integers. */ RS6000_CONSTRAINT_MAX }; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 791aca783c5e..b5ccb03ba437 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -726,15 +726,16 @@ ;; complex forms. Basic data transfer is done later. (define_insn "zero_extendqi2" - [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r,^wJwK,^wK") - (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r,Z,wK")))] + [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r,^wIwH,^wH") + (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r,Z,wH")))] "" "@ lbz%U1%X1 %0,%1 rlwinm %0,%1,0,0xff lxsibzx %x0,%y1 vextractub %0,%1,7" - [(set_attr "type" "load,shift,fpload,vecperm")]) + [(set_attr "type" "load,shift,fpload,vecperm") + (set_attr "isa" "*,*,p9v,p9v")]) (define_insn_and_split "*zero_extendqi2_dot" [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") @@ -779,15 +780,16 @@ (define_insn "zero_extendhi2" - [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,^wJwK,^wK") - (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,wK")))] + [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,^wIwH,^wH") + (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,wH")))] "" "@ lhz%U1%X1 %0,%1 rlwinm %0,%1,0,0xffff lxsihzx %x0,%y1 vextractuh %0,%1,6" - [(set_attr "type" "load,shift,fpload,vecperm")]) + [(set_attr "type" "load,shift,fpload,vecperm") + (set_attr "isa" "*,*,p9v,p9v")]) (define_insn_and_split "*zero_extendhi2_dot" [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") @@ -832,8 +834,8 @@ (define_insn "zero_extendsi2" - [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wz,wu,wj,r,wJwK") - (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wIwH,wJwK")))] + [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wz,wu,wj,r,wIwH") + (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wIwH,wIwH")))] "" "@ lwz%U1%X1 %0,%1 @@ -843,7 +845,8 @@ mtvsrwz %x0,%1 mfvsrwz %0,%x1 xxextractuw %x0,%x1,4" - [(set_attr "type" "load,shift,fpload,fpload,mffgpr,mftgpr,vecexts")]) + [(set_attr "type" "load,shift,fpload,fpload,mffgpr,mftgpr,vecexts") + (set_attr "isa" "*,*,*,*,*,*,p9v")]) (define_insn_and_split "*zero_extendsi2_dot" [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") @@ -888,13 +891,14 @@ (define_insn "extendqi2" - [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,?*wK") - (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,?*wK")))] + [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,?*wH") + (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,?*wH")))] "" "@ extsb %0,%1 vextsb2d %0,%1" - [(set_attr "type" "exts,vecperm")]) + [(set_attr "type" "exts,vecperm") + (set_attr "isa" "*,p9v")]) (define_insn_and_split "*extendqi2_dot" [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") @@ -945,8 +949,8 @@ "") (define_insn "*extendhi2" - [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,?*wK,?*wK") - (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,wK")))] + [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,?*wH,?*wH") + (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,wH")))] "" "@ lha%U1%X1 %0,%1 @@ -955,7 +959,8 @@ vextsh2d %0,%1" [(set_attr "type" "load,exts,fpload,vecperm") (set_attr "sign_extend" "yes") - (set_attr "length" "4,4,8,4")]) + (set_attr "length" "4,4,8,4") + (set_attr "isa" "*,*,p9v,p9v")]) (define_split [(set (match_operand:EXTHI 0 "altivec_register_operand") @@ -1014,10 +1019,10 @@ (define_insn "extendsi2" [(set (match_operand:EXTSI 0 "gpc_reg_operand" - "=r, r, wl, wu, wj, wK, wH, wr") + "=r, r, wl, wu, wj, wH, wH, wr") (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand" - "YZ, r, Z, Z, r, wK, wH, ?wIwH")))] + "YZ, r, Z, Z, r, wH, wH, ?wIwH")))] "" "@ lwa%U1%X1 %0,%1 @@ -1030,7 +1035,8 @@ #" [(set_attr "type" "load,exts,fpload,fpload,mffgpr,vecexts,vecperm,mftgpr") (set_attr "sign_extend" "yes") - (set_attr "length" "4,4,4,4,4,4,8,8")]) + (set_attr "length" "4,4,4,4,4,4,8,8") + (set_attr "isa" "*,*,*,*,*,p9v,*,*")]) (define_split [(set (match_operand:EXTSI 0 "int_reg_operand") @@ -5218,8 +5224,8 @@ ; We don't define lfiwax/lfiwzx with the normal definition, because we ; don't want to support putting SImode in FPR registers. (define_insn "lfiwax" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wK") - (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wK")] + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wH") + (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wH")] UNSPEC_LFIWAX))] "TARGET_HARD_FLOAT && TARGET_LFIWAX" "@ @@ -5227,7 +5233,8 @@ lxsiwax %x0,%y1 mtvsrwa %x0,%1 vextsw2d %0,%1" - [(set_attr "type" "fpload,fpload,mffgpr,vecexts")]) + [(set_attr "type" "fpload,fpload,mffgpr,vecexts") + (set_attr "isa" "*,*,*,p9v")]) ; This split must be run before register allocation because it allocates the ; memory slot that is needed to move values to/from the FPR. We don't allocate @@ -5299,8 +5306,8 @@ (set_attr "type" "fpload")]) (define_insn "lfiwzx" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wJwK") - (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wJwK")] + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wIwH") + (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wIwH")] UNSPEC_LFIWZX))] "TARGET_HARD_FLOAT && TARGET_LFIWZX" "@ @@ -5308,7 +5315,8 @@ lxsiwzx %x0,%y1 mtvsrwz %x0,%1 xxextractuw %x0,%x1,4" - [(set_attr "type" "fpload,fpload,mftgpr,vecexts")]) + [(set_attr "type" "fpload,fpload,mftgpr,vecexts") + (set_attr "isa" "*,*,*,p9v")]) (define_insn_and_split "floatunssi2_lfiwzx" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") @@ -5552,10 +5560,10 @@ (define_insn_and_split "*float2_internal" [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=,,") (float:FP_ISA3 - (match_operand:QHI 1 "reg_or_indexed_operand" "wK,r,Z"))) - (clobber (match_scratch:DI 2 "=wK,wi,wK")) + (match_operand:QHI 1 "reg_or_indexed_operand" "wH,r,Z"))) + (clobber (match_scratch:DI 2 "=wH,wi,wH")) (clobber (match_scratch:DI 3 "=X,r,X")) - (clobber (match_scratch: 4 "=X,X,wK"))] + (clobber (match_scratch: 4 "=X,X,wH"))] "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64" "#" "&& reload_completed" @@ -5587,7 +5595,8 @@ emit_insn (gen_floatdi2 (result, di)); DONE; -}) +} + [(set_attr "isa" "p9v,*,p9v")]) (define_expand "floatuns2" [(parallel [(set (match_operand:FP_ISA3 0 "vsx_register_operand") @@ -5604,8 +5613,8 @@ (define_insn_and_split "*floatuns2_internal" [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=,,") (unsigned_float:FP_ISA3 - (match_operand:QHI 1 "reg_or_indexed_operand" "wK,r,Z"))) - (clobber (match_scratch:DI 2 "=wK,wi,wJwK")) + (match_operand:QHI 1 "reg_or_indexed_operand" "wH,r,Z"))) + (clobber (match_scratch:DI 2 "=wH,wi,wIwH")) (clobber (match_scratch:DI 3 "=X,r,X"))] "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64" "#" @@ -5632,7 +5641,8 @@ emit_insn (gen_floatdi2 (result, di)); DONE; -}) +} + [(set_attr "isa" "p9v,*,p9v")]) (define_expand "fix_truncsi2" [(set (match_operand:SI 0 "gpc_reg_operand") @@ -5745,8 +5755,8 @@ ;; register allocation prevents the register allocator from doing a direct move ;; of the SImode value to a GPR, and then a store/load. (define_insn_and_split "fix_trunc2" - [(set (match_operand: 0 "gpc_reg_operand" "=wJ,wJwK,r") - (any_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand" "wJ,wJwK,wa"))) + [(set (match_operand: 0 "gpc_reg_operand" "=wI,wIwH,r") + (any_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand" "wI,wIwH,wa"))) (clobber (match_scratch:SI 2 "=X,X,wi"))] "TARGET_DIRECT_MOVE" "@ @@ -5761,8 +5771,9 @@ { operands[3] = gen_rtx_REG (SImode, REGNO (operands[0])); } - [(set_attr "length" "4,4,8") - (set_attr "type" "fp")]) + [(set_attr "type" "fp") + (set_attr "length" "4,4,8") + (set_attr "isa" "p9v,p9v,*")]) (define_insn "*fix_truncsi2_p8" [(set (match_operand:SI 0 "gpc_reg_operand" "=d,wa") @@ -6871,17 +6882,15 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=r, r, r, wI, wH, m, Z, Z, r, r, - r, wIwH, wJwK, wJwK, wu, - wJwK, wH, wK, wIwH, r, + r, wIwH, wIwH, wIwH, wu, + wIwH, wH, wH, wIwH, r, r, *h, *h") - (match_operand:SI 1 "input_operand" "r, U, m, Z, Z, r, wI, wH, I, L, n, wIwH, O, wM, wB, O, wM, wS, r, wIwH, *h, r, 0"))] - "gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode)" "@ @@ -6914,13 +6923,18 @@ *, veclogical, vecsimple, vecsimple, vecsimple, veclogical, veclogical, vecsimple, mffgpr, mftgpr, *, *, *") - (set_attr "length" "4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 8, 4, 4, - 4, 4, 4")]) + 4, 4, 4") + (set_attr "isa" + "*, *, *, *, *, + *, *, *, *, *, + *, *, p9v, p9v, *, + p9v, *, p9v, *, *, + *, *, *")]) ;; Like movsi, but adjust a SF value to be used in a SI context, i.e. ;; (set (reg:SI ...) (subreg:SI (reg:SF ...) 0)) @@ -7006,18 +7020,15 @@ (define_insn_and_split "*movdi_from_sf_zero_ext" [(set (match_operand:DI 0 "gpc_reg_operand" "=r, r, ?*wI, ?*wH, r, - ?wK, wIwH") - + ?wH, wIwH") (zero_extend:DI (unspec:SI [(match_operand:SF 1 "input_operand" "r, m, Z, Z, wIwH, wIwH, r")] UNSPEC_SI_FROM_SF))) - (clobber (match_scratch:V4SF 2 "=X, X, X, X, wa, wIwH, X"))] - "TARGET_DIRECT_MOVE_64BIT && (register_operand (operands[0], DImode) || register_operand (operands[1], SImode))" @@ -7046,10 +7057,12 @@ [(set_attr "type" "*, load, fpload, fpload, two, two, mffgpr") - (set_attr "length" "4, 4, 4, 4, 8, - 8, 4")]) + 8, 4") + (set_attr "isa" + "*, *, *, *, *, + p9v, *")]) ;; Like movsi_from_sf, but combine a convert from DFmode to SFmode before ;; moving it to SImode. We cannot do a SFmode store without having to do the @@ -7143,15 +7156,13 @@ ;; MTVSRWZ MF%1 MT%1 NOP (define_insn "*mov_internal" [(set (match_operand:QHI 0 "nonimmediate_operand" - "=r, r, wJwK, m, Z, r, - wJwK, wJwK, wJwK, wK, ?wK, r, - wJwK, r, *c*l, *h") - + "=r, r, wIwH, m, Z, r, + wIwH, wIwH, wIwH, wH, ?wH, r, + wIwH, r, *c*l, *h") (match_operand:QHI 1 "input_operand" - "r, m, Z, r, wJwK, i, - wJwK, O, wM, wB, wS, wJwK, + "r, m, Z, r, wIwH, i, + wIwH, O, wM, wB, wS, wIwH, r, *h, r, 0"))] - "gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode)" "@ @@ -7175,11 +7186,14 @@ "*, load, fpload, store, fpstore, *, vecsimple, vecperm, vecperm, vecperm, vecperm, mftgpr, mffgpr, mfjmpr, mtjmpr, *") - (set_attr "length" "4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 8, 4, - 4, 4, 4, 4")]) + 4, 4, 4, 4") + (set_attr "isa" + "*, *, p9v, *, p9v, *, + p9v, p9v, p9v, p9v, p9v, p9v, + p9v, *, *, *")]) ;; Here is how to move condition codes around. When we store CC data in diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 0b2ddaae1105..7c89ad8ad3a0 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3525,7 +3525,7 @@ (define_insn "vsx_extract__p9" [(set (match_operand: 0 "gpc_reg_operand" "=r,") (vec_select: - (match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wK,") + (match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wH,") (parallel [(match_operand:QI 2 "" "n,n")]))) (clobber (match_scratch:SI 3 "=r,X"))] "VECTOR_MEM_VSX_P (mode) && TARGET_VEXTRACTUB" @@ -3550,7 +3550,8 @@ return "vextractu %0,%1,%2"; } } - [(set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple") + (set_attr "isa" "p9v,*")]) (define_split [(set (match_operand: 0 "int_reg_operand") @@ -3580,7 +3581,7 @@ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,") (zero_extend:DI (vec_select: - (match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wK,") + (match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wH,") (parallel [(match_operand:QI 2 "const_int_operand" "n,n")])))) (clobber (match_scratch:SI 3 "=r,X"))] "VECTOR_MEM_VSX_P (mode) && TARGET_VEXTRACTUB" @@ -3593,7 +3594,8 @@ (clobber (match_dup 3))])] { operands[4] = gen_rtx_REG (mode, REGNO (operands[0])); -}) +} + [(set_attr "isa" "p9v,*")]) ;; Optimize stores to use the ISA 3.0 scalar store instructions (define_insn_and_split "*vsx_extract__store_p9" @@ -3617,9 +3619,9 @@ (define_insn_and_split "*vsx_extract_si" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,wHwI,Z") (vec_select:SI - (match_operand:V4SI 1 "gpc_reg_operand" "wJv,wJv,wJv") + (match_operand:V4SI 1 "gpc_reg_operand" "v,v,v") (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))) - (clobber (match_scratch:V4SI 3 "=wJv,wJv,wJv"))] + (clobber (match_scratch:V4SI 3 "=v,v,v"))] "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT && !TARGET_P9_VECTOR" "#" "&& reload_completed" @@ -3733,7 +3735,7 @@ (define_insn_and_split "vsx_extract__var" [(set (match_operand: 0 "gpc_reg_operand" "=r,r,r") (unspec: - [(match_operand:VSX_EXTRACT_I 1 "input_operand" "wK,v,m") + [(match_operand:VSX_EXTRACT_I 1 "input_operand" "wH,v,m") (match_operand:DI 2 "gpc_reg_operand" "r,r,r")] UNSPEC_VSX_EXTRACT)) (clobber (match_scratch:DI 3 "=r,r,&b")) @@ -3746,13 +3748,14 @@ rs6000_split_vec_extract_var (operands[0], operands[1], operands[2], operands[3], operands[4]); DONE; -}) +} + [(set_attr "isa" "p9v,*,*")]) (define_insn_and_split "*vsx_extract__mode_var" [(set (match_operand: 0 "gpc_reg_operand" "=r,r,r") (zero_extend: (unspec: - [(match_operand:VSX_EXTRACT_I 1 "input_operand" "wK,v,m") + [(match_operand:VSX_EXTRACT_I 1 "input_operand" "wH,v,m") (match_operand:DI 2 "gpc_reg_operand" "r,r,r")] UNSPEC_VSX_EXTRACT))) (clobber (match_scratch:DI 3 "=r,r,&b")) @@ -3767,7 +3770,8 @@ operands[1], operands[2], operands[3], operands[4]); DONE; -}) +} + [(set_attr "isa" "p9v,*,*")]) ;; VSX_EXTRACT optimizations ;; Optimize double d = (double) vec_extract (vi, ) @@ -3951,7 +3955,7 @@ (match_operand:SF 2 "gpc_reg_operand" "ww") (match_operand:QI 3 "const_0_to_3_operand" "n")] UNSPEC_VSX_SET)) - (clobber (match_scratch:SI 4 "=&wJwK"))] + (clobber (match_scratch:SI 4 "=&wIwH"))] "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64" "#" "&& reload_completed" @@ -3976,7 +3980,8 @@ operands[8] = gen_rtx_REG (V4SImode, reg_or_subregno (operands[0])); } [(set_attr "type" "vecperm") - (set_attr "length" "12")]) + (set_attr "length" "12") + (set_attr "isa" "p9v")]) ;; Special case setting 0.0f to a V4SF element (define_insn_and_split "*vsx_set_v4sf_p9_zero" @@ -3986,7 +3991,7 @@ (match_operand:SF 2 "zero_fp_constant" "j") (match_operand:QI 3 "const_0_to_3_operand" "n")] UNSPEC_VSX_SET)) - (clobber (match_scratch:SI 4 "=&wJwK"))] + (clobber (match_scratch:SI 4 "=&wIwH"))] "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64" "#" "&& reload_completed" @@ -4001,7 +4006,8 @@ operands[5] = gen_rtx_REG (V4SImode, reg_or_subregno (operands[0])); } [(set_attr "type" "vecperm") - (set_attr "length" "8")]) + (set_attr "length" "8") + (set_attr "isa" "p9v")]) ;; Optimize x = vec_insert (vec_extract (v2, n), v1, m) if n is the element ;; that is in the default scalar position (1 for big endian, 2 for little @@ -4043,7 +4049,7 @@ [(match_operand:QI 3 "const_0_to_3_operand" "n")])) (match_operand:QI 4 "const_0_to_3_operand" "n")] UNSPEC_VSX_SET)) - (clobber (match_scratch:SI 5 "=&wJwK"))] + (clobber (match_scratch:SI 5 "=&wIwH"))] "VECTOR_MEM_VSX_P (V4SFmode) && VECTOR_MEM_VSX_P (V4SImode) && TARGET_P9_VECTOR && TARGET_POWERPC64 && (INTVAL (operands[3]) != (BYTES_BIG_ENDIAN ? 1 : 2))" @@ -4066,7 +4072,8 @@ operands[7] = gen_lowpart (V4SImode, operands[0]); operands[8] = gen_lowpart (V4SImode, operands[1]); } - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecperm") + (set_attr "isa" "p9v")]) ;; Expanders for builtins (define_expand "vsx_mergel_" diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 1debcabec3c3..b96d24eb1538 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3337,12 +3337,6 @@ Altivec register if @option{-mvsx-small-integer}. @item wI Floating point register if @option{-mvsx-small-integer}. -@item wJ -FP register if @option{-mvsx-small-integer} and @option{-mpower9-vector}. - -@item wK -Altivec register if @option{-mvsx-small-integer} and @option{-mpower9-vector}. - @item wL Int constant that is the element number that the MFVSRLD instruction. targets.