h8300.md (*extzv_1_r_h8300): Correct the insn length.

	* config/h8300/h8300.md (*extzv_1_r_h8300): Correct the insn
	length.
	(*extzv_1_r_h8300hs): Likewise.
	(*extzv_1_r_inv_h8300): Likewise.
	(*extzv_1_r_inv_h8300hs): Likewise.

From-SVN: r61115

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d0c1d65a74d06ee3f883e48586f084e5c527977a..f25bab9c1602992bb5b8dd52d2d505aa19b7825c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2003-01-09  Kazu Hirata  <kazu@cs.umass.edu>
+
+       * config/h8300/h8300.md (*extzv_1_r_h8300): Correct the insn
+       length.
+       (*extzv_1_r_h8300hs): Likewise.
+       (*extzv_1_r_inv_h8300): Likewise.
+       (*extzv_1_r_inv_h8300hs): Likewise.
+
 2003-01-09  Kazu Hirata  <kazu@cs.umass.edu>
 
        * config/h8300/h8300.h (PREDICATE_CODES): New.

diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 65ff9888e40c50ca8d6c7561c049c0b405b0c496..1d1fdacd625e3ff565ae5028e46d5fb0215aba97 100644 (file)
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -2403,7 +2403,7 @@
 ;; Normal loads with a 32bit destination.
 ;;
 
-(define_insn ""
+(define_insn "*extzv_1_r_h8300"
   [(set (match_operand:SI 0 "register_operand" "=&r")
        (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
                         (const_int 1)
@@ -2412,9 +2412,9 @@
    && INTVAL (operands[2]) < 16"
   "* return output_simode_bld (0, operands);"
   [(set_attr "cc" "clobber")
-   (set_attr "length" "6")])
+   (set_attr "length" "8")])
 
-(define_insn ""
+(define_insn "*extzv_1_r_h8300hs"
   [(set (match_operand:SI 0 "register_operand" "=r")
        (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
                         (const_int 1)
@@ -2423,13 +2423,13 @@
    && INTVAL (operands[2]) < 16"
   "* return output_simode_bld (0, operands);"
   [(set_attr "cc" "clobber")
-   (set_attr "length" "6")])
+   (set_attr "length" "8")])
 
 ;;
 ;; Inverted loads with a 32bit destination.
 ;;
 
-(define_insn ""
+(define_insn "*extzv_1_r_inv_h8300"
   [(set (match_operand:SI 0 "register_operand" "=&r")
        (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
                                 (match_operand:HI 3 "const_int_operand" "n"))
@@ -2440,9 +2440,9 @@
    && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
   "* return output_simode_bld (1, operands);"
   [(set_attr "cc" "clobber")
-   (set_attr "length" "6")])
+   (set_attr "length" "8")])
 
-(define_insn ""
+(define_insn "*extzv_1_r_inv_h8300hs"
   [(set (match_operand:SI 0 "register_operand" "=r")
        (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "r")
                                 (match_operand 3 "const_int_operand" "n"))
@@ -2453,7 +2453,7 @@
    && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
   "* return output_simode_bld (1, operands);"
   [(set_attr "cc" "clobber")
-   (set_attr "length" "6")])
+   (set_attr "length" "8")])
 
 (define_expand "insv"
   [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")