The expand pattern for reciprocal division was enabled for all math
optimization modes, but the patterns it was generating were not
enabled unless -funsafe-math-optimizations were enabled, this leads to
an ICE when the pattern we generate cannot be recognized.
Fixed by only enabling vector division when doing unsafe math.
gcc:
PR target/108120
* config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
Gate with ARM_HAVE_NEON_<MODE>_ARITH.
gcc/testsuite:
PR target/108120
* gcc.target/arm/neon-recip-div-1.c: New file.
(cherry picked from commit
016c4eed368b80a97101f6156ed99e4c5474fbb7)
Enabled with -funsafe-math-optimizations -freciprocal-math
and disabled for -Os since it increases code size . */
-(define_expand "div<mode>3"
+(define_expand "div<VCVTF:mode>3"
[(set (match_operand:VCVTF 0 "s_register_operand")
(div:VCVTF (match_operand:VCVTF 1 "s_register_operand")
(match_operand:VCVTF 2 "s_register_operand")))]
- "TARGET_NEON && !optimize_size
+ "ARM_HAVE_NEON_<MODE>_ARITH && !optimize_size
&& flag_reciprocal_math"
{
rtx rec = gen_reg_rtx (<MODE>mode);
--- /dev/null
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O3 -freciprocal-math -fno-unsafe-math-optimizations -save-temps" } */
+/* { dg-add-options arm_neon } */
+
+int *a;
+int n;
+void b() {
+ int c;
+ for (c = 0; c < 100000; c++)
+ a[c] = (float)c / n;
+}
+/* We should not ICE, or get a vectorized reciprocal instruction when unsafe
+ math optimizations are disabled. */
+/* { dg-final { scan-assembler-not "vrecpe\\.f32\\t\[qd\].*" } } */
+/* { dg-final { scan-assembler-not "vrecps\\.f32\\t\[qd\].*" } } */