constraints.md ("z" constraint): Change to CA_REGS.

2010-05-28  Segher Boessenkool  <segher@kernel.crashing.org>

        * config/rs6000/constraints.md ("z" constraint): Change to CA_REGS.
        * config/rs6000/predicates.md: Change XER_REGNO_P to CA_REGNO_P
        throughout.
        * config/rs6000/rs6000.c (rs6000_reg_names, alt_reg_names): Change
        "xer" to "ca".
        Change XER_REGNO_P to CA_REGNO_P, XER_REGNO to CA_REGNO, and
        XER_REGS to CA_REGS throughout.
        * config/rs6000/rs6000.h: Same.
        (ADDITIONAL_REGISTER_NAMES): Add "xer".
        * config/rs6000/rs6000.md: Change XER_REGNO to CA_REGNO.  Document
        that mode_iterator "P" is the size for arithmetic carries as well.
        * doc/md.texi (rs6000 section, "z" constraint): Fix documentation.

From-SVN: r159953

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0638a80e784a9b6ac38990f82dc3dd22dc923be4..5cc16f7beee1f72ea21c37a5e723b380c3ba6599 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2010-05-28  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       * config/rs6000/constraints.md ("z" constraint): Change to CA_REGS.
+       * config/rs6000/predicates.md: Change XER_REGNO_P to CA_REGNO_P
+       throughout.
+       * config/rs6000/rs6000.c (rs6000_reg_names, alt_reg_names): Change
+       "xer" to "ca".
+       Change XER_REGNO_P to CA_REGNO_P, XER_REGNO to CA_REGNO, and
+       XER_REGS to CA_REGS throughout.
+       * config/rs6000/rs6000.h: Same.
+       (ADDITIONAL_REGISTER_NAMES): Add "xer".
+       * config/rs6000/rs6000.md: Change XER_REGNO to CA_REGNO.  Document
+       that mode_iterator "P" is the size for arithmetic carries as well.
+       * doc/md.texi (rs6000 section, "z" constraint): Fix documentation.
+
 2010-05-28  Jakub Jelinek  <jakub@redhat.com>
 
        PR bootstrap/44255

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 7b99094d738561c79488ec7e4cb78b4d941f0cd7..bd4a1a1b8ae8d48aa59e92c233f2b43bebf57c57 100644 (file)
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -51,7 +51,7 @@
 (define_register_constraint "y" "CR_REGS"
   "@internal")
 
-(define_register_constraint "z" "XER_REGS"
+(define_register_constraint "z" "CA_REGS"
   "@internal")
 
 ;; Use w as a prefix to add VSX modes

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 2d8a2a8d5d1bc619d846d7c24f574d4964216abd..b4de82b6612c4b16a87d0b9664cfd0a81aff81b1 100644 (file)
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -69,10 +69,10 @@
                     || VLOGICAL_REGNO_P (REGNO (op))
                     || REGNO (op) > LAST_VIRTUAL_REGISTER")))
 
-;; Return 1 if op is XER register.
-(define_predicate "xer_operand"
+;; Return 1 if op is the carry register.
+(define_predicate "ca_operand"
   (and (match_code "reg")
-       (match_test "XER_REGNO_P (REGNO (op))")))
+       (match_test "CA_REGNO_P (REGNO (op))")))
 
 ;; Return 1 if op is a signed 5-bit constant integer.
 (define_predicate "s5bit_cint_operand"
@@ -116,7 +116,7 @@
    (and (match_operand 0 "register_operand")
        (match_test "(GET_CODE (op) != REG
                      || (REGNO (op) >= ARG_POINTER_REGNUM
-                         && !XER_REGNO_P (REGNO (op)))
+                         && !CA_REGNO_P (REGNO (op)))
                      || REGNO (op) < MQ_REGNO)
                     && !((TARGET_E500_DOUBLE || TARGET_SPE)
                          && invalid_e500_subreg (op, mode))")))

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index eb8af6fea845f41d247854bccfcd322c167a3592..b1cc4c784a52d21b61474fb9a2ade0da07df9d44 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1210,7 +1210,7 @@ char rs6000_reg_names[][8] =
      "24", "25", "26", "27", "28", "29", "30", "31",
      "mq", "lr", "ctr","ap",
       "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
-      "xer",
+      "ca",
       /* AltiVec registers.  */
       "0",  "1",  "2",  "3",  "4",  "5",  "6", "7",
       "8",  "9",  "10", "11", "12", "13", "14", "15",
@@ -1236,7 +1236,7 @@ static const char alt_reg_names[][8] =
   "%f24",  "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
     "mq",    "lr",  "ctr",   "ap",
   "%cr0",  "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
-   "xer",
+   "ca",
   /* AltiVec registers.  */
    "%v0",  "%v1",  "%v2",  "%v3",  "%v4",  "%v5",  "%v6", "%v7",
    "%v8",  "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
@@ -1649,8 +1649,8 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
   if (CR_REGNO_P (regno))
     return GET_MODE_CLASS (mode) == MODE_CC;
 
-  if (XER_REGNO_P (regno))
-    return mode == PSImode;
+  if (CA_REGNO_P (regno))
+    return mode == BImode;
 
   /* AltiVec only in AldyVec registers.  */
   if (ALTIVEC_REGNO_P (regno))
@@ -1771,7 +1771,7 @@ rs6000_debug_reg_global (void)
   rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
   rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
   rs6000_debug_reg_print (MQ_REGNO, MQ_REGNO, "mq");
-  rs6000_debug_reg_print (XER_REGNO, XER_REGNO, "xer");
+  rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
   rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
   rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
   rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a");
@@ -1896,7 +1896,7 @@ rs6000_init_hard_regno_mode_ok (void)
   rs6000_regno_regclass[MQ_REGNO] = MQ_REGS;
   rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
   rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
-  rs6000_regno_regclass[XER_REGNO] = XER_REGS;
+  rs6000_regno_regclass[CA_REGNO] = CA_REGS;
   rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
   rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
   rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;
@@ -25745,8 +25745,8 @@ rs6000_dbx_register_number (unsigned int regno)
     return 109;
   if (CR_REGNO_P (regno))
     return regno - CR0_REGNO + 86;
-  if (regno == XER_REGNO)
-    return 101;
+  if (regno == CA_REGNO)
+    return 101;  /* XER */
   if (ALTIVEC_REGNO_P (regno))
     return regno - FIRST_ALTIVEC_REGNO + 1124;
   if (regno == VRSAVE_REGNO)

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 6be51cc47d5377e63f5cdc041a798d5c0852752e..327673e160c5d812f4be59116a2e43f2f3a89db6 100644 (file)
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -946,7 +946,7 @@ extern unsigned rs6000_pointer_size;
        mq              (not saved; best to use it if we can)
        ctr             (not saved; when we have the choice ctr is better)
        lr              (saved)
-       cr5, r1, r2, ap, xer (fixed)
+       cr5, r1, r2, ap, ca (fixed)
        v0 - v1         (not saved or used for anything)
        v13 - v3        (not saved; incoming vector arg registers)
        v2              (not saved; incoming vector arg reg; return value)
@@ -1008,8 +1008,8 @@ extern unsigned rs6000_pointer_size;
 /* PAIRED SIMD registers are just the FPRs.  */
 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
 
-/* True if register is the XER register.  */
-#define XER_REGNO_P(N) ((N) == XER_REGNO)
+/* True if register is the CA register.  */
+#define CA_REGNO_P(N) ((N) == CA_REGNO)
 
 /* True if register is an AltiVec register.  */
 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
@@ -1229,7 +1229,7 @@ enum reg_class
   CR0_REGS,
   CR_REGS,
   NON_FLOAT_REGS,
-  XER_REGS,
+  CA_REGS,
   ALL_REGS,
   LIM_REG_CLASSES
 };
@@ -1260,7 +1260,7 @@ enum reg_class
   "CR0_REGS",                                                          \
   "CR_REGS",                                                           \
   "NON_FLOAT_REGS",                                                    \
-  "XER_REGS",                                                          \
+  "CA_REGS",                                                           \
   "ALL_REGS"                                                           \
 }
 
@@ -1290,7 +1290,7 @@ enum reg_class
   { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */        \
   { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */         \
   { 0xffffffff, 0x00000000, 0x0000efff, 0x00020000 }, /* NON_FLOAT_REGS */   \
-  { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */        \
+  { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */         \
   { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff }  /* ALL_REGS */        \
 }
 
@@ -1311,7 +1311,7 @@ enum reg_class
   GENERAL_REGS, SPECIAL_REGS, FLOAT_REGS, ALTIVEC_REGS, /* VSX_REGS, */             \
   /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS,                  \
   /* MQ_REGS, LINK_REGS, CTR_REGS, */                                       \
-  CR_REGS, XER_REGS, LIM_REG_CLASSES                                        \
+  CR_REGS, CA_REGS, LIM_REG_CLASSES                                         \
 }
 
 #define IRA_COVER_CLASSES_VSX                                               \
@@ -1319,7 +1319,7 @@ enum reg_class
   GENERAL_REGS, SPECIAL_REGS, /* FLOAT_REGS, ALTIVEC_REGS, */ VSX_REGS,             \
   /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS,                  \
   /* MQ_REGS, LINK_REGS, CTR_REGS, */                                       \
-  CR_REGS, XER_REGS, LIM_REG_CLASSES                                        \
+  CR_REGS, CA_REGS, LIM_REG_CLASSES                                         \
 }
 
 /* The same information, inverted:
@@ -2259,7 +2259,7 @@ extern char rs6000_reg_names[][8];        /* register names (0 vs. %r0).  */
   &rs6000_reg_names[74][0],    /* cr6  */                              \
   &rs6000_reg_names[75][0],    /* cr7  */                              \
                                                                        \
-  &rs6000_reg_names[76][0],    /* xer  */                              \
+  &rs6000_reg_names[76][0],    /* ca  */                               \
                                                                        \
   &rs6000_reg_names[77][0],    /* v0  */                               \
   &rs6000_reg_names[78][0],    /* v1  */                               \
@@ -2333,6 +2333,8 @@ extern char rs6000_reg_names[][8];        /* register names (0 vs. %r0).  */
   {"cr0",  68}, {"cr1",  69}, {"cr2",  70}, {"cr3",  71},      \
   {"cr4",  72}, {"cr5",  73}, {"cr6",  74}, {"cr7",  75},      \
   {"cc",   68}, {"sp",    1}, {"toc",   2},                    \
+  /* CA is only part of XER, but we do not model the other parts (yet).  */ \
+  {"xer",  76},                                                        \
   /* VSX registers overlaid on top of FR, Altivec registers */ \
   {"vs0",  32}, {"vs1",  33}, {"vs2",  34}, {"vs3",  35},      \
   {"vs4",  36}, {"vs5",  37}, {"vs6",  38}, {"vs7",  39},      \

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 34d619c38e74094ac93364c300fb6d1ea3330054..bcb66ec1479c74f175c9b0f13c3acc0e390941d8 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -39,7 +39,7 @@
    (CR6_REGNO                  74)
    (CR7_REGNO                  75)
    (MAX_CR_REGNO               75)
-   (XER_REGNO                  76)
+   (CA_REGNO                   76)
    (FIRST_ALTIVEC_REGNO                77)
    (LAST_ALTIVEC_REGNO         108)
    (VRSAVE_REGNO               109)
@@ -201,7 +201,7 @@
 (define_mode_iterator SDI [SI DI])
 
 ; The size of a pointer.  Also, the size of the value that a record-condition
-; (one with a '.') will compare.
+; (one with a '.') will compare; and the size used for arithmetic carries.
 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
 
 ; Any hardware-supported floating-point mode

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index ead8b26545808ff049b74f105071874945cc754c..fb3a4c1bc73fb51488b3eaa42e952fa6c549ad7a 100644 (file)
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -1949,7 +1949,7 @@ Any VSX register
 @samp{CR} register (condition register)
 
 @item z
-@samp{FPMEM} stack memory for FPR-GPR transfers
+@samp{XER[CA]} carry bit (part of the XER register)
 
 @item I
 Signed 16-bit constant