#ifndef HALF_PIC_P
#define HALF_PIC_P() 0
#define HALF_PIC_ENCODE(DECL)
+#define HALF_PIC_DECLARE(NAME)
#define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
#define HALF_PIC_ADDRESS_P(X) 0
#define HALF_PIC_PTR(X) X
in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
- mips_declare_object (STREAM, NAME, "", ":\n", 0);
+do \
+ { \
+ mips_declare_object (STREAM, NAME, "", ":\n", 0); \
+ HALF_PIC_DECLARE (NAME); \
+ } \
+while (0)
/* This is how to output a command to make the user-level label named NAME
STREAM = asm_out_text_file; \
\
current_function_name = NAME; \
+ HALF_PIC_DECLARE (NAME); \
}
/* This is how to output a reference to a user-level label named NAME.
}
\f
-/* Output before read-only data. */
-
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* Output before writable data. */
-
-#define DATA_SECTION_ASM_OP ".data"
-
-/* Output before writable short data. */
-
-#define SDATA_SECTION_ASM_OP ".sdata"
-
-/* Output before read-only data. */
-
-#define RDATA_SECTION_ASM_OP ".rdata"
-#define READONLY_DATA_SECTION rdata_section
+/* Define the strings to put out for each section in the object file. */
+#define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
+#define DATA_SECTION_ASM_OP "\t.data" /* large data */
+#define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
+#define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
+#define READONLY_DATA_SECTION rdata_section
/* What other sections we support other than the normal .data/.text. */
;; whether or not an instruction has a mandatory delay slot
(define_attr "dslot" "no,yes"
- (if_then_else (eq_attr "type" "branch,jump,call,load,xfer,hilo,fcmp")
+ (if_then_else (eq_attr "type" "branch,jump,call,load,xfer,hilo,fcmp,pic")
(const_string "yes")
(const_string "no")))
;; different predicates, because register spilling and other parts of
;; the compiler, have memoized the insn number already.
-(define_insn "movsi"
+(define_expand "movsi"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "")
+ (match_operand:SI 1 "general_operand" ""))]
+ ""
+ "
+{
+ /* If this is a half-pic address being moved to a register, convert the
+ address into a load, so that scheduling and stuff works properly. */
+
+ if (HALF_PIC_P()
+ && GET_CODE (operands[0]) == REG
+ && GET_CODE (operands[1]) == SYMBOL_REF
+ && HALF_PIC_ADDRESS_P (operands[1]))
+ {
+ rtx ptr = HALF_PIC_PTR (operands[1]);
+ if (XSTR (ptr, 0) != XSTR (operands[1], 0))
+ {
+ emit_move_insn (operands[0], gen_rtx (MEM, Pmode, ptr));
+ DONE;
+ }
+ }
+}")
+
+(define_insn "movsi_internal"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*fs,*f,*f,*f,*R,*m,*x,*d")
(match_operand:SI 1 "general_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*fs,*d,*f,*R,*m,*f,*f,*d,*x"))]
""
;; Insn generated by block moves
(define_insn "movstrsi_internal"
- [(set (match_operand:BLK 0 "memory_operand" "Ro")
+ [(set (match_operand:BLK 0 "memory_operand" "=Ro")
(match_operand:BLK 1 "memory_operand" "Ro"))
- (clobber (match_scratch:SI 4 "d"))
- (clobber (match_scratch:SI 5 "d"))
- (clobber (match_scratch:SI 6 "d"))
- (clobber (match_scratch:SI 7 "d"))
+ (clobber (match_scratch:SI 4 "=d"))
+ (clobber (match_scratch:SI 5 "=d"))
+ (clobber (match_scratch:SI 6 "=d"))
+ (clobber (match_scratch:SI 7 "=d"))
(use (match_operand:SI 2 "small_int" "I"))
(use (match_operand:SI 3 "small_int" "I"))]
""