gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode),
const0_rtx));
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine vfsqrt.v and cond_mask
(define_insn_and_split "*cond_<optab><mode>"
riscv_vector::emit_vlmax_insn (code_for_pred_ncopysign (<MODE>mode),
riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine sign_extend/zero_extend(vf2) and vcond_mask
(define_insn_and_split "*cond_<optab><v_double_trunc><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine sign_extend/zero_extend(vf4) and vcond_mask
(define_insn_and_split "*cond_<optab><v_quad_trunc><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine sign_extend/zero_extend(vf8) and vcond_mask
(define_insn_and_split "*cond_<optab><v_oct_trunc><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine trunc(vf2) + vcond_mask
(define_insn_and_split "*cond_trunc<mode><v_double_trunc>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine FP extend(vf2) and vcond_mask
(define_insn_and_split "*cond_extend<v_double_trunc><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine FP trunc(vf2) + vcond_mask
(define_insn_and_split "*cond_trunc<mode><v_double_trunc>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine convert(FP->INT) + vcond_mask
(define_insn_and_split "*cond_<optab><mode><vconvert>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine convert(INT->FP) + vcond_mask
(define_insn_and_split "*cond_<float_cvt><vconvert><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine convert(FP->2xINT) + vcond_mask
(define_insn_and_split "*cond_<optab><vnconvert><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine convert(INT->2xFP) + vcond_mask
(define_insn_and_split "*cond_<float_cvt><vnconvert><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine convert(2xFP->INT) + vcond_mask
(define_insn_and_split "*cond_<optab><mode><vnconvert>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine convert(2xINT->FP) + vcond_mask
(define_insn_and_split "*cond_<float_cvt><mode><vnconvert>2"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; =============================================================================
;; Combine extend + binop to widen_binop
<MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vector")])
(define_insn_and_split "*single_widen_sub<any_extend:su><mode>"
[(set (match_operand:VWEXTI 0 "register_operand")
<MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "viwalu")])
(define_insn_and_split "*single_widen_add<any_extend:su><mode>"
[(set (match_operand:VWEXTI 0 "register_operand")
<MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "viwalu")])
;; This combine pattern does not correspond to an single instruction,
;; i.e. there is no vwmul.wv instruction. This is a temporary pattern
insn_code icode = code_for_pred (MULT, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, ops);
DONE;
-})
+}
+[(set_attr "type" "viwmul")])
(define_insn_and_split "*dual_widen_mulsu<mode>"
[(set (match_operand:VWEXTI 0 "register_operand")
insn_code icode = code_for_pred_widen_mulsu (<MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vector")])
(define_insn_and_split "*dual_widen_mulus<mode>"
[(set (match_operand:VWEXTI 0 "register_operand")
insn_code icode = code_for_pred_widen_mulsu (<MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vector")])
(define_insn_and_split "*dual_widen_<optab><mode>"
[(set (match_operand:VWEXTF 0 "register_operand")
insn_code icode = code_for_pred_dual_widen (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP_FRM_DYN, operands);
DONE;
-})
+}
+[(set_attr "type" "vector")])
(define_insn_and_split "*single_widen_add<mode>"
[(set (match_operand:VWEXTF 0 "register_operand")
insn_code icode = code_for_pred_single_widen_add (<MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP_FRM_DYN, operands);
DONE;
-})
+}
+[(set_attr "type" "vfwalu")])
(define_insn_and_split "*single_widen_sub<mode>"
[(set (match_operand:VWEXTF 0 "register_operand")
insn_code icode = code_for_pred_single_widen_sub (<MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP_FRM_DYN, operands);
DONE;
-})
+}
+[(set_attr "type" "vfwalu")])
;; This combine pattern does not correspond to an single instruction,
;; i.e. there is no vfwmul.wv instruction. This is a temporary pattern
riscv_vector::emit_vlmax_insn (code_for_pred (MULT, <MODE>mode),
riscv_vector::BINARY_OP_FRM_DYN, ops);
DONE;
-})
+}
+[(set_attr "type" "vfwmul")])
riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vialu")])
;; -------------------------------------------------------------------------
;; ---- [INT] Binary shifts by scalar.
riscv_vector::MERGE_OP, operands);
DONE;
}
+ [(set_attr "type" "vector")]
)
;; -------------------------------------------------------------------------
insn_code icode = code_for_pred_vf4 (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vext")])
(define_insn_and_split "<optab><v_oct_trunc><mode>2"
[(set (match_operand:VOEXTI 0 "register_operand")
insn_code icode = code_for_pred_vf8 (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vext")])
;; -------------------------------------------------------------------------
;; ---- [INT] Truncation
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vfcvtftoi")])
;; -------------------------------------------------------------------------
;; ---- [FP<-INT] Conversions
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, operands);
DONE;
-})
+}
+[(set_attr "type" "vfcvtitof")])
;; =========================================================================
;; == Widening/narrowing Conversions
insn_code icode = code_for_pred_widen (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vfwcvtftoi")])
;; -------------------------------------------------------------------------
;; ---- [FP<-INT] Widening Conversions
insn_code icode = code_for_pred_widen (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vfwcvtitof")])
;; -------------------------------------------------------------------------
;; ---- [INT<-FP] Narrowing Conversions
insn_code icode = code_for_pred_narrow (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vfncvtftoi")])
;; -------------------------------------------------------------------------
;; ---- [FP<-INT] Narrowing Conversions
insn_code icode = code_for_pred_narrow (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, operands);
DONE;
-})
+}
+[(set_attr "type" "vfncvtitof")])
;; =========================================================================
;; == Unary arithmetic
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vialu")])
;; -------------------------------------------------------------------------------
;; - [INT] ABS expansion to vmslt and vneg.
riscv_vector::emit_vlmax_insn (code_for_pred (NEG, <MODE>mode),
riscv_vector::UNARY_OP_TAMU, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; -------------------------------------------------------------------------------
;; ---- [FP] Unary operations
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; -------------------------------------------------------------------------------
;; - [FP] Square root
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, operands);
DONE;
-})
+}
+[(set_attr "type" "vfsqrt")])
;; =========================================================================
;; == Ternary arithmetic
riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
riscv_vector::BINARY_OP_FRM_DYN, operands);
DONE;
-})
+}
+[(set_attr "type" "vfalu")])
;; -------------------------------------------------------------------------
;; Includes:
riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vfminmax")])
;; -------------------------------------------------------------------------------
;; ---- [FP] Sign copying
insn_code icode = code_for_pred_mulh (UNSPEC_VMULHS, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vimul")])
(define_insn_and_split "umul<mode>3_highpart"
[(set (match_operand:VFULLI 0 "register_operand")
insn_code icode = code_for_pred_mulh (UNSPEC_VMULHU, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vimul")])
;; -------------------------------------------------------------------------
;; ---- [INT] Conditional unary operations
git://gcc.gnu.org / gcc.git / commitdiff