static int arm_gen_constant PARAMS ((enum rtx_code, Mmode, Hint, rtx, rtx, int, int));
static unsigned bit_count PARAMS ((Ulong));
static int arm_address_register_rtx_p PARAMS ((rtx, int));
-static int arm_legitimate_index_p PARAMS ((enum machine_mode,
- rtx, int));
-static int thumb_base_register_rtx_p PARAMS ((rtx,
- enum machine_mode,
- int));
+static int arm_legitimate_index_p PARAMS ((Mmode, rtx, int));
+static int thumb_base_register_rtx_p PARAMS ((rtx, Mmode, int));
inline static int thumb_index_register_rtx_p PARAMS ((rtx, int));
static int const_ok_for_op PARAMS ((Hint, enum rtx_code));
static int eliminate_lr2ip PARAMS ((rtx *));
static Mfix * create_fix_barrier PARAMS ((Mfix *, Hint));
static void push_minipool_barrier PARAMS ((rtx, Hint));
static void push_minipool_fix PARAMS ((rtx, Hint, rtx *, Mmode, rtx));
-static void note_invalid_constants PARAMS ((rtx, Hint));
+static bool note_invalid_constants PARAMS ((rtx, Hint, bool));
static int current_file_function_operand PARAMS ((rtx));
static Ulong arm_compute_save_reg0_reg12_mask PARAMS ((void));
static Ulong arm_compute_save_reg_mask PARAMS ((void));
static void arm_output_function_prologue PARAMS ((FILE *, Hint));
static void thumb_output_function_prologue PARAMS ((FILE *, Hint));
static int arm_comp_type_attributes PARAMS ((tree, tree));
-static void arm_set_default_type_attributes PARAMS ((tree));
+static void arm_set_default_type_attributes PARAMS ((tree));
static int arm_adjust_cost PARAMS ((rtx, rtx, rtx, int));
-static int count_insns_for_constant PARAMS ((HOST_WIDE_INT, int));
+static int count_insns_for_constant PARAMS ((Hint, int));
static int arm_get_strip_length PARAMS ((int));
static bool arm_function_ok_for_sibcall PARAMS ((tree, tree));
+static void arm_internal_label PARAMS ((FILE *, Ccstar, Ulong));
+static void arm_output_mi_thunk PARAMS ((FILE *, tree, Hint, Hint, tree));
+static int arm_rtx_costs_1 PARAMS ((rtx, enum rtx_code, enum rtx_code));
+static bool arm_rtx_costs PARAMS ((rtx, int, int, int *));
+static int arm_address_cost PARAMS ((rtx));
+static bool arm_memory_load_p PARAMS ((rtx));
+static bool arm_cirrus_insn_p PARAMS ((rtx));
+static void cirrus_reorg PARAMS ((rtx));
#ifdef OBJECT_FORMAT_ELF
-static void arm_elf_asm_named_section PARAMS ((const char *, unsigned int));
+static void arm_elf_asm_named_section PARAMS ((Ccstar, unsigned int));
#endif
#ifndef ARM_PE
static void arm_encode_section_info PARAMS ((tree, int));
#endif
#ifdef AOF_ASSEMBLER
-static void aof_globalize_label PARAMS ((FILE *, const char *));
+static void aof_globalize_label PARAMS ((FILE *, Ccstar));
#endif
-static void arm_internal_label PARAMS ((FILE *, const char *, unsigned long));
-static void arm_output_mi_thunk PARAMS ((FILE *, tree,
- HOST_WIDE_INT,
- HOST_WIDE_INT, tree));
-static int arm_rtx_costs_1 PARAMS ((rtx, enum rtx_code,
- enum rtx_code));
-static bool arm_rtx_costs PARAMS ((rtx, int, int, int*));
-static int arm_address_cost PARAMS ((rtx));
-static int is_load_address PARAMS ((rtx));
-static int is_cirrus_insn PARAMS ((rtx));
-static void cirrus_reorg PARAMS ((rtx));
#undef Hint
#undef Mmode
&& INTVAL (op) < 64);
}
-/* Return nonzero if INSN is an LDR R0,ADDR instruction. */
+/* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
+ Use by the Cirrus Maverick code which has to workaround
+ a hardware bug triggered by such instructions. */
-static int
-is_load_address (insn)
+static bool
+arm_memory_load_p (insn)
rtx insn;
{
rtx body, lhs, rhs;;
- if (!insn)
- return 0;
-
- if (GET_CODE (insn) != INSN)
- return 0;
+ if (insn == NULL_RTX || GET_CODE (insn) != INSN)
+ return false;
body = PATTERN (insn);
if (GET_CODE (body) != SET)
- return 0;
+ return false;
lhs = XEXP (body, 0);
rhs = XEXP (body, 1);
- return (GET_CODE (lhs) == REG
- && REGNO_REG_CLASS (REGNO (lhs)) == GENERAL_REGS
- && (GET_CODE (rhs) == MEM
- || GET_CODE (rhs) == SYMBOL_REF));
+ lhs = REG_OR_SUBREG_RTX (lhs);
+
+ /* If the destination is not a general purpose
+ register we do not have to worry. */
+ if (GET_CODE (lhs) != REG
+ || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
+ return false;
+
+ /* As well as loads from memory we also have to react
+ to loads of invalid constants which will be turned
+ into loads from the minipool. */
+ return (GET_CODE (rhs) == MEM
+ || GET_CODE (rhs) == SYMBOL_REF
+ || note_invalid_constants (insn, -1, false));
}
-/* Return nonzero if INSN is a Cirrus instruction. */
+/* Return TRUE if INSN is a Cirrus instruction. */
-static int
-is_cirrus_insn (insn)
+static bool
+arm_cirrus_insn_p (insn)
rtx insn;
{
enum attr_cirrus attr;
attr = get_attr_cirrus (insn);
- return attr != CIRRUS_NO;
+ return attr != CIRRUS_NOT;
}
/* Cirrus reorg for invalid instruction combinations. */
nops = 0;
t = next_nonnote_insn (first);
- if (is_cirrus_insn (t))
+ if (arm_cirrus_insn_p (t))
++ nops;
- if (is_cirrus_insn (next_nonnote_insn (t)))
+ if (arm_cirrus_insn_p (next_nonnote_insn (t)))
++ nops;
while (nops --)
be followed by a non Cirrus insn. */
if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
{
- if (is_cirrus_insn (next_nonnote_insn (first)))
+ if (arm_cirrus_insn_p (next_nonnote_insn (first)))
emit_insn_after (gen_nop (), first);
return;
}
- else if (is_load_address (first))
+ else if (arm_memory_load_p (first))
{
unsigned int arm_regno;
/* Next insn. */
first = next_nonnote_insn (first);
- if (!is_cirrus_insn (first))
+ if (! arm_cirrus_insn_p (first))
return;
body = PATTERN (first);
t = next_nonnote_insn (first);
- if (is_cirrus_insn (t))
+ if (arm_cirrus_insn_p (t))
++ nops;
- if (is_cirrus_insn (next_nonnote_insn (t)))
+ if (arm_cirrus_insn_p (next_nonnote_insn (t)))
++ nops;
while (nops --)
minipool_fix_tail = fix;
}
-/* Scan INSN and note any of its operands that need fixing. */
+/* Scan INSN and note any of its operands that need fixing.
+ If DO_PUSHES is false we do not actually push any of the fixups
+ needed. The function returns TRUE is any fixups were needed/pushed.
+ This is used by arm_memory_load_p() which needs to know about loads
+ of constants that will be converted into minipool loads. */
-static void
-note_invalid_constants (insn, address)
+static bool
+note_invalid_constants (insn, address, do_pushes)
rtx insn;
HOST_WIDE_INT address;
+ bool do_pushes;
{
+ bool result = false;
int opno;
extract_insn (insn);
if (!constrain_operands (1))
fatal_insn_not_found (insn);
- /* Fill in recog_op_alt with information about the constraints of this
- insn. */
+ /* Fill in recog_op_alt with information about the constraints of this insn. */
preprocess_constraints ();
for (opno = 0; opno < recog_data.n_operands; opno++)
rtx op = recog_data.operand[opno];
if (CONSTANT_P (op))
- push_minipool_fix (insn, address, recog_data.operand_loc[opno],
- recog_data.operand_mode[opno], op);
-#if 0
- /* RWE: Now we look correctly at the operands for the insn,
- this shouldn't be needed any more. */
-#ifndef AOF_ASSEMBLER
- /* XXX Is this still needed? */
- else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_PIC_SYM)
- push_minipool_fix (insn, address, recog_data.operand_loc[opno],
- recog_data.operand_mode[opno],
- XVECEXP (op, 0, 0));
-#endif
-#endif
+ {
+ if (do_pushes)
+ push_minipool_fix (insn, address, recog_data.operand_loc[opno],
+ recog_data.operand_mode[opno], op);
+ result = true;
+ }
else if (GET_CODE (op) == MEM
&& GET_CODE (XEXP (op, 0)) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
- push_minipool_fix (insn, address, recog_data.operand_loc[opno],
- recog_data.operand_mode[opno],
- get_pool_constant (XEXP (op, 0)));
+ {
+ if (do_pushes)
+ push_minipool_fix (insn, address, recog_data.operand_loc[opno],
+ recog_data.operand_mode[opno],
+ get_pool_constant (XEXP (op, 0)));
+
+ result = true;
+ }
}
}
+
+ return result;
}
void
for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn))
{
if (TARGET_CIRRUS_FIX_INVALID_INSNS
- && (is_cirrus_insn (insn)
+ && (arm_cirrus_insn_p (insn)
|| GET_CODE (insn) == JUMP_INSN
- || is_load_address (insn)))
+ || arm_memory_load_p (insn)))
cirrus_reorg (insn);
if (GET_CODE (insn) == BARRIER)
push_minipool_barrier (insn, address);
- else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
- || GET_CODE (insn) == JUMP_INSN)
+ else if (INSN_P (insn))
{
rtx table;
- note_invalid_constants (insn, address);
+ note_invalid_constants (insn, address, true);
address += get_attr_length (insn);
/* If the insn is a vector jump, add the size of the table
instructions to be safe. */
if (GET_CODE (scanbody) != USE
&& GET_CODE (scanbody) != CLOBBER
- && get_attr_cirrus (this_insn) != CIRRUS_NO)
+ && get_attr_cirrus (this_insn) != CIRRUS_NOT)
fail = TRUE;
break;
;; Boston, MA 02111-1307, USA.
-(define_attr "cirrus_fpu" "fpa,fpe2,fpe3,yes" (const (symbol_ref "arm_fpu_attr")))
-
-; Classification of each insn
-; farith Floating point arithmetic (4 cycle)
-; dmult Double multiplies (7 cycle)
-(define_attr "cirrus_type" "normal,farith,dmult" (const_string "normal"))
-
; Cirrus types for invalid insn combinations
-; no Not a cirrus insn
-; yes Cirrus insn
+; not Not a cirrus insn
+; normal Any Cirrus insn not covered by the special cases below
; double cfldrd, cfldr64, cfstrd, cfstr64
; compare cfcmps, cfcmpd, cfcmp32, cfcmp64
; move cfmvdlr, cfmvdhr, cfmvsr, cfmv64lr, cfmv64hr
-(define_attr "cirrus" "no,yes,double,compare,move" (const_string "no"))
-\f
-(define_function_unit "cirrus_fpa" 1 0
- (and (eq_attr "cirrus_fpu" "yes")
- (eq_attr "cirrus_type" "farith")) 4 1)
-
-(define_function_unit "cirrus_fpa" 1 0
- (and (eq_attr "cirrus_fpu" "yes")
- (eq_attr "cirrus_type" "dmult")) 7 4)
+(define_attr "cirrus" "not,normal,double,compare,move" (const_string "not"))
-(define_function_unit "cirrus_fpa" 1 0
- (and (eq_attr "cirrus_fpu" "yes")
- (eq_attr "cirrus_type" "normal")) 1 1)
\f
(define_insn "cirrus_adddi3"
[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
(match_operand:DI 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfadd64%?\\t%V0, %V1, %V2"
- [(set_attr "cirrus_type" "farith")
- (set_attr "cirrus" "yes")]
+ [(set_attr "type" "mav_farith")
+ (set_attr "cirrus" "normal")]
)
(define_insn "*cirrus_addsi3"
(match_operand:SI 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfadd32%?\\t%V0, %V1, %V2"
- [(set_attr "cirrus_type" "farith")
- (set_attr "cirrus" "yes")]
+ [(set_attr "type" "mav_farith")
+ (set_attr "cirrus" "normal")]
)
;; define_insn replaced by define_expand and define_insn
(match_operand:SF 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfadds%?\\t%V0, %V1, %V2"
- [(set_attr "cirrus_type" "farith")
- (set_attr "cirrus" "yes")]
+ [(set_attr "type" "mav_farith")
+ (set_attr "cirrus" "normal")]
)
;; define_insn replaced by define_expand and define_insn
(match_operand:DF 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfaddd%?\\t%V0, %V1, %V2"
- [(set_attr "cirrus_type" "farith")
- (set_attr "cirrus" "yes")]
+ [(set_attr "type" "mav_farith")
+ (set_attr "cirrus" "normal")]
)
(define_insn "cirrus_subdi3"
(match_operand:DI 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfsub64%?\\t%V0, %V1, %V2"
- [(set_attr "cirrus_type" "farith")
- (set_attr "cirrus" "yes")]
+ [(set_attr "type" "mav_farith")
+ (set_attr "cirrus" "normal")]
)
(define_insn "*cirrus_subsi3_insn"
(match_operand:SI 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfsub32%?\\t%V0, %V1, %V2"
- [(set_attr "cirrus_type" "farith")
- (set_attr "cirrus" "yes")]
+ [(set_attr "type" "mav_farith")
+ (set_attr "cirrus" "normal")]
)
(define_expand "subsf3"
(match_operand:SF 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfsubs%?\\t%V0, %V1, %V2"
- [(set_attr "cirrus_type" "farith")
- (set_attr "cirrus" "yes")]
+ [(set_attr "type" "mav_farith")
+ (set_attr "cirrus" "normal")]
)
(define_expand "subdf3"
(match_operand:DF 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfsubd%?\\t%V0, %V1, %V2"
- [(set_attr "cirrus_type" "farith")
- (set_attr "cirrus" "yes")]
+ [(set_attr "type" "mav_farith")
+ (set_attr "cirrus" "normal")]
)
(define_insn "*cirrus_mulsi3"
(match_operand:SI 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfmul32%?\\t%V0, %V1, %V2"
- [(set_attr "cirrus_type" "farith")
- (set_attr "cirrus" "yes")]
+ [(set_attr "type" "mav_farith")
+ (set_attr "cirrus" "normal")]
)
(define_insn "muldi3"
(match_operand:DI 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfmul64%?\\t%V0, %V1, %V2"
- [(set_attr "cirrus_type" "dmult")
- (set_attr "cirrus" "yes")]
+ [(set_attr "type" "mav_dmult")
+ (set_attr "cirrus" "normal")]
)
(define_insn "*cirrus_mulsi3addsi"
(match_operand:SI 3 "cirrus_fp_register" "0")))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfmac32%?\\t%V0, %V1, %V2"
- [(set_attr "cirrus_type" "farith")
- (set_attr "cirrus" "yes")]
+ [(set_attr "type" "mav_farith")
+ (set_attr "cirrus" "normal")]
)
;; Cirrus SI multiply-subtract
(match_operand:SI 3 "cirrus_fp_register" "v"))))]
"0 && TARGET_ARM && TARGET_CIRRUS"
"cfmsc32%?\\t%V0, %V2, %V3"
- [(set_attr "cirrus_type" "farith")
- (set_attr "cirrus" "yes")]
+ [(set_attr "type" "mav_farith")
+ (set_attr "cirrus" "normal")]
)
(define_expand "mulsf3"
(match_operand:SF 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfmuls%?\\t%V0, %V1, %V2"
- [(set_attr "cirrus_type" "farith")
- (set_attr "cirrus" "yes")]
+ [(set_attr "type" "mav_farith")
+ (set_attr "cirrus" "normal")]
)
(define_expand "muldf3"
(match_operand:DF 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfmuld%?\\t%V0, %V1, %V2"
- [(set_attr "cirrus_type" "dmult")
- (set_attr "cirrus" "yes")]
+ [(set_attr "type" "mav_dmult")
+ (set_attr "cirrus" "normal")]
)
(define_insn "cirrus_ashl_const"
(match_operand:SI 2 "cirrus_shift_const" "")))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfsh32%?\\t%V0, %V1, #%s2"
- [(set_attr "cirrus" "yes")]
+ [(set_attr "cirrus" "normal")]
)
(define_insn "cirrus_ashiftrt_const"
(match_operand:SI 2 "cirrus_shift_const" "")))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfsh32%?\\t%V0, %V1, #-%s2"
- [(set_attr "cirrus" "yes")]
+ [(set_attr "cirrus" "normal")]
)
(define_insn "cirrus_ashlsi3"
(match_operand:SI 2 "register_operand" "r")))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfrshl32%?\\t%V1, %V0, %s2"
- [(set_attr "cirrus" "yes")]
+ [(set_attr "cirrus" "normal")]
)
(define_insn "ashldi3_cirrus"
(match_operand:SI 2 "register_operand" "r")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfrshl64%?\\t%V1, %V0, %s2"
- [(set_attr "cirrus" "yes")]
+ [(set_attr "cirrus" "normal")]
)
(define_insn "cirrus_ashldi_const"
(match_operand:SI 2 "cirrus_shift_const" "")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfsh64%?\\t%V0, %V1, #%s2"
- [(set_attr "cirrus" "yes")]
+ [(set_attr "cirrus" "normal")]
)
(define_insn "cirrus_ashiftrtdi_const"
(match_operand:SI 2 "cirrus_shift_const" "")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfsh64%?\\t%V0, %V1, #-%s2"
- [(set_attr "cirrus" "yes")]
+ [(set_attr "cirrus" "normal")]
)
(define_insn "*cirrus_absdi2"
(abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfabs64%?\\t%V0, %V1"
- [(set_attr "cirrus" "yes")]
+ [(set_attr "cirrus" "normal")]
)
;; This doesn't really clobber ``cc''. Fixme: aldyh.
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM && TARGET_CIRRUS"
"cfneg64%?\\t%V0, %V1"
- [(set_attr "cirrus" "yes")]
+ [(set_attr "cirrus" "normal")]
)
(define_insn "*cirrus_negsi2"
(neg:SI (match_operand:SI 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfneg32%?\\t%V0, %V1"
- [(set_attr "cirrus" "yes")]
+ [(set_attr "cirrus" "normal")]
)
(define_expand "negsf2"
(neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfnegs%?\\t%V0, %V1"
- [(set_attr "cirrus" "yes")]
+ [(set_attr "cirrus" "normal")]
)
(define_expand "negdf2"
(neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfnegd%?\\t%V0, %V1"
- [(set_attr "cirrus" "yes")]
+ [(set_attr "cirrus" "normal")]
)
(define_expand "abssi2"
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfabs32%?\\t%V0, %V1"
- [(set_attr "cirrus" "yes")]
+ [(set_attr "cirrus" "normal")]
)
(define_expand "abssf2"
(abs:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfabss%?\\t%V0, %V1"
- [(set_attr "cirrus" "yes")]
+ [(set_attr "cirrus" "normal")]
)
(define_expand "absdf2"
(abs:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfabsd%?\\t%V0, %V1"
- [(set_attr "cirrus" "yes")]
+ [(set_attr "cirrus" "normal")]
)
(define_expand "floatsisf2"
(float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfcvt64s%?\\t%V0, %V1"
- [(set_attr "cirrus" "yes")])
+ [(set_attr "cirrus" "normal")])
(define_insn "floatdidf2"
[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
(float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfcvt64d%?\\t%V0, %V1"
- [(set_attr "cirrus" "yes")])
+ [(set_attr "cirrus" "normal")])
(define_expand "fix_truncsfsi2"
[(set (match_operand:SI 0 "s_register_operand" "")
"TARGET_ARM && TARGET_CIRRUS"
"cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
[(set_attr "length" "8")
- (set_attr "cirrus" "yes")]
+ (set_attr "cirrus" "normal")]
)
(define_expand "fix_truncdfsi2"
(match_operand:DF 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfcvtds%?\\t%V0, %V1"
- [(set_attr "cirrus" "yes")]
+ [(set_attr "cirrus" "normal")]
)
(define_insn "*cirrus_extendsfdf2"
(float_extend:DF (match_operand:SF 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfcvtsd%?\\t%V0, %V1"
- [(set_attr "cirrus" "yes")]
+ [(set_attr "cirrus" "normal")]
)
(define_insn "*cirrus_arm_movdi"
default: abort ();
}
}"
- [(set_attr "length" "8,8,8,8,8,4,4,4")
- (set_attr "type" "*,load,store2,*,*,load,store2,*")
- (set_attr "pool_range" "*,1020,*,*,*,*,*,*")
- (set_attr "neg_pool_range" "*,1012,*,*,*,*,*,*")
- (set_attr "cirrus" "no,no,no,move,yes,double,double,yes")]
+ [(set_attr "length" " 8, 8, 8, 8, 8, 4, 4, 4")
+ (set_attr "type" " *,load,store2, *, *, load,store2, *")
+ (set_attr "pool_range" " *,1020, *, *, *, *, *, *")
+ (set_attr "neg_pool_range" " *,1012, *, *, *, *, *, *")
+ (set_attr "cirrus" "not, not, not,move,normal,double,double,normal")]
)
;; Cirrus SI values have been outlawed. Look in arm.h for the comment
cfldr32%?\\t%V0, %1
cfstr32%?\\t%V1, %0
cfsh32%?\\t%V0, %V1, #0"
- [(set_attr "type" "*,*,load,store1,*,*,load,store1,*")
- (set_attr "pool_range" "*,*,4096,*,*,*,1024,*,*")
- (set_attr "neg_pool_range" "*,*,4084,*,*,*,1012,*,*")
- (set_attr "cirrus" "no,no,no,no,move,yes,yes,yes,yes")]
+ [(set_attr "type" "*, *, load,store1, *, *, load,store1, *")
+ (set_attr "pool_range" "*, *, 4096, *, *, *, 1024, *, *")
+ (set_attr "neg_pool_range" "*, *, 4084, *, *, *, 1012, *, *")
+ (set_attr "cirrus" "not,not, not, not,move,normal,normal,normal,normal")]
)
(define_insn "*cirrus_movsf_hard_insn"
mov%?\\t%0, %1
ldr%?\\t%0, %1\\t%@ float
str%?\\t%1, %0\\t%@ float"
- [(set_attr "length" "*,*,*,*,*,4,4,4")
- (set_attr "type" "*,load,*,*,store1,*,load,store1")
- (set_attr "pool_range" "*,*,*,*,*,*,4096,*")
- (set_attr "neg_pool_range" "*,*,*,*,*,*,4084,*")
- (set_attr "cirrus" "yes,yes,move,yes,yes,no,no,no")]
+ [(set_attr "length" " *, *, *, *, *, 4, 4, 4")
+ (set_attr "type" " *, load, *, *,store1, *,load,store1")
+ (set_attr "pool_range" " *, *, *, *, *, *,4096, *")
+ (set_attr "neg_pool_range" " *, *, *, *, *, *,4084, *")
+ (set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")]
)
(define_insn "*cirrus_movdf_hard_insn"
default: abort ();
}
}"
- [(set_attr "type" "load,store2,*,store2,load,*,load,*,*,store2")
- (set_attr "length" "4,4,8,8,8,4,4,8,8,4")
- (set_attr "pool_range" "*,*,*,*,252,*,*,*,*,*")
- (set_attr "neg_pool_range" "*,*,*,*,244,*,*,*,*,*")
- (set_attr "cirrus" "no,no,no,no,no,yes,double,move,yes,double")]
+ [(set_attr "type" "load,store2, *,store2,load, *, load, *, *,store2")
+ (set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4")
+ (set_attr "pool_range" " *, *, *, *, 252, *, *, *, *, *")
+ (set_attr "neg_pool_range" " *, *, *, *, 244, *, *, *, *, *")
+ (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")]
)
git://gcc.gnu.org / gcc.git / commitdiff