Added DLB/DSTB peepholes for HFmode.

Corrected mnemonics for HImode DSTB peephole.

From-SVN: r10314

diff --git a/gcc/config/1750a/1750a.md b/gcc/config/1750a/1750a.md
index 02e64699c0679d45f9546e475bd5e0ef631f2a4b..bcfc64eb4d475b3e22920038f43cbf315187ec2f 100644 (file)
--- a/gcc/config/1750a/1750a.md
+++ b/gcc/config/1750a/1750a.md
@@ -1295,6 +1295,15 @@
     && INTVAL(operands[2]) <= 255"
   "dlb r%1,%2")
 
+(define_peephole 
+  [(set (match_operand:HF 0 "register_operand" "=r")
+        (mem:HF (plus:QI (match_operand:QI 1 "register_operand" "x")
+                         (match_operand:QI 2 "immediate_operand" "L"))))
+   ]
+  "REGNO(operands[0]) == 0 && REGNO(operands[1]) >= 12
+    && INTVAL(operands[2]) <= 255"
+  "dlb r%1,%2")
+
 ;; Store Base
 (define_peephole 
   [(set (mem:QI (plus:QI (match_operand:QI 0 "register_operand" "x")
@@ -1313,7 +1322,16 @@
    ]
   "REGNO(operands[2]) == 0 && REGNO(operands[0]) >= 12
     && INTVAL(operands[1]) <= 255"
-  "stb r%0,%1")
+  "dstb r%0,%1")
+
+(define_peephole 
+  [(set (mem:HF (plus:QI (match_operand:QI 0 "register_operand" "x")
+                         (match_operand:QI 1 "immediate_operand" "L")))
+       (match_operand:HF 2 "register_operand" "r"))
+   ]
+  "REGNO(operands[2]) == 0 && REGNO(operands[0]) >= 12
+    && INTVAL(operands[1]) <= 255"
+  "dstb r%0,%1")
 
 ;; Eliminate the redundant load in a store/load sequence
 (define_peephole