&& (INTVAL (op) == 2 || INTVAL (op) == 4 || INTVAL (op) == 8));
}
+int
+const_0_to_3_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+ return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 4);
+}
+
+int
+const_0_to_7_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+ return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 8);
+}
+
+int
+const_0_to_15_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+ return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 16);
+}
+
+int
+const_0_to_255_operand (register rtx op,
+ enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+ return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 256);
+}
+
+
/* True if this is a constant appropriate for an increment or decrement. */
int
return false;
code = (code == GTU ? GEU : LTU);
}
- else if (!nonimmediate_operand (op1, mode)
- || !general_operand (op0, mode))
- /* Swapping operands in this case would generate an
- unrecognizable insn. */
- return false;
else
{
rtx tmp = op1;
default:
return false;
}
+ /* Swapping operands may cause constant to appear as first operand. */
+ if (!nonimmediate_operand (op0, VOIDmode))
+ {
+ if (no_new_pseudos)
+ return false;
+ op0 = force_reg (mode, op0);
+ }
ix86_compare_op0 = op0;
ix86_compare_op1 = op1;
*pop = ix86_expand_compare (code, NULL, NULL);
/* In case the insn wants input operands in modes different from
the result, abort. */
- if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
+ if ((GET_MODE (op0) != mode0 && GET_MODE (op0) != VOIDmode)
+ || (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode))
abort ();
if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
op0 = copy_to_mode_reg (mode0, op0);
if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
{
- /* @@@ better error message */
- error ("selector must be an immediate");
+ error ("selector must be an integer constant in the range 0..%i",
+ fcode == IX86_BUILTIN_PEXTRW ? 3:7);
return gen_reg_rtx (tmode);
}
if (target == 0
op1 = copy_to_mode_reg (mode1, op1);
if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
{
- /* @@@ better error message */
- error ("selector must be an immediate");
+ error ("selector must be an integer constant in the range 0..%i",
+ fcode == IX86_BUILTIN_PINSRW ? 15:255);
return const0_rtx;
}
if (target == 0
")
(define_insn "zero_extendsidi2_32"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
- (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,m,m")))
(clobber (reg:CC 17))]
- "!TARGET_64BIT"
- "#"
- [(set_attr "mode" "SI")])
+ "!TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
+ "@
+ #
+ #
+ #
+ movd\t{%1, %0|%0, %1}
+ movd\t{%1, %0|%0, %1}"
+ [(set_attr "mode" "SI,SI,SI,DI,TI")
+ (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
+
+(define_insn "*zero_extendsidi2_32_1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,rm,rm")))
+ (clobber (reg:CC 17))]
+ "!TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
+ "@
+ #
+ #
+ #
+ movd\t{%1, %0|%0, %1}
+ movd\t{%1, %0|%0, %1}"
+ [(set_attr "mode" "SI,SI,SI,DI,TI")
+ (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
(define_insn "zero_extendsidi2_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
- (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
- "TARGET_64BIT"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!?Y")
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,m,m")))]
+ "TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
"@
mov\t{%k1, %k0|%k0, %k1}
- #"
- [(set_attr "type" "imovx,imov")
- (set_attr "mode" "SI,DI")])
+ #
+ movd\t{%1, %0|%0, %1}
+ movd\t{%1, %0|%0, %1}"
+ [(set_attr "type" "imovx,imov,mmxmov,ssemov")
+ (set_attr "mode" "SI,DI,DI,TI")])
+
+(define_insn "*zero_extendsidi2_rex64_1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!*?")
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,rm,rm")))]
+ "TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
+ "@
+ mov\t{%k1, %k0|%k0, %k1}
+ #
+ movd\t{%1, %0|%0, %1}
+ movd\t{%1, %0|%0, %1}"
+ [(set_attr "type" "imovx,imov,mmxmov,ssemov")
+ (set_attr "mode" "SI,DI,SI,SI")])
(define_split
[(set (match_operand:DI 0 "memory_operand" "")
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(zero_extend:DI (match_operand:SI 1 "general_operand" "")))
(clobber (reg:CC 17))]
- "!TARGET_64BIT && reload_completed"
+ "!TARGET_64BIT && reload_completed
+ && !SSE_REG_P (operands[0]) && !MMX_REG_P (operands[0])"
[(set (match_dup 3) (match_dup 1))
(set (match_dup 4) (const_int 0))]
"split_di (&operands[0], 1, &operands[3], &operands[4]);")
(vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
(vec_duplicate:V4HI
(truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
- (match_operand:SI 3 "immediate_operand" "i")))]
+ (match_operand:SI 3 "const_0_to_15_operand" "N")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pinsrw\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "mmxcvt")
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
(parallel
- [(match_operand:SI 2 "immediate_operand" "i")]))))]
+ [(match_operand:SI 2 "const_0_to_3_operand" "N")]))))]
"TARGET_SSE || TARGET_3DNOW_A"
"pextrw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "mmxcvt")
(vec_duplicate:V8HI
(truncate:HI
(match_operand:SI 2 "nonimmediate_operand" "rm")))
- (match_operand:SI 3 "immediate_operand" "i")))]
+ (match_operand:SI 3 "const_0_to_255_operand" "N")))]
"TARGET_SSE2"
"pinsrw\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssecvt")
(zero_extend:SI
(vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
(parallel
- [(match_operand:SI 2 "immediate_operand" "i")]))))]
+ [(match_operand:SI 2 "const_0_to_7_operand" "N")]))))]
"TARGET_SSE2"
"pextrw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecvt")