"rev8\t%0,%1"
[(set_attr "type" "bitmanip")])
+;; HI bswap can be emulated using SI/DI bswap followed
+;; by a logical shift right
+;; SI bswap for TARGET_64BIT is already similarly in
+;; the common code.
+(define_expand "bswaphi2"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (bswap:HI (match_operand:HI 1 "register_operand" "r")))]
+ "TARGET_ZBB"
+{
+ rtx tmp = gen_reg_rtx (word_mode);
+ rtx newop1 = gen_lowpart (word_mode, operands[1]);
+ if (TARGET_64BIT)
+ emit_insn (gen_bswapdi2 (tmp, newop1));
+ else
+ emit_insn (gen_bswapsi2 (tmp, newop1));
+ rtx tmp1 = gen_reg_rtx (word_mode);
+ if (TARGET_64BIT)
+ emit_insn (gen_lshrdi3 (tmp1, tmp, GEN_INT (64 - 16)));
+ else
+ emit_insn (gen_lshrsi3 (tmp1, tmp, GEN_INT (32 - 16)));
+ emit_move_insn (operands[0], gen_lowpart (HImode, tmp1));
+ DONE;
+})
+
(define_insn "<bitmanip_optab><mode>3"
[(set (match_operand:X 0 "register_operand" "=r")
(bitmanip_minmax:X (match_operand:X 1 "register_operand" "r")
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+int foo(int n)
+{
+ return __builtin_bswap16(n);
+}
+
+/* { dg-final { scan-assembler "rev8" } } */
+/* { dg-final { scan-assembler "srli" } } */
+
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+int foo(int n)
+{
+ return __builtin_bswap16(n);
+}
+
+/* { dg-final { scan-assembler "rev8" } } */
+/* { dg-final { scan-assembler "srli" } } */
+