* longlong.h: Fix macros for m32r add_ssaaaa and sub_ddmmss.

From-SVN: r83174

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d2c7c64e2542e701c0d118b5c9842bd0656782bd..fec39d76c9ead38a6241a8060c51d3ee119a8437 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -12,6 +12,8 @@
        (m32r_return_addr): Added for __builtin_return_address(0).
        (m32r_reload_lr): Ditto.
 
+       * longlong.h: Fix macros for m32r add_ssaaaa and sub_ddmmss. 
+       
 2004-06-15  Paolo Bonzini  <bonzini@gnu.org>
 
        * doc/install.texi (Prerequisites): Update libbanshee,

diff --git a/gcc/longlong.h b/gcc/longlong.h
index 0f5d05ffe2d357df2d546b96670bd4839e2043f3..05a706517b8f10c523e9a5e7d3e940347a806ef1 100644 (file)
--- a/gcc/longlong.h
+++ b/gcc/longlong.h
@@ -376,17 +376,17 @@ UDItype __umulsidi3 (USItype, USItype);
 #if defined (__M32R__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
-  __asm__ ("cmp %0,%0\n\taddx %%5,%1\n\taddx %%3,%0"                   \
+  __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"                     \
           : "=r" ((USItype) (sh)),                                     \
             "=&r" ((USItype) (sl))                                     \
-          : "%0" ((USItype) (ah)),                                     \
+          : "0" ((USItype) (ah)),                                      \
             "r" ((USItype) (bh)),                                      \
-            "%1" ((USItype) (al)),                                     \
+            "1" ((USItype) (al)),                                      \
             "r" ((USItype) (bl))                                       \
           : "cbit")
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
-  __asm__ ("cmp %0,%0\n\tsubx %5,%1\n\tsubx %3,%0"                     \
+  __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"                     \
           : "=r" ((USItype) (sh)),                                     \
             "=&r" ((USItype) (sl))                                     \
           : "0" ((USItype) (ah)),                                      \