return "add{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
- "&& reload_completed"
+ "&& reload_completed
+ && !(rtx_equal_p (operands[0], operands[1])
+ || rtx_equal_p (operands[0], operands[2]))"
[(set (strict_low_part (match_dup 0)) (match_dup 1))
(parallel
[(set (strict_low_part (match_dup 0))
(match_operand:QI 2 "const_int_operand")) 0))
(clobber (reg:CC FLAGS_REG))])])
-(define_insn "*addqi_ext<mode>_1"
+;; Alternative 1 is needed to work around LRA limitation, see PR82524.
+(define_insn_and_split "*addqi_ext<mode>_1"
[(set (zero_extract:SWI248
- (match_operand 0 "int248_register_operand" "+Q")
+ (match_operand 0 "int248_register_operand" "+Q,&Q")
(const_int 8)
(const_int 8))
(subreg:SWI248
(plus:QI
(subreg:QI
(match_operator:SWI248 3 "extract_operator"
- [(match_operand 1 "int248_register_operand" "0")
+ [(match_operand 1 "int248_register_operand" "0,!Q")
(const_int 8)
(const_int 8)]) 0)
- (match_operand:QI 2 "general_operand" "QnBn")) 0))
+ (match_operand:QI 2 "general_operand" "QnBn,QnBn")) 0))
(clobber (reg:CC FLAGS_REG))]
- "/* FIXME: without this LRA can't reload this pattern, see PR82524. */
- rtx_equal_p (operands[0], operands[1])"
+ ""
{
+ if (which_alternative)
+ return "#";
+
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return "inc{b}\t%h0";
else
- {
+ {
gcc_assert (operands[2] == constm1_rtx);
- return "dec{b}\t%h0";
- }
+ return "dec{b}\t%h0";
+ }
default:
return "add{b}\t{%2, %h0|%h0, %2}";
}
}
+ "reload_completed
+ && !rtx_equal_p (operands[0], operands[1])"
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (zero_extract:SWI248
+ (match_dup 1) (const_int 8) (const_int 8)))
+ (parallel
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (subreg:SWI248
+ (plus:QI
+ (subreg:QI
+ (match_op_dup 3
+ [(match_dup 0) (const_int 8) (const_int 8)]) 0)
+ (match_dup 2)) 0))
+ (clobber (reg:CC FLAGS_REG))])]
+ ""
[(set_attr "addr" "gpr8")
(set (attr "type")
(if_then_else (match_operand:QI 2 "incdec_operand")
(const_string "alu")))
(set_attr "mode" "QI")])
-(define_insn "*addqi_ext<mode>_2"
+;; Alternative 1 is needed to work around LRA limitation, see PR82524.
+(define_insn_and_split "*<insn>qi_ext<mode>_2"
[(set (zero_extract:SWI248
- (match_operand 0 "int248_register_operand" "+Q")
+ (match_operand 0 "int248_register_operand" "+Q,&Q")
(const_int 8)
(const_int 8))
(subreg:SWI248
- (plus:QI
+ (plusminus:QI
(subreg:QI
(match_operator:SWI248 3 "extract_operator"
- [(match_operand 1 "int248_register_operand" "%0")
+ [(match_operand 1 "int248_register_operand" "<comm>0,!Q")
(const_int 8)
(const_int 8)]) 0)
(subreg:QI
(match_operator:SWI248 4 "extract_operator"
- [(match_operand 2 "int248_register_operand" "Q")
+ [(match_operand 2 "int248_register_operand" "Q,Q")
(const_int 8)
(const_int 8)]) 0)) 0))
- (clobber (reg:CC FLAGS_REG))]
- "/* FIXME: without this LRA can't reload this pattern, see PR82524. */
- rtx_equal_p (operands[0], operands[1])
- || rtx_equal_p (operands[0], operands[2])"
- "add{b}\t{%h2, %h0|%h0, %h2}"
+ (clobber (reg:CC FLAGS_REG))]
+ ""
+ "@
+ <insn>{b}\t{%h2, %h0|%h0, %h2}
+ #"
+ "reload_completed
+ && !(rtx_equal_p (operands[0], operands[1])
+ || (<CODE> == PLUS && rtx_equal_p (operands[0], operands[2])))"
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (zero_extract:SWI248
+ (match_dup 1) (const_int 8) (const_int 8)))
+ (parallel
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (subreg:SWI248
+ (plusminus:QI
+ (subreg:QI
+ (match_op_dup 3
+ [(match_dup 0) (const_int 8) (const_int 8)]) 0)
+ (subreg:QI
+ (match_op_dup 4
+ [(match_dup 2) (const_int 8) (const_int 8)]) 0)) 0))
+ (clobber (reg:CC FLAGS_REG))])]
+ ""
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
"@
sub{<imodesuffix>}\t{%2, %0|%0, %2}
#"
- "&& reload_completed"
+ "&& reload_completed
+ && !(rtx_equal_p (operands[0], operands[1]))"
[(set (strict_low_part (match_dup 0)) (match_dup 1))
(parallel
[(set (strict_low_part (match_dup 0))
(set_attr "type" "alu")
(set_attr "mode" "QI")])
-(define_insn "*subqi_ext<mode>_2"
+;; Alternative 1 is needed to work around LRA limitation, see PR82524.
+(define_insn_and_split "*subqi_ext<mode>_1"
[(set (zero_extract:SWI248
- (match_operand 0 "int248_register_operand" "+Q")
+ (match_operand 0 "int248_register_operand" "+Q,&Q")
(const_int 8)
(const_int 8))
(subreg:SWI248
(minus:QI
(subreg:QI
(match_operator:SWI248 3 "extract_operator"
- [(match_operand 1 "int248_register_operand" "0")
+ [(match_operand 1 "int248_register_operand" "0,!Q")
(const_int 8)
(const_int 8)]) 0)
- (subreg:QI
- (match_operator:SWI248 4 "extract_operator"
- [(match_operand 2 "int248_register_operand" "Q")
- (const_int 8)
- (const_int 8)]) 0)) 0))
- (clobber (reg:CC FLAGS_REG))]
- "/* FIXME: without this LRA can't reload this pattern, see PR82524. */
- rtx_equal_p (operands[0], operands[1])"
- "sub{b}\t{%h2, %h0|%h0, %h2}"
- [(set_attr "type" "alu")
+ (match_operand:QI 2 "general_operand" "QnBn,QnBn")) 0))
+ (clobber (reg:CC FLAGS_REG))]
+ ""
+ "@
+ sub{b}\t{%2, %h0|%h0, %2}
+ #"
+ "reload_completed
+ && !(rtx_equal_p (operands[0], operands[1]))"
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (zero_extract:SWI248
+ (match_dup 1) (const_int 8) (const_int 8)))
+ (parallel
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (subreg:SWI248
+ (minus:QI
+ (subreg:QI
+ (match_op_dup 3
+ [(match_dup 0) (const_int 8) (const_int 8)]) 0)
+ (match_dup 2)) 0))
+ (clobber (reg:CC FLAGS_REG))])]
+ ""
+ [(set_attr "addr" "gpr8")
+ (set_attr "type" "alu")
(set_attr "mode" "QI")])
;; Subtract with jump on overflow.
(symbol_ref "true")))])
;; Alternative 1 is needed to work around LRA limitation, see PR82524.
-(define_insn_and_split "*and<mode>_1_slp"
+(define_insn_and_split "*<code><mode>_1_slp"
[(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+<r>,&<r>"))
- (and:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "%0,!<r>")
- (match_operand:SWI12 2 "general_operand" "<r>mn,<r>mn")))
+ (any_logic:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "%0,!<r>")
+ (match_operand:SWI12 2 "general_operand" "<r>mn,<r>mn")))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
"@
- and{<imodesuffix>}\t{%2, %0|%0, %2}
+ <logic>{<imodesuffix>}\t{%2, %0|%0, %2}
#"
- "&& reload_completed"
+ "&& reload_completed
+ && !(rtx_equal_p (operands[0], operands[1])
+ || rtx_equal_p (operands[0], operands[2]))"
[(set (strict_low_part (match_dup 0)) (match_dup 1))
(parallel
[(set (strict_low_part (match_dup 0))
- (and:SWI12 (match_dup 0) (match_dup 2)))
+ (any_logic:SWI12 (match_dup 0) (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
""
[(set_attr "type" "alu")
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
-(define_insn "*andqi_ext<mode>_0"
+(define_insn "*<code>qi_ext<mode>_0"
[(set (match_operand:QI 0 "nonimmediate_operand" "=QBn")
- (and:QI
+ (any_logic:QI
(subreg:QI
(match_operator:SWI248 3 "extract_operator"
[(match_operand 2 "int248_register_operand" "Q")
(match_operand:QI 1 "nonimmediate_operand" "0")))
(clobber (reg:CC FLAGS_REG))]
""
- "and{b}\t{%h2, %0|%0, %h2}"
+ "<logic>{b}\t{%h2, %0|%0, %h2}"
[(set_attr "addr" "gpr8")
(set_attr "type" "alu")
(set_attr "mode" "QI")])
(match_operand:QI 2 "const_int_operand")) 0))
(clobber (reg:CC FLAGS_REG))])])
-(define_insn "*andqi_ext<mode>_1"
+;; Alternative 1 is needed to work around LRA limitation, see PR82524.
+(define_insn_and_split "*<code>qi_ext<mode>_1"
[(set (zero_extract:SWI248
- (match_operand 0 "int248_register_operand" "+Q")
+ (match_operand 0 "int248_register_operand" "+Q,&Q")
(const_int 8)
(const_int 8))
(subreg:SWI248
- (and:QI
+ (any_logic:QI
(subreg:QI
(match_operator:SWI248 3 "extract_operator"
- [(match_operand 1 "int248_register_operand" "0")
+ [(match_operand 1 "int248_register_operand" "0,!Q")
(const_int 8)
(const_int 8)]) 0)
- (match_operand:QI 2 "general_operand" "QnBn")) 0))
+ (match_operand:QI 2 "general_operand" "QnBn,QnBn")) 0))
(clobber (reg:CC FLAGS_REG))]
- "/* FIXME: without this LRA can't reload this pattern, see PR82524. */
- rtx_equal_p (operands[0], operands[1])"
- "and{b}\t{%2, %h0|%h0, %2}"
+ ""
+ "@
+ <logic>{b}\t{%2, %h0|%h0, %2}
+ #"
+ "reload_completed
+ && !(rtx_equal_p (operands[0], operands[1]))"
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (zero_extract:SWI248
+ (match_dup 1) (const_int 8) (const_int 8)))
+ (parallel
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (subreg:SWI248
+ (any_logic:QI
+ (subreg:QI
+ (match_op_dup 3
+ [(match_dup 0) (const_int 8) (const_int 8)]) 0)
+ (match_dup 2)) 0))
+ (clobber (reg:CC FLAGS_REG))])]
+ ""
[(set_attr "addr" "gpr8")
(set_attr "type" "alu")
(set_attr "mode" "QI")])
-;; Generated by peephole translating test to and. This shows up
-;; often in fp comparisons.
-(define_insn "*andqi_ext<mode>_1_cc"
- [(set (reg FLAGS_REG)
- (compare
- (and:QI
- (subreg:QI
- (match_operator:SWI248 3 "extract_operator"
- [(match_operand 1 "int248_register_operand" "0")
- (const_int 8)
- (const_int 8)]) 0)
- (match_operand:QI 2 "general_operand" "QnBn"))
- (const_int 0)))
+;; Alternative 1 is needed to work around LRA limitation, see PR82524.
+(define_insn_and_split "*<code>qi_ext<mode>_1_cc"
+ [(set (match_operand 4 "flags_reg_operand")
+ (match_operator 5 "compare_operator"
+ [(any_logic:QI
+ (subreg:QI
+ (match_operator:SWI248 3 "extract_operator"
+ [(match_operand 1 "int248_register_operand" "0,!Q")
+ (const_int 8)
+ (const_int 8)]) 0)
+ (match_operand:QI 2 "general_operand" "QnBn,QnBn"))
+ (const_int 0)]))
(set (zero_extract:SWI248
- (match_operand 0 "int248_register_operand" "+Q")
+ (match_operand 0 "int248_register_operand" "+Q,&Q")
(const_int 8)
(const_int 8))
(subreg:SWI248
- (and:QI
+ (any_logic:QI
(subreg:QI
(match_op_dup 3
- [(match_dup 1)
- (const_int 8)
- (const_int 8)]) 0)
+ [(match_dup 0) (const_int 8) (const_int 8)]) 0)
(match_dup 2)) 0))]
- "ix86_match_ccmode (insn, CCNOmode)
- /* FIXME: without this LRA can't reload this pattern, see PR82524. */
- && rtx_equal_p (operands[0], operands[1])"
- "and{b}\t{%2, %h0|%h0, %2}"
+ "ix86_match_ccmode (insn, CCNOmode)"
+ "@
+ <logic>{b}\t{%2, %h0|%h0, %2}
+ #"
+ "&& reload_completed
+ && !(rtx_equal_p (operands[0], operands[1]))"
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (zero_extract:SWI248
+ (match_dup 1) (const_int 8) (const_int 8)))
+ (parallel
+ [(set (match_dup 4)
+ (match_op_dup 5
+ [(any_logic:QI
+ (subreg:QI
+ (match_op_dup 3
+ [(match_dup 0) (const_int 8) (const_int 8)]) 0)
+ (match_dup 2))
+ (const_int 0)]))
+ (set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (subreg:SWI248
+ (any_logic:QI
+ (subreg:QI
+ (match_op_dup 3
+ [(match_dup 1) (const_int 8) (const_int 8)]) 0)
+ (match_dup 2)) 0))])]
+ ""
[(set_attr "addr" "gpr8")
(set_attr "type" "alu")
(set_attr "mode" "QI")])
-(define_insn "*andqi_ext<mode>_2"
+;; Alternative 1 is needed to work around LRA limitation, see PR82524.
+(define_insn_and_split "*<code>qi_ext<mode>_2"
[(set (zero_extract:SWI248
- (match_operand 0 "int248_register_operand" "+Q")
+ (match_operand 0 "int248_register_operand" "+Q,&Q")
(const_int 8)
(const_int 8))
(subreg:SWI248
- (and:QI
+ (any_logic:QI
(subreg:QI
(match_operator:SWI248 3 "extract_operator"
- [(match_operand 1 "int248_register_operand" "%0")
+ [(match_operand 1 "int248_register_operand" "%0,!Q")
(const_int 8)
(const_int 8)]) 0)
(subreg:QI
(match_operator:SWI248 4 "extract_operator"
- [(match_operand 2 "int248_register_operand" "Q")
+ [(match_operand 2 "int248_register_operand" "Q,Q")
(const_int 8)
(const_int 8)]) 0)) 0))
(clobber (reg:CC FLAGS_REG))]
- "/* FIXME: without this LRA can't reload this pattern, see PR82524. */
- rtx_equal_p (operands[0], operands[1])
- || rtx_equal_p (operands[0], operands[2])"
- "and{b}\t{%h2, %h0|%h0, %h2}"
+ ""
+ "@
+ <logic>{b}\t{%h2, %h0|%h0, %h2}
+ #"
+ "reload_completed
+ && !(rtx_equal_p (operands[0], operands[1])
+ || rtx_equal_p (operands[0], operands[2]))"
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (zero_extract:SWI248
+ (match_dup 1) (const_int 8) (const_int 8)))
+ (parallel
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (subreg:SWI248
+ (any_logic:QI
+ (subreg:QI
+ (match_op_dup 3
+ [(match_dup 0) (const_int 8) (const_int 8)]) 0)
+ (subreg:QI
+ (match_op_dup 4
+ [(match_dup 2) (const_int 8) (const_int 8)]) 0)) 0))
+ (clobber (reg:CC FLAGS_REG))])]
+ ""
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
-;; *andqi_ext<mode>_3 is defined via *<code>qi_ext<mode>_3 below.
+;; Alternative 1 is needed to work around LRA limitation, see PR82524.
+(define_insn_and_split "*<code>qi_ext<mode>_3"
+ [(set (zero_extract:SWI248
+ (match_operand 0 "int248_register_operand" "+Q,&Q")
+ (const_int 8)
+ (const_int 8))
+ (match_operator:SWI248 3 "extract_operator"
+ [(any_logic
+ (match_operand 1 "int248_register_operand" "%0,!Q")
+ (match_operand 2 "int248_register_operand" "Q,Q"))
+ (const_int 8)
+ (const_int 8)]))
+ (clobber (reg:CC FLAGS_REG))]
+ "GET_MODE (operands[1]) == GET_MODE (operands[2])"
+ "@
+ <logic>{b}\t{%h2, %h0|%h0, %h2}
+ #"
+ "&& reload_completed
+ && !(rtx_equal_p (operands[0], operands[1])
+ || rtx_equal_p (operands[0], operands[2]))"
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (zero_extract:SWI248
+ (match_dup 1) (const_int 8) (const_int 8)))
+ (parallel
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (match_op_dup 3
+ [(any_logic (match_dup 4) (match_dup 2))
+ (const_int 8) (const_int 8)]))
+ (clobber (reg:CC FLAGS_REG))])]
+ "operands[4] = gen_lowpart (GET_MODE (operands[1]), operands[0]);"
+ [(set_attr "type" "alu")
+ (set_attr "mode" "QI")])
;; Convert wide AND instructions with immediate operand to shorter QImode
;; equivalents when possible.
(symbol_ref "!TARGET_PARTIAL_REG_STALL")]
(symbol_ref "true")))])
-;; Alternative 1 is needed to work around LRA limitation, see PR82524.
-(define_insn_and_split "*<code><mode>_1_slp"
- [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+<r>,&<r>"))
- (any_or:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "%0,!<r>")
- (match_operand:SWI12 2 "general_operand" "<r>mn,<r>mn")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
- "@
- <logic>{<imodesuffix>}\t{%2, %0|%0, %2}
- #"
- "&& reload_completed"
- [(set (strict_low_part (match_dup 0)) (match_dup 1))
- (parallel
- [(set (strict_low_part (match_dup 0))
- (any_or:SWI12 (match_dup 0) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))])]
- ""
- [(set_attr "type" "alu")
- (set_attr "mode" "<MODE>")])
-
;; convert (sign_extend:WIDE (any_logic:NARROW (memory, immediate)))
;; to (any_logic:WIDE (sign_extend (memory)), (sign_extend (immediate))).
;; This eliminates sign extension after logic operation.
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
-(define_insn "*<code>qi_ext<mode>_0"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=QBn")
- (any_or:QI
- (subreg:QI
- (match_operator:SWI248 3 "extract_operator"
- [(match_operand 2 "int248_register_operand" "Q")
- (const_int 8)
- (const_int 8)]) 0)
- (match_operand:QI 1 "nonimmediate_operand" "0")))
- (clobber (reg:CC FLAGS_REG))]
- ""
- "<logic>{b}\t{%h2, %0|%0, %h2}"
- [(set_attr "addr" "gpr8")
- (set_attr "type" "alu")
- (set_attr "mode" "QI")])
-
-(define_insn "*<code>qi_ext<mode>_1"
- [(set (zero_extract:SWI248
- (match_operand 0 "int248_register_operand" "+Q")
- (const_int 8)
- (const_int 8))
- (subreg:SWI248
- (any_or:QI
- (subreg:QI
- (match_operator:SWI248 3 "extract_operator"
- [(match_operand 1 "int248_register_operand" "0")
- (const_int 8)
- (const_int 8)]) 0)
- (match_operand:QI 2 "general_operand" "QnBn")) 0))
- (clobber (reg:CC FLAGS_REG))]
- "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
- /* FIXME: without this LRA can't reload this pattern, see PR82524. */
- && rtx_equal_p (operands[0], operands[1])"
- "<logic>{b}\t{%2, %h0|%h0, %2}"
- [(set_attr "addr" "gpr8")
- (set_attr "type" "alu")
- (set_attr "mode" "QI")])
-
-(define_insn "*<code>qi_ext<mode>_2"
- [(set (zero_extract:SWI248
- (match_operand 0 "int248_register_operand" "+Q")
- (const_int 8)
- (const_int 8))
- (subreg:SWI248
- (any_or:QI
- (subreg:QI
- (match_operator:SWI248 3 "extract_operator"
- [(match_operand 1 "int248_register_operand" "%0")
- (const_int 8)
- (const_int 8)]) 0)
- (subreg:QI
- (match_operator:SWI248 4 "extract_operator"
- [(match_operand 2 "int248_register_operand" "Q")
- (const_int 8)
- (const_int 8)]) 0)) 0))
- (clobber (reg:CC FLAGS_REG))]
- "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
- /* FIXME: without this LRA can't reload this pattern, see PR82524. */
- && (rtx_equal_p (operands[0], operands[1])
- || rtx_equal_p (operands[0], operands[2]))"
- "<logic>{b}\t{%h2, %h0|%h0, %h2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "QI")])
-
-(define_insn "*<code>qi_ext<mode>_3"
- [(set (zero_extract:SWI248
- (match_operand 0 "int248_register_operand" "+Q")
- (const_int 8)
- (const_int 8))
- (zero_extract:SWI248
- (any_logic:SWI248
- (match_operand 1 "int248_register_operand" "%0")
- (match_operand 2 "int248_register_operand" "Q"))
- (const_int 8)
- (const_int 8)))
- (clobber (reg:CC FLAGS_REG))]
- "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
- /* FIXME: without this LRA can't reload this pattern, see PR82524. */
- && (rtx_equal_p (operands[0], operands[1])
- || rtx_equal_p (operands[0], operands[2]))"
- "<logic>{b}\t{%h2, %h0|%h0, %h2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "QI")])
-
;; Convert wide OR instructions with immediate operand to shorter QImode
;; equivalents when possible.
;; Don't do the splitting with memory operands, since it introduces risk
(const_int 8)) 0)
(match_dup 2)) 0))])])
-(define_insn "*xorqi_ext<mode>_1_cc"
- [(set (reg FLAGS_REG)
- (compare
- (xor:QI
- (subreg:QI
- (match_operator:SWI248 3 "extract_operator"
- [(match_operand 1 "int248_register_operand" "0")
- (const_int 8)
- (const_int 8)]) 0)
- (match_operand:QI 2 "general_operand" "QnBn"))
- (const_int 0)))
- (set (zero_extract:SWI248
- (match_operand 0 "int248_register_operand" "+Q")
- (const_int 8)
- (const_int 8))
- (subreg:SWI248
- (xor:QI
- (subreg:QI
- (match_op_dup 3
- [(match_dup 1)
- (const_int 8)
- (const_int 8)]) 0)
- (match_dup 2)) 0))]
- "ix86_match_ccmode (insn, CCNOmode)
- /* FIXME: without this LRA can't reload this pattern, see PR82524. */
- && rtx_equal_p (operands[0], operands[1])"
- "xor{b}\t{%2, %h0|%h0, %2}"
- [(set_attr "addr" "gpr8")
- (set_attr "type" "alu")
- (set_attr "mode" "QI")])
-
;; Peephole2 rega = 0; rega op= regb into rega = regb.
(define_peephole2
[(parallel [(set (match_operand:SWI 0 "general_reg_operand")
"@
neg{<imodesuffix>}\t%0
#"
- "&& reload_completed"
+ "&& reload_completed
+ && !(rtx_equal_p (operands[0], operands[1]))"
[(set (strict_low_part (match_dup 0)) (match_dup 1))
(parallel
[(set (strict_low_part (match_dup 0))
(set (match_operand:SWI48 0 "register_operand")
(neg:SWI48 (match_dup 1)))])])
-(define_insn "*negqi_ext<mode>_2"
+;; Alternative 1 is needed to work around LRA limitation, see PR82524.
+(define_insn_and_split "*negqi_ext<mode>_1"
[(set (zero_extract:SWI248
- (match_operand 0 "int248_register_operand" "+Q")
+ (match_operand 0 "int248_register_operand" "+Q,&Q")
(const_int 8)
(const_int 8))
(subreg:SWI248
(neg:QI
(subreg:QI
(match_operator:SWI248 2 "extract_operator"
- [(match_operand 1 "int248_register_operand" "0")
+ [(match_operand 1 "int248_register_operand" "0,!Q")
(const_int 8)
(const_int 8)]) 0)) 0))
(clobber (reg:CC FLAGS_REG))]
- "/* FIXME: without this LRA can't reload this pattern, see PR82524. */
- rtx_equal_p (operands[0], operands[1])"
- "neg{b}\t%h0"
+ ""
+ "@
+ neg{b}\t%h0
+ #"
+ "reload_completed
+ && !(rtx_equal_p (operands[0], operands[1]))"
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (zero_extract:SWI248
+ (match_dup 1) (const_int 8) (const_int 8)))
+ (parallel
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (subreg:SWI248
+ (neg:QI
+ (subreg:QI
+ (match_op_dup 2
+ [(match_dup 0) (const_int 8) (const_int 8)]) 0)) 0))
+ (clobber (reg:CC FLAGS_REG))])]
+ ""
[(set_attr "type" "negnot")
(set_attr "mode" "QI")])
"@
not{<imodesuffix>}\t%0
#"
- "&& reload_completed"
+ "&& reload_completed
+ && !(rtx_equal_p (operands[0], operands[1]))"
[(set (strict_low_part (match_dup 0)) (match_dup 1))
(set (strict_low_part (match_dup 0))
(not:SWI12 (match_dup 0)))]
(const_int 0)]))
(set (match_dup 1)
(zero_extend:DI (xor:SI (match_dup 3) (const_int -1))))])])
+
+;; Alternative 1 is needed to work around LRA limitation, see PR82524.
+(define_insn_and_split "*one_cmplqi_ext<mode>_1"
+ [(set (zero_extract:SWI248
+ (match_operand 0 "int248_register_operand" "+Q,&Q")
+ (const_int 8)
+ (const_int 8))
+ (subreg:SWI248
+ (not:QI
+ (subreg:QI
+ (match_operator:SWI248 2 "extract_operator"
+ [(match_operand 1 "int248_register_operand" "0,!Q")
+ (const_int 8)
+ (const_int 8)]) 0)) 0))]
+ ""
+ "@
+ not{b}\t%h0
+ #"
+ "reload_completed
+ && !(rtx_equal_p (operands[0], operands[1]))"
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (zero_extract:SWI248
+ (match_dup 1) (const_int 8) (const_int 8)))
+ (set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (subreg:SWI248
+ (not:QI
+ (subreg:QI
+ (match_op_dup 2
+ [(match_dup 0) (const_int 8) (const_int 8)]) 0)) 0))]
+ ""
+ [(set_attr "type" "negnot")
+ (set_attr "mode" "QI")])
\f
;; Shift instructions
return "sal{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
- "&& reload_completed"
+ "&& reload_completed
+ && !(rtx_equal_p (operands[0], operands[1]))"
[(set (strict_low_part (match_dup 0)) (match_dup 1))
(parallel
[(set (strict_low_part (match_dup 0))
(const_string "*")))
(set_attr "mode" "<MODE>")])
-(define_insn "*ashlqi_ext<mode>_2"
+;; Alternative 1 is needed to work around LRA limitation, see PR82524.
+(define_insn_and_split "*ashlqi_ext<mode>_1"
[(set (zero_extract:SWI248
- (match_operand 0 "int248_register_operand" "+Q")
+ (match_operand 0 "int248_register_operand" "+Q,&Q")
(const_int 8)
(const_int 8))
(subreg:SWI248
(ashift:QI
(subreg:QI
(match_operator:SWI248 3 "extract_operator"
- [(match_operand 1 "int248_register_operand" "0")
+ [(match_operand 1 "int248_register_operand" "0,!Q")
(const_int 8)
(const_int 8)]) 0)
- (match_operand:QI 2 "nonmemory_operand" "cI")) 0))
- (clobber (reg:CC FLAGS_REG))]
- "/* FIXME: without this LRA can't reload this pattern, see PR82524. */
- rtx_equal_p (operands[0], operands[1])"
+ (match_operand:QI 2 "nonmemory_operand" "cI,cI")) 0))
+ (clobber (reg:CC FLAGS_REG))]
+ ""
{
+ if (which_alternative)
+ return "#";
+
switch (get_attr_type (insn))
{
case TYPE_ALU:
return "sal{b}\t{%2, %h0|%h0, %2}";
}
}
+ "reload_completed
+ && !(rtx_equal_p (operands[0], operands[1]))"
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (match_dup 1))
+ (parallel
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (subreg:SWI248
+ (ashift:QI
+ (subreg:QI
+ (match_op_dup 3
+ [(match_dup 0) (const_int 8) (const_int 8)]) 0)
+ (match_dup 2)) 0))
+ (clobber (reg:CC FLAGS_REG))])]
+ ""
[(set (attr "type")
(cond [(and (match_test "TARGET_DOUBLE_WITH_ADD")
(match_operand 2 "const1_operand"))
else
return "<shift>{<imodesuffix>}\t{%2, %0|%0, %2}";
}
- "&& reload_completed"
+ "&& reload_completed
+ && !(rtx_equal_p (operands[0], operands[1]))"
[(set (strict_low_part (match_dup 0)) (match_dup 1))
(parallel
[(set (strict_low_part (match_dup 0))
(const_string "*")))
(set_attr "mode" "<MODE>")])
-(define_insn "*<insn>qi_ext<mode>_2"
+;; Alternative 1 is needed to work around LRA limitation, see PR82524.
+(define_insn_and_split "*<insn>qi_ext<mode>_1"
[(set (zero_extract:SWI248
- (match_operand 0 "int248_register_operand" "+Q")
+ (match_operand 0 "int248_register_operand" "+Q,&Q")
(const_int 8)
(const_int 8))
(subreg:SWI248
(any_shiftrt:QI
(subreg:QI
(match_operator:SWI248 3 "extract_operator"
- [(match_operand 1 "int248_register_operand" "0")
+ [(match_operand 1 "int248_register_operand" "0,!Q")
(const_int 8)
(const_int 8)]) 0)
- (match_operand:QI 2 "nonmemory_operand" "cI")) 0))
- (clobber (reg:CC FLAGS_REG))]
- "/* FIXME: without this LRA can't reload this pattern, see PR82524. */
- rtx_equal_p (operands[0], operands[1])"
+ (match_operand:QI 2 "nonmemory_operand" "cI,cI")) 0))
+ (clobber (reg:CC FLAGS_REG))]
+ ""
{
+ if (which_alternative)
+ return "#";
+
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "<shift>{b}\t%h0";
else
return "<shift>{b}\t{%2, %h0|%h0, %2}";
}
+ "reload_completed
+ && !(rtx_equal_p (operands[0], operands[1]))"
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (match_dup 1))
+ (parallel
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (subreg:SWI248
+ (any_shiftrt:QI
+ (subreg:QI
+ (match_op_dup 3
+ [(match_dup 0) (const_int 8) (const_int 8)]) 0)
+ (match_dup 2)) 0))
+ (clobber (reg:CC FLAGS_REG))])]
+ ""
[(set_attr "type" "ishift")
(set (attr "length_immediate")
(if_then_else
else
return "<rotate>{<imodesuffix>}\t{%2, %0|%0, %2}";
}
- "&& reload_completed"
+ "&& reload_completed
+ && !(rtx_equal_p (operands[0], operands[1]))"
[(set (strict_low_part (match_dup 0)) (match_dup 1))
(parallel
[(set (strict_low_part (match_dup 0))