(define_expand "floathisf2"
[(set (match_operand:SF 0 "register_operand" "")
(float:SF (match_operand:HI 1 "nonimmediate_operand" "")))]
- "TARGET_SSE || TARGET_80387"
+ "TARGET_80387 || TARGET_SSE_MATH"
{
- if (TARGET_SSE && TARGET_SSE_MATH)
+ if (TARGET_SSE_MATH)
{
emit_insn (gen_floatsisf2 (operands[0],
convert_to_mode (SImode, operands[1], 0)));
}
})
-(define_insn "*floathisf2_1"
+(define_insn "*floathisf2_i387"
[(set (match_operand:SF 0 "register_operand" "=f,f")
- (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
- "TARGET_80387 && (!TARGET_SSE || !TARGET_SSE_MATH)"
+ (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
+ "TARGET_80387 && !TARGET_SSE_MATH"
"@
fild%z1\t%1
#"
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "register_operand" "")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
- "TARGET_SSE || TARGET_80387"
+ "TARGET_80387 || TARGET_SSE_MATH"
"")
-(define_insn "*floatsisf2_i387"
+(define_insn "*floatsisf2_mixed"
[(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
- "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
+ "TARGET_MIX_SSE_I387"
"@
fild%z1\t%1
#
(define_insn "*floatsisf2_sse"
[(set (match_operand:SF 0 "register_operand" "=x,x")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
- "TARGET_SSE"
+ "TARGET_SSE_MATH"
"cvtsi2ss\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "mode" "SF")
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
- "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
+ "reload_completed
+ && TARGET_SSE_MATH && TARGET_SSE_PARTIAL_REGS
&& SSE_REG_P (operands[0])"
[(const_int 0)]
{
DONE;
})
-(define_expand "floatdisf2"
- [(set (match_operand:SF 0 "register_operand" "")
- (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
- "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
- "")
-
-(define_insn "*floatdisf2_i387_only"
- [(set (match_operand:SF 0 "register_operand" "=f,?f")
- (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
- "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
+(define_insn "*floatsisf2_i387"
+ [(set (match_operand:SF 0 "register_operand" "=f,f")
+ (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
+ "TARGET_80387"
"@
fild%z1\t%1
#"
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
-(define_insn "*floatdisf2_i387"
+(define_expand "floatdisf2"
+ [(set (match_operand:SF 0 "register_operand" "")
+ (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
+ "TARGET_80387 || (TARGET_64BIT && TARGET_SSE_MATH)"
+ "")
+
+(define_insn "*floatdisf2_mixed"
[(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
- "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
+ "TARGET_64BIT && TARGET_MIX_SSE_I387"
"@
fild%z1\t%1
#
(define_insn "*floatdisf2_sse"
[(set (match_operand:SF 0 "register_operand" "=x,x")
(float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
- "TARGET_64BIT && TARGET_SSE"
+ "TARGET_64BIT && TARGET_SSE_MATH"
"cvtsi2ss{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "mode" "SF")
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
- "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
+ "reload_completed
+ && TARGET_64BIT && TARGET_SSE_MATH && TARGET_SSE_PARTIAL_REGS
&& SSE_REG_P (operands[0])"
[(const_int 0)]
{
DONE;
})
+(define_insn "*floatdisf2_i387"
+ [(set (match_operand:SF 0 "register_operand" "=f,f")
+ (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
+ "TARGET_80387"
+ "@
+ fild%z1\t%1
+ #"
+ [(set_attr "type" "fmov,multi")
+ (set_attr "mode" "SF")
+ (set_attr "fp_int_src" "true")])
+
(define_expand "floathidf2"
[(set (match_operand:DF 0 "register_operand" "")
(float:DF (match_operand:HI 1 "nonimmediate_operand" "")))]
- "TARGET_SSE2 || TARGET_80387"
+ "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
{
- if (TARGET_SSE && TARGET_SSE_MATH)
+ if (TARGET_SSE2 && TARGET_SSE_MATH)
{
emit_insn (gen_floatsidf2 (operands[0],
convert_to_mode (SImode, operands[1], 0)));
}
})
-(define_insn "*floathidf2_1"
+(define_insn "*floathidf2_i387"
[(set (match_operand:DF 0 "register_operand" "=f,f")
- (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
- "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
+ (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
+ "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
"@
fild%z1\t%1
#"
(define_expand "floatsidf2"
[(set (match_operand:DF 0 "register_operand" "")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
- "TARGET_80387 || TARGET_SSE2"
+ "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
"")
-(define_insn "*floatsidf2_i387"
+(define_insn "*floatsidf2_mixed"
[(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
- "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
+ "TARGET_SSE2 && TARGET_MIX_SSE_I387"
"@
fild%z1\t%1
#
(define_insn "*floatsidf2_sse"
[(set (match_operand:DF 0 "register_operand" "=Y,Y")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
- "TARGET_SSE2"
+ "TARGET_SSE2 && TARGET_SSE_MATH"
"cvtsi2sd\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "mode" "DF")
(set_attr "athlon_decode" "double,direct")
(set_attr "fp_int_src" "true")])
-(define_expand "floatdidf2"
- [(set (match_operand:DF 0 "register_operand" "")
- (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
- "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
- "")
-
-(define_insn "*floatdidf2_i387_only"
- [(set (match_operand:DF 0 "register_operand" "=f,?f")
- (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
- "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
+(define_insn "*floatsidf2_i387"
+ [(set (match_operand:DF 0 "register_operand" "=f,f")
+ (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
+ "TARGET_80387"
"@
fild%z1\t%1
#"
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
-(define_insn "*floatdidf2_i387"
+(define_expand "floatdidf2"
+ [(set (match_operand:DF 0 "register_operand" "")
+ (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
+ "TARGET_80387 || (TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH)"
+ "")
+
+(define_insn "*floatdidf2_mixed"
[(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
- "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
+ "TARGET_64BIT && TARGET_SSE2 && TARGET_MIX_SSE_I387"
"@
fild%z1\t%1
#
(define_insn "*floatdidf2_sse"
[(set (match_operand:DF 0 "register_operand" "=Y,Y")
(float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
- "TARGET_SSE2"
+ "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
"cvtsi2sd{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "mode" "DF")
(set_attr "athlon_decode" "double,direct")
(set_attr "fp_int_src" "true")])
+(define_insn "*floatdidf2_i387"
+ [(set (match_operand:DF 0 "register_operand" "=f,f")
+ (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
+ "TARGET_80387"
+ "@
+ fild%z1\t%1
+ #"
+ [(set_attr "type" "fmov,multi")
+ (set_attr "mode" "DF")
+ (set_attr "fp_int_src" "true")])
+
(define_insn "floathixf2"
[(set (match_operand:XF 0 "register_operand" "=f,f")
- (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
+ (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
"TARGET_80387"
"@
fild%z1\t%1
(define_insn "floatsixf2"
[(set (match_operand:XF 0 "register_operand" "=f,f")
- (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
+ (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
"TARGET_80387"
"@
fild%z1\t%1
(define_insn "floatdixf2"
[(set (match_operand:XF 0 "register_operand" "=f,f")
- (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
+ (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
"TARGET_80387"
"@
fild%z1\t%1
(define_split
[(set (match_operand 0 "fp_register_operand" "")
(float (match_operand 1 "register_operand" "")))]
- "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
+ "reload_completed
+ && TARGET_80387
+ && FLOAT_MODE_P (GET_MODE (operands[0]))"
[(const_int 0)]
{
operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
(define_expand "floatunssisf2"
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SI 1 "register_operand" ""))]
- "TARGET_SSE && TARGET_SSE_MATH && !TARGET_64BIT"
+ "!TARGET_64BIT && TARGET_SSE_MATH"
"x86_emit_floatuns (operands); DONE;")
(define_expand "floatunsdisf2"
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:DI 1 "register_operand" ""))]
- "TARGET_SSE && TARGET_SSE_MATH && TARGET_64BIT"
+ "TARGET_64BIT && TARGET_SSE_MATH"
"x86_emit_floatuns (operands); DONE;")
(define_expand "floatunsdidf2"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DI 1 "register_operand" ""))]
- "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_64BIT"
+ "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
"x86_emit_floatuns (operands); DONE;")
\f
;; SSE extract/set expanders