static bool is_aligning_offset (const_tree, const_tree);
static rtx reduce_to_bit_field_precision (rtx, rtx, tree);
-static rtx do_store_flag (sepops, rtx, machine_mode);
+static rtx do_store_flag (const_sepops, rtx, machine_mode);
#ifdef PUSH_ROUNDING
static void emit_single_push_insn (machine_mode, rtx, tree);
#endif
}
rtx
-expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode,
+expand_expr_real_2 (const_sepops ops, rtx target, machine_mode tmode,
enum expand_modifier modifier)
{
rtx op0, op1, op2, temp;
set/jump/set sequence. */
static rtx
-do_store_flag (sepops ops, rtx target, machine_mode mode)
+do_store_flag (const_sepops ops, rtx target, machine_mode mode)
{
enum rtx_code code;
tree arg0, arg1, type;
if (new_code != ops->code)
{
struct separate_ops nops = *ops;
- nops.code = ops->code = new_code;
+ nops.code = new_code;
nops.op0 = arg0;
nops.op1 = arg1;
nops.type = TREE_TYPE (arg0);
tree type;
tree op0, op1, op2;
} *sepops;
+
+typedef const struct separate_ops *const_sepops;
\f
/* This is run during target initialization to set up which modes can be
used directly in memory and to initialize the block move optab. */
enum expand_modifier, rtx *, bool);
extern rtx expand_expr_real_1 (tree, rtx, machine_mode,
enum expand_modifier, rtx *, bool);
-extern rtx expand_expr_real_2 (sepops, rtx, machine_mode,
+extern rtx expand_expr_real_2 (const_sepops, rtx, machine_mode,
enum expand_modifier);
extern rtx expand_expr_real_gassign (gassign *, rtx, machine_mode,
enum expand_modifier modifier,
type-promotion (vec-unpack) 1 oprnd0 - - */
rtx
-expand_widen_pattern_expr (sepops ops, rtx op0, rtx op1, rtx wide_op,
+expand_widen_pattern_expr (const_sepops ops, rtx op0, rtx op1, rtx wide_op,
rtx target, int unsignedp)
{
class expand_operand eops[4];
OPTAB_MUST_WIDEN
};
-extern rtx expand_widen_pattern_expr (struct separate_ops *, rtx , rtx , rtx,
+extern rtx expand_widen_pattern_expr (const struct separate_ops *, rtx , rtx , rtx,
rtx, int);
extern rtx expand_ternary_op (machine_mode mode, optab ternary_optab,
rtx op0, rtx op1, rtx op2, rtx target,