This adds new regression tests to ensure half-register rotations are
correctly optimized into rori instructions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-rol-ror-08.c: New test.
* gcc.target/riscv/zbb-rol-ror-09.c: New test.
Co-authored-by: Charlie Jenkins <charlie@rivosinc.com>
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-final { scan-assembler-not "and" } } */
+
+/*
+**foo1:
+** rori a0,a0,32
+** ret
+*/
+unsigned long foo1(unsigned long rotate)
+{
+ return (rotate << 32) | (rotate >> 32);
+}
+
+/*
+**foo2:
+** roriw a0,a0,16
+** ret
+*/
+unsigned int foo2(unsigned int rotate)
+{
+ return (rotate << 16) | (rotate >> 16);
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -fno-lto -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-final { scan-assembler-not "and" } } */
+
+/*
+**foo1:
+** rori a0,a0,16
+** ret
+*/
+unsigned int foo1(unsigned int rs1)
+{
+ return (rs1 << 16) | (rs1 >> 16);
+}