In same cases, like gcc/testsuite/gcc.dg/pr78148.c in RISC-V, there will
be only 1 operand when SET_SRC in create_pre_exit. For example as below.
(insn 13 9 14 2 (clobber (reg/i:TI 10 a0)) "gcc/testsuite/gcc.dg/pr78148.c":24:1 -1
(expr_list:REG_UNUSED (reg/i:TI 10 a0)
(nil)))
Unfortunately, SET_SRC requires at least 2 operands and then Segment
Fault here. For SH4 part result in Segment Fault, it looks like only
valid when the return_copy_pat is load or something like that. Thus,
this patch try to fix it by restrict the SET insn for SET_SRC.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* mode-switching.cc (create_pre_exit): Add SET insn check.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mode-switch-ice-1.c: New test.
conflict with address reloads. */
if (copy_start >= ret_start
&& copy_start + copy_num <= ret_end
+ && GET_CODE (return_copy_pat) == SET
&& OBJECT_P (SET_SRC (return_copy_pat)))
forced_late_switch = true;
break;
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct A { char e, f; };
+
+struct B
+{
+ int g;
+ struct A h[4];
+};
+
+extern void bar (int, int);
+
+struct B foo (void)
+{
+ bar (2, 1);
+}
+
+void baz ()
+{
+ foo ();
+}