RISC-V: Add __RISCV_ prefix to VXRM and FRM enum

According to doc:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222/files
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226

Add __RISCV_ prefix to VXRM and FRM enum.

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_VXRM_ENUM): Add
	__RISCV_ prefix.
	(DEF_RVV_FRM_ENUM): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/frm-1.c: Ditto.
	* gcc.target/riscv/rvv/base/vxrm-1.c: Ditto.
	* gcc.target/riscv/rvv/base/vxrm-10.c: Ditto.
	* gcc.target/riscv/rvv/base/vxrm-11.c: Ditto.
	* gcc.target/riscv/rvv/base/vxrm-12.c: Ditto.
	* gcc.target/riscv/rvv/base/vxrm-6.c: Ditto.
	* gcc.target/riscv/rvv/base/vxrm-7.c: Ditto.
	* gcc.target/riscv/rvv/base/vxrm-8.c: Ditto.
	* gcc.target/riscv/rvv/base/vxrm-9.c: Ditto.

diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 43bf6d8f262cedfe0b67458820d01c03f90ac3b0..9e6dae98a6d6bc8c56ea12571421025ca88b3077 100644 (file)
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -4026,11 +4026,11 @@ register_vxrm ()
 {
   auto_vec<string_int_pair, 4> values;
 #define DEF_RVV_VXRM_ENUM(NAME, VALUE)                                          \
-  values.quick_push (string_int_pair ("VXRM_" #NAME, VALUE));
+  values.quick_push (string_int_pair ("__RISCV_VXRM_" #NAME, VALUE));
 #include "riscv-vector-builtins.def"
 #undef DEF_RVV_VXRM_ENUM
 
-  lang_hooks.types.simulate_enum_decl (input_location, "RVV_VXRM", &values);
+  lang_hooks.types.simulate_enum_decl (input_location, "__RISCV_VXRM", &values);
 }
 
 /* Register the frm enum.  */
@@ -4039,11 +4039,11 @@ register_frm ()
 {
   auto_vec<string_int_pair, 5> values;
 #define DEF_RVV_FRM_ENUM(NAME, VALUE)                                          \
-  values.quick_push (string_int_pair ("FRM_" #NAME, VALUE));
+  values.quick_push (string_int_pair ("__RISCV_FRM_" #NAME, VALUE));
 #include "riscv-vector-builtins.def"
 #undef DEF_RVV_FRM_ENUM
 
-  lang_hooks.types.simulate_enum_decl (input_location, "RVV_FRM", &values);
+  lang_hooks.types.simulate_enum_decl (input_location, "__RISCV_FRM", &values);
 }
 
 /* Implement #pragma riscv intrinsic vector.  */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c
index f5635fb959e3e2069ef33df0c41b591edd0be85c..ff19c8bc0890da1e406eea37b6b4a95f91b96d40 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c
@@ -5,27 +5,27 @@
 
 size_t f0 ()
 {
-  return FRM_RNE;
+  return __RISCV_FRM_RNE;
 }
 
 size_t f1 ()
 {
-  return FRM_RTZ;
+  return __RISCV_FRM_RTZ;
 }
 
 size_t f2 ()
 {
-  return FRM_RDN;
+  return __RISCV_FRM_RDN;
 }
 
 size_t f3 ()
 {
-  return FRM_RUP;
+  return __RISCV_FRM_RUP;
 }
 
 size_t f4 ()
 {
-  return FRM_RMM;
+  return __RISCV_FRM_RMM;
 }
 
 /* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*0} 1} } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c
index 0d364787ad036f547f4376ad32c9ead8d9d284c9..b0ed27b0520ed0c38672b44c6ba9804b1f172bfc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c
@@ -5,22 +5,22 @@
 
 size_t f0 ()
 {
-  return VXRM_RNU;
+  return __RISCV_VXRM_RNU;
 }
 
 size_t f1 ()
 {
-  return VXRM_RNE;
+  return __RISCV_VXRM_RNE;
 }
 
 size_t f2 ()
 {
-  return VXRM_RDN;
+  return __RISCV_VXRM_RDN;
 }
 
 size_t f3 ()
 {
-  return VXRM_ROD;
+  return __RISCV_VXRM_ROD;
 }
 
 /* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*0} 1} } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c
index a707aa1645e2a5250e3a4ccc0e7b249bfee405fa..3c7872bb73df2776dfc70879856c22a054986edc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c
@@ -8,16 +8,16 @@ void f (void * in, void *out, int32_t x, int n, int m)
   for (int i = 0; i < n; i++) {
     vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
     vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
-    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
-    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4);
+    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4);
     __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
   }
   
   for (int i = 0; i < n; i++) {
     vint32m1_t v = __riscv_vle32_v_i32m1 (in + i + 1000, 4);
     vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i + 1000, 4);
-    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RNE, 4);
-    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RNE, 4);
+    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RNE, 4);
+    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RNE, 4);
     __riscv_vse32_v_i32m1 (out + 100 + i + 1000, v3, 4);
   }
 }

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
index 7f637a8b7f5e615b2c17d74724451df0656ab47d..2cbd548eeb6aea5d8ebea21e2e08917a35654dfb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
@@ -10,9 +10,9 @@ void f (void * in, void *out, int32_t x, int n, int m)
   for (int i = 0; i < n; i++) {
     vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
     vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
-    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
+    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4);
     fn ();
-    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4);
     __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
   }
 }

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
index c3ab509f10681cc027000334aa3c804f6c4c530b..95a58ca6b904fb1cfb17fab88fe9aa7d7b6ae7ae 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
@@ -8,9 +8,9 @@ void f (void * in, void *out, int32_t x, int n, int m)
   for (int i = 0; i < n; i++) {
     vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
     vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
-    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
+    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4);
     asm volatile ("csrwi\tvxrm,1");
-    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4);
     __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
   }
 }

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-6.c
index 4b346d67c27b40b6f81aca206257db9db71e3e54..6ef469fdce8a53aa9ecd8ee4422f198c157b3c70 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-6.c
@@ -7,8 +7,8 @@ void f (void * in, void *out, int32_t x, int n, int m)
 {
   vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
   vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100, 4);
-  vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
-  v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+  vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4);
+  v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4);
   __riscv_vse32_v_i32m1 (out + 100, v3, 4);
 }
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-7.c
index 1ca795ce3f4c7623870359b26fbcb41da3c0ae17..50902c37a551ffe7bd839f0a42c6f8ad0ab0eb34 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-7.c
@@ -7,8 +7,8 @@ void f (void * in, void *out, int32_t x, int n, int m)
 {
   vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
   vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100, 4);
-  vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RNE, 4);
-  v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+  vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RNE, 4);
+  v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4);
   __riscv_vse32_v_i32m1 (out + 100, v3, 4);
 }
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-8.c
index 5799f731e210b0eb493023a59408d65ccd3f4b25..3ed0d00d1e93888135425866e44b40aeffdb0a9a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-8.c
@@ -8,8 +8,8 @@ void f (void * in, void *out, int32_t x, int n, int m)
   for (int i = 0; i < n; i++) {
     vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
     vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
-    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
-    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4);
+    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4);
     __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
   }
 }

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-9.c
index 13921d4af212722f98b28cb0af1e8fd6916fe765..0939705b2e76d4e98361a1eedf53e791fa6461ee 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-9.c
@@ -8,16 +8,16 @@ void f (void * in, void *out, int32_t x, int n, int m)
   for (int i = 0; i < n; i++) {
     vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
     vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
-    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
-    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4);
+    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4);
     __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
   }
   
   for (int i = 0; i < n; i++) {
     vint32m1_t v = __riscv_vle32_v_i32m1 (in + i + 1000, 4);
     vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i + 1000, 4);
-    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
-    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, __RISCV_VXRM_RDN, 4);
+    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, __RISCV_VXRM_RDN, 4);
     __riscv_vse32_v_i32m1 (out + 100 + i + 1000, v3, 4);
   }
 }