if (GET_CODE (index) == CONST_INT)
{
+ /* Short 5-bit displacements always okay. */
if (INT_5_BITS (index))
return true;
- /* When INT14_OK_STRICT is false, a secondary reload is needed
- to adjust the displacement of SImode and DImode floating point
- instructions but this may fail when the register also needs
- reloading. So, we return false when STRICT is true. We
- also reject long displacements for float mode addresses since
- the majority of accesses will use floating point instructions
- that don't support 14-bit offsets. */
- if (!INT14_OK_STRICT
- && (strict || !(reload_in_progress || reload_completed))
- && mode != QImode
- && mode != HImode)
+ if (!base14_operand (index, mode))
return false;
- return base14_operand (index, mode);
+ /* Long 14-bit displacements always okay for these cases. */
+ if (INT14_OK_STRICT
+ || mode == QImode
+ || mode == HImode)
+ return true;
+
+ /* A secondary reload may be needed to adjust the displacement
+ of floating-point accesses when STRICT is nonzero. */
+ if (strict)
+ return false;
+
+ /* We get significantly better code if we allow long displacements
+ before reload for all accesses. Instructions must satisfy their
+ constraints after reload, so we must have an integer access.
+ Return true for both cases. */
+ return true;
}
if (!TARGET_DISABLE_INDEXING
#define TARGET_ELF32 0
#endif
+/* Generate code for ELF64 ABI. */
+#ifndef TARGET_ELF64
+#define TARGET_ELF64 0
+#endif
+
/* Generate code for SOM 32bit ABI. */
#ifndef TARGET_SOM
#define TARGET_SOM 0
/* Nonzero if 14-bit offsets can be used for all loads and stores.
This is not possible when generating PA 1.x code as floating point
- loads and stores only support 5-bit offsets. Note that we do not
- forbid the use of 14-bit offsets for integer modes. Instead, we
- use secondary reloads to fix REG+D memory addresses for integer
- mode floating-point loads and stores.
+ accesses only support 5-bit offsets. Note that we do not forbid
+ the use of 14-bit offsets prior to reload. Instead, we use secondary
+ reloads to fix REG+D memory addresses for floating-point accesses.
- FIXME: the ELF32 linker clobbers the LSB of the FP register number
+ FIXME: the GNU ELF linker clobbers the LSB of the FP register number
in PA 2.0 floating-point insns with long displacements. This is
because R_PARISC_DPREL14WR and other relocations like it are not
yet supported by GNU ld. For now, we reject long displacements
#define INT14_OK_STRICT \
(TARGET_SOFT_FLOAT \
- || (TARGET_PA_20 && !TARGET_ELF32))
+ || (TARGET_PA_20 && !TARGET_ELF32 && !TARGET_ELF64))
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
and check its validity for a certain class.
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
+/* 64-bit ELF target. */
+#undef TARGET_ELF64
+#define TARGET_ELF64 1
+
#if 0 /* needs some work :-( */
/* If defined, this macro specifies a table of register pairs used to
eliminate unneeded registers that point into the stack frame. */
if (!INT_14_BITS (op))
return false;
+ /* Short displacement. */
+ if (INT_5_BITS (op))
+ return true;
+
/* Although this may not be necessary, we require that the
base value is correctly aligned for its mode as this is
assumed in the instruction encoding. */
if (reg_plus_base_memory_operand (op, mode))
{
- if (reload_in_progress)
- return true;
-
/* Extract CONST_INT operand. */
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
op = XEXP (op, 0);
op = REG_P (XEXP (op, 0)) ? XEXP (op, 1) : XEXP (op, 0);
- return base14_operand (op, mode) || INT_5_BITS (op);
+ return base14_operand (op, mode);
}
if (!MEM_P (op))
if (reg_plus_base_memory_operand (op, mode))
{
- if (reload_in_progress)
- return true;
-
/* Extract CONST_INT operand. */
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
op = XEXP (op, 0);
op = REG_P (XEXP (op, 0)) ? XEXP (op, 1) : XEXP (op, 0);
- return ((TARGET_PA_20
- && !TARGET_ELF32
- && base14_operand (op, mode))
+ return ((INT14_OK_STRICT && base14_operand (op, mode))
|| INT_5_BITS (op));
}