bfin.md (addv2hi3, [...]): Pattern names fixed by appending the necessary digit.

	* config/bfin/bfin.md (addv2hi3, subv2hi3, sminv2hi3, smaxv2hi3,
	mulv2hi3, negv2hi2, absv2hi2): Pattern names fixed by appending the
	necessary digit.

From-SVN: r101461

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6a9d21270d2d5f6bbd11cadb193684af5318f673..db9151564e56b22b2862c99df46977691c91cbc2 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2005-06-30  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+       * config/bfin/bfin.md (addv2hi3, subv2hi3, sminv2hi3, smaxv2hi3,
+       mulv2hi3, negv2hi2, absv2hi2): Pattern names fixed by appending the
+       necessary digit.
+
 2005-06-29  David Edelsohn  <edelsohn@gnu.org>
 
        * config/rs6000/rs6000.c (rs6000_file_start): Use PPC405_ERRATUM77.

diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index 984f3d0d41c57f136701dc7875367f09b63c1b52..76d6e13d89a2a8524020ac49243cc7c5f6e02963 100644 (file)
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -1941,7 +1941,7 @@
 
 ;;; Vector instructions
 
-(define_insn "addv2hi"
+(define_insn "addv2hi3"
   [(set (match_operand:V2HI 0 "register_operand" "=d")
        (plus:V2HI (match_operand:V2HI 1 "register_operand" "d")
                   (match_operand:V2HI 2 "register_operand" "d")))]
@@ -1949,7 +1949,7 @@
   "%0 = %1 +|+ %2;"
   [(set_attr "type" "dsp32")])
 
-(define_insn "subv2hi"
+(define_insn "subv2hi3"
   [(set (match_operand:V2HI 0 "register_operand" "=d")
        (minus:V2HI (match_operand:V2HI 1 "register_operand" "d")
                   (match_operand:V2HI 2 "register_operand" "d")))]
@@ -1957,7 +1957,7 @@
   "%0 = %1 -|- %2;"
   [(set_attr "type" "dsp32")])
 
-(define_insn "sminv2hi"
+(define_insn "sminv2hi3"
   [(set (match_operand:V2HI 0 "register_operand" "=d")
        (smin:V2HI (match_operand:V2HI 1 "register_operand" "d")
                   (match_operand:V2HI 2 "register_operand" "d")))]
@@ -1965,7 +1965,7 @@
   "%0 = MIN (%1, %2) (V);"
   [(set_attr "type" "dsp32")])
 
-(define_insn "smaxv2hi"
+(define_insn "smaxv2hi3"
   [(set (match_operand:V2HI 0 "register_operand" "=d")
        (smax:V2HI (match_operand:V2HI 1 "register_operand" "d")
                   (match_operand:V2HI 2 "register_operand" "d")))]
@@ -1973,7 +1973,7 @@
   "%0 = MAX (%1, %2) (V);"
   [(set_attr "type" "dsp32")])
 
-(define_insn "mulv2hi"
+(define_insn "mulv2hi3"
   [(set (match_operand:V2HI 0 "register_operand" "=d")
        (mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
                   (match_operand:V2HI 2 "register_operand" "d")))]
@@ -1981,14 +1981,14 @@
   "%h0 = %h1 * %h2, %d0 = %d1 * %d2 (IS);"
   [(set_attr "type" "dsp32")])
 
-(define_insn "negv2hi"
+(define_insn "negv2hi2"
   [(set (match_operand:V2HI 0 "register_operand" "=d")
        (neg:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
   ""
   "%0 = - %1 (V);"
   [(set_attr "type" "dsp32")])
 
-(define_insn "absv2hi"
+(define_insn "absv2hi2"
   [(set (match_operand:V2HI 0 "register_operand" "=d")
        (abs:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
   ""