re PR target/40697 (inefficient code to extract least bits from an integer value)

gcc/
	PR target/40697
	* optabs.c (avoid_expensive_constant): Use rtx_cost to find out
	the cost of loading the constant rather than assuming
	COSTS_N_INSNS (1).
	* config/arm/arm.c (thumb1_rtx_costs) <case CONST_INT>: If the
	outer code is AND, do the same tests as the andsi3 expander and
	return COSTS_N_INSNS (1) if and is cheap.

testsuite/
	PR target/40697
	* gcc.target/arm/thumb-andsi.c: New test.

From-SVN: r157582

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bdc8dae8da080a50bb06068b77d9ba3a3c5bb19f..7afdbaca8ba1cc18fec8c38dd25765b31f98729d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -4,6 +4,14 @@
        * ira-lives.c (check_and_make_def_conflict): Ignore conflict for a
        use that may match DEF.
 
+       PR target/40697
+       * optabs.c (avoid_expensive_constant): Use rtx_cost to find out
+       the cost of loading the constant rather than assuming
+       COSTS_N_INSNS (1).
+       * config/arm/arm.c (thumb1_rtx_costs) <case CONST_INT>: If the
+       outer code is AND, do the same tests as the andsi3 expander and
+       return COSTS_N_INSNS (1) if and is cheap.
+       
 2010-03-19  Michael Matz  <matz@suse.de>
 
        PR c++/43116

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 870e56ed85ed7e2e283a3803a45079eb156ed310..cc023c1efdaf6c15c6b96c4d0050db9e6e00118f 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -6228,6 +6228,15 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
       else if ((outer == IOR || outer == XOR || outer == AND)
               && INTVAL (x) < 256 && INTVAL (x) >= -256)
        return COSTS_N_INSNS (1);
+      else if (outer == AND)
+       {
+         int i;
+         /* This duplicates the tests in the andsi3 expander.  */
+         for (i = 9; i <= 31; i++)
+           if ((((HOST_WIDE_INT) 1) << i) - 1 == INTVAL (x)
+               || (((HOST_WIDE_INT) 1) << i) - 1 == ~INTVAL (x))
+             return COSTS_N_INSNS (2);
+       }
       else if (outer == ASHIFT || outer == ASHIFTRT
               || outer == LSHIFTRT)
        return 0;

diff --git a/gcc/optabs.c b/gcc/optabs.c
index 747166b18d38b8d278a1f42ea4f22419698c143a..a82619e7cf3e222ebcbe7cf9dd34ed0c9216a4b9 100644 (file)
--- a/gcc/optabs.c
+++ b/gcc/optabs.c
@@ -1389,11 +1389,11 @@ static rtx
 avoid_expensive_constant (enum machine_mode mode, optab binoptab,
                          rtx x, bool unsignedp)
 {
+  bool speed = optimize_insn_for_speed_p ();
   if (mode != VOIDmode
       && optimize
       && CONSTANT_P (x)
-      && rtx_cost (x, binoptab->code, optimize_insn_for_speed_p ())
-                   > COSTS_N_INSNS (1))
+      && rtx_cost (x, binoptab->code, speed) > rtx_cost (x, SET, speed))
     {
       if (CONST_INT_P (x))
        {

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index a13e71208e5a3be4de3ea3b76d96319bbe1eee9a..6c7e19ce2b281d62045aed229bb95f14a18e41f2 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -2,7 +2,10 @@
 
        PR rtl-optimization/42258
        * gcc.target/arm/thumb1-mul-moves.c: New test.
-       
+
+       PR target/40697
+       * gcc.target/arm/thumb-andsi.c: New test.
+
 2010-03-19  Michael Matz  <matz@suse.de>
 
        PR c++/43116

diff --git a/gcc/testsuite/gcc.target/arm/thumb-andsi.c b/gcc/testsuite/gcc.target/arm/thumb-andsi.c
new file mode 100644 (file)
index 0000000..9e8e4d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/thumb-andsi.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -mthumb -march=armv5te" } */
+
+unsigned get_least_bits(unsigned value)
+{
+  return value << 9 >> 9;
+}
+
+/* { dg-final { scan-assembler "lsl" } } */
+/* { dg-final { scan-assembler "lsr" } } */