genoutput.c (validate_insn_operands): New.

        * genoutput.c (validate_insn_operands): New.
        (gen_insn): Call it.

        * config/alpha/alpha.md (divmodsi_internal): Renumber operands.
        (divmoddi_internal): Likewise.
        * config/arm/arm.md (andsi3_compare0_scratch): Likewise.
        * config/i960/i960.md (branch patterns): Likewise.
        * config/ia64/ia64.md (tbit_and_0): Likewise.
        (tbit_and_1, tbit_or_0, tbit_or_1): Likewise.
        * config/m68k/m68k.md (zero_extract memory patterns): Likewise.
        * config/mips/mips.md (divmodsi4_internal): Likewise.
        (divmoddi4_internal): Likewise.
        * config/rs6000/rs6000.md (call patterns): Likewise.
        * config/sh/sh.md (movsi_y): Likewise.
        * config/sparc/sparc.md: Comment out if 0 v8p shift pattern.

From-SVN: r37828

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9bae5dda07feb79bc1c823caadd0810e2a876787..18b1d1519e5d6cfe40a2a46b13e7d556931b3148 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,21 @@
+2000-11-28  Richard Henderson  <rth@redhat.com>
+
+       * genoutput.c (validate_insn_operands): New.
+       (gen_insn): Call it.
+
+       * config/alpha/alpha.md (divmodsi_internal): Renumber operands.
+       (divmoddi_internal): Likewise.
+       * config/arm/arm.md (andsi3_compare0_scratch): Likewise.
+       * config/i960/i960.md (branch patterns): Likewise.
+       * config/ia64/ia64.md (tbit_and_0): Likewise.
+       (tbit_and_1, tbit_or_0, tbit_or_1): Likewise.
+       * config/m68k/m68k.md (zero_extract memory patterns): Likewise.
+       * config/mips/mips.md (divmodsi4_internal): Likewise.
+       (divmoddi4_internal): Likewise.
+       * config/rs6000/rs6000.md (call patterns): Likewise.
+       * config/sh/sh.md (movsi_y): Likewise.
+       * config/sparc/sparc.md: Comment out if 0 v8p shift pattern.
+
 2000-11-28  Richard Henderson  <rth@redhat.com>
 
        * config.gcc: Kill residual pyramid support.

diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 028ce48739a2f1faed4889dfc1084a9a4ffe1350..b50d2671c250edd2acf38af357bdac3cf010f210 100644 (file)
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -986,23 +986,23 @@
 ;; expanded by the assembler.
 (define_insn "*divmodsi_internal"
   [(set (reg:DI 27)
-       (sign_extend:DI (match_operator:SI 1 "divmod_operator"
+       (sign_extend:DI (match_operator:SI 0 "divmod_operator"
                        [(reg:DI 24) (reg:DI 25)])))
    (clobber (reg:DI 23))
    (clobber (reg:DI 28))]
   "!TARGET_OPEN_VMS"
-  "%E1 $24,$25,$27"
+  "%E0 $24,$25,$27"
   [(set_attr "type" "jsr")
    (set_attr "length" "8")])
 
 (define_insn "*divmoddi_internal"
   [(set (reg:DI 27)
-       (match_operator:DI 1 "divmod_operator"
+       (match_operator:DI 0 "divmod_operator"
                        [(reg:DI 24) (reg:DI 25)]))
    (clobber (reg:DI 23))
    (clobber (reg:DI 28))]
   "!TARGET_OPEN_VMS"
-  "%E1 $24,$25,$27"
+  "%E0 $24,$25,$27"
   [(set_attr "type" "jsr")
    (set_attr "length" "8")])
 \f

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 15c2cd9df6f0f29fb6208f0646dbdf296c736848..dc99511132d75b0c636e5272a4fab1f77d269e85 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -1708,11 +1708,11 @@
         (and:SI (match_operand:SI 0 "s_register_operand" "r,r")
                 (match_operand:SI 1 "arm_not_operand" "rI,K"))
         (const_int 0)))
-   (clobber (match_scratch:SI 3 "=X,r"))]
+   (clobber (match_scratch:SI 2 "=X,r"))]
   "TARGET_ARM"
   "@
    tst%?\\t%0, %1
-   bic%?s\\t%3, %0, #%B1"
+   bic%?s\\t%2, %0, #%B1"
   [(set_attr "conds" "set")]
 )
 

diff --git a/gcc/config/i960/i960.md b/gcc/config/i960/i960.md
index 600865b4febae588c3fea2f53ae32ca60973afa6..5b423874749d27b1da045f867a791b3253a73b8d 100644 (file)
--- a/gcc/config/i960/i960.md
+++ b/gcc/config/i960/i960.md
@@ -164,53 +164,53 @@
 (define_insn ""
   [(set (pc)
        (if_then_else
-        (ne (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
+        (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "d")
                              (const_int 1)
-                             (match_operand:SI 2 "arith_operand" "dI"))
+                             (match_operand:SI 1 "arith_operand" "dI"))
             (const_int 0))
-        (label_ref (match_operand 3 "" ""))
+        (label_ref (match_operand 2 "" ""))
         (pc)))]
   ""
-  "bbs%+       %2,%1,%l3"
+  "bbs%+       %1,%0,%l2"
   [(set_attr "type" "branch")])
 
 (define_insn ""
   [(set (pc)
        (if_then_else
-        (eq (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
+        (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "d")
                              (const_int 1)
-                             (match_operand:SI 2 "arith_operand" "dI"))
+                             (match_operand:SI 1 "arith_operand" "dI"))
             (const_int 0))
-        (label_ref (match_operand 3 "" ""))
+        (label_ref (match_operand 2 "" ""))
         (pc)))]
   ""
-  "bbc%+       %2,%1,%l3"
+  "bbc%+       %1,%0,%l2"
   [(set_attr "type" "branch")])
 
 (define_insn ""
   [(set (pc)
        (if_then_else
-        (ne (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
+        (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
                              (const_int 1)
-                             (match_operand:SI 2 "arith_operand" "dI"))
+                             (match_operand:SI 1 "arith_operand" "dI"))
             (const_int 0))
-        (label_ref (match_operand 3 "" ""))
+        (label_ref (match_operand 2 "" ""))
         (pc)))]
   ""
-  "bbs%+       %2,%1,%l3"
+  "bbs%+       %1,%0,%l2"
   [(set_attr "type" "branch")])
 
 (define_insn ""
   [(set (pc)
        (if_then_else
-        (eq (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
+        (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
                              (const_int 1)
-                             (match_operand:SI 2 "arith_operand" "dI"))
+                             (match_operand:SI 1 "arith_operand" "dI"))
             (const_int 0))
-        (label_ref (match_operand 3 "" ""))
+        (label_ref (match_operand 2 "" ""))
         (pc)))]
   ""
-  "bbc%+       %2,%1,%l3"
+  "bbc%+       %1,%0,%l2"
   [(set_attr "type" "branch")])
 
 ;; ??? These will never match.  The LOG_LINKs necessary to make these match

diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 614fd38ecc3afee4f6b0df71f4fe6b16ea12e409..a79b879524025708a3dc2ad113f21796f7345718 100644 (file)
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -1662,7 +1662,7 @@
        (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
                               (const_int 1))
                       (const_int 0))
-               (match_operand:BI 3 "register_operand" "0")))]
+               (match_operand:BI 2 "register_operand" "0")))]
   ""
   "tbit.nz.and.orcm %0, %I0 = %1, 0"
   [(set_attr "itanium_class" "tbit")])
@@ -1672,7 +1672,7 @@
        (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
                               (const_int 1))
                       (const_int 0))
-               (match_operand:BI 3 "register_operand" "0")))]
+               (match_operand:BI 2 "register_operand" "0")))]
   ""
   "tbit.z.and.orcm %0, %I0 = %1, 0"
   [(set_attr "itanium_class" "tbit")])
@@ -1786,7 +1786,7 @@
        (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
                               (const_int 1))
                       (const_int 0))
-               (match_operand:BI 3 "register_operand" "0")))]
+               (match_operand:BI 2 "register_operand" "0")))]
   ""
   "tbit.nz.or.andcm %0, %I0 = %1, 0"
   [(set_attr "itanium_class" "tbit")])
@@ -1796,7 +1796,7 @@
        (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
                               (const_int 1))
                       (const_int 0))
-               (match_operand:BI 3 "register_operand" "0")))]
+               (match_operand:BI 2 "register_operand" "0")))]
   ""
   "tbit.z.or.andcm %0, %I0 = %1, 0"
   [(set_attr "itanium_class" "tbit")])

diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 4be439cf06f40478af1ec476cc1378b69c0f2286..75c552535c9381477c0405c86e0e66cf1cda6513 100644 (file)
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -5277,17 +5277,17 @@
 (define_insn ""
   [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
                         (const_int 32)
-                        (match_operand:SI 2 "const_int_operand" "n"))
-       (match_operand:SI 3 "general_src_operand" "rmSi"))]
+                        (match_operand:SI 1 "const_int_operand" "n"))
+       (match_operand:SI 2 "general_src_operand" "rmSi"))]
   "TARGET_68020 && TARGET_BITFIELD
-   && (INTVAL (operands[2]) % 8) == 0
+   && (INTVAL (operands[1]) % 8) == 0
    && ! mode_dependent_address_p (XEXP (operands[0], 0))"
   "*
 {
   operands[0]
-    = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
+    = adj_offsettable_operand (operands[0], INTVAL (operands[1]) / 8);
 
-  return \"move%.l %3,%0\";
+  return \"move%.l %2,%0\";
 }")
 
 (define_insn ""
@@ -5331,14 +5331,14 @@
   [(set (match_operand:SI 0 "general_operand" "=rm")
        (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
                         (const_int 32)
-                        (match_operand:SI 3 "const_int_operand" "n")))]
+                        (match_operand:SI 2 "const_int_operand" "n")))]
   "TARGET_68020 && TARGET_BITFIELD
-   && (INTVAL (operands[3]) % 8) == 0
+   && (INTVAL (operands[2]) % 8) == 0
    && ! mode_dependent_address_p (XEXP (operands[1], 0))"
   "*
 {
   operands[1]
-    = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
+    = adj_offsettable_operand (operands[1], INTVAL (operands[2]) / 8);
 
   return \"move%.l %1,%0\";
 }")
@@ -5385,14 +5385,14 @@
   [(set (match_operand:SI 0 "general_operand" "=rm")
        (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
                         (const_int 32)
-                        (match_operand:SI 3 "const_int_operand" "n")))]
+                        (match_operand:SI 2 "const_int_operand" "n")))]
   "TARGET_68020 && TARGET_BITFIELD
-   && (INTVAL (operands[3]) % 8) == 0
+   && (INTVAL (operands[2]) % 8) == 0
    && ! mode_dependent_address_p (XEXP (operands[1], 0))"
   "*
 {
   operands[1]
-    = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
+    = adj_offsettable_operand (operands[1], INTVAL (operands[2]) / 8);
 
   return \"move%.l %1,%0\";
 }")

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 06d4c3842b49e75d46e24e0eecf859dc23b4ba2e..a37464e569ff2eda162bef55fc3a95676c087da9 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -2291,7 +2291,7 @@
    (set (match_operand:SI 3 "register_operand" "=h")
        (mod:SI (match_dup 1)
                (match_dup 2)))
-   (clobber (match_scratch:SI 6 "=a"))]
+   (clobber (match_scratch:SI 4 "=a"))]
   "optimize"
   "div\\t$0,%1,%2"
   [(set_attr "type"    "idiv")
@@ -2338,7 +2338,7 @@
    (set (match_operand:DI 3 "register_operand" "=h")
        (mod:DI (match_dup 1)
                (match_dup 2)))
-   (clobber (match_scratch:DI 6 "=a"))]
+   (clobber (match_scratch:DI 4 "=a"))]
   "TARGET_64BIT && optimize"
   "ddiv\\t$0,%1,%2"
   [(set_attr "type"    "idiv")
@@ -2376,7 +2376,7 @@
    (set (match_operand:SI 3 "register_operand" "=h")
        (umod:SI (match_dup 1)
                 (match_dup 2)))
-   (clobber (match_scratch:SI 6 "=a"))]
+   (clobber (match_scratch:SI 4 "=a"))]
   "optimize"
   "divu\\t$0,%1,%2"
   [(set_attr "type"    "idiv")
@@ -2414,7 +2414,7 @@
    (set (match_operand:DI 3 "register_operand" "=h")
        (umod:DI (match_dup 1)
                 (match_dup 2)))
-   (clobber (match_scratch:DI 6 "=a"))]
+   (clobber (match_scratch:DI 4 "=a"))]
   "TARGET_64BIT && optimize"
   "ddivu\\t$0,%1,%2"
   [(set_attr "type"    "idiv")

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index e725f4318329cb890269fc90e31ad71fc2250300..54ecc5f1536d765f3b58d6cf743c380fa17cf9b9 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -9552,7 +9552,7 @@ operands[2] = GEN_INT (INTVAL (operands[1]) >> 32);
    (use (reg:SI 11))
    (set (reg:SI 2)
        (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
-   (clobber (match_scratch:SI 3 "=l"))]
+   (clobber (match_scratch:SI 2 "=l"))]
   "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
   "b%T0l\;{l|lwz} 2,20(1)"
   [(set_attr "type" "jmpreg")
@@ -9577,7 +9577,7 @@ operands[2] = GEN_INT (INTVAL (operands[1]) >> 32);
    (use (reg:DI 11))
    (set (reg:DI 2)
        (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
-   (clobber (match_scratch:SI 3 "=l"))]
+   (clobber (match_scratch:SI 2 "=l"))]
   "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
   "b%T0l\;ld 2,40(1)"
   [(set_attr "type" "jmpreg")
@@ -12568,7 +12568,7 @@ operands[2] = GEN_INT (INTVAL (operands[1]) >> 32);
   [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
        (compare:CCEQ (match_operator:SI 2 
                                      "branch_positive_comparison_operator"
-                                     [(match_operand 3
+                                     [(match_operand 1
                                                      "cc_reg_operand" "y")
                                       (const_int 0)])
                      (const_int 0)))]

diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index f71060473fc8bf11a198f3489212e5099fa50b86..de1f553a4a2186f6b0f92fe42d00ae0ed3368c28 100644 (file)
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -3172,7 +3172,7 @@
 (define_insn "*movsi_y"
   [(set (match_operand:SI 0 "register_operand" "=y,y")
        (match_operand:SI 1 "immediate_operand" "Qi,I"))
-   (clobber (match_scratch:SI 3 "=&z,r"))]
+   (clobber (match_scratch:SI 2 "=&z,r"))]
   "TARGET_SH3E
    && (reload_in_progress || reload_completed)"
   "#"

diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 21cf0a3bc8c38114a446665d0fcd70f73fd65d66..b15c39e4524de438dd0586cb8b06bf61695e2695 100644 (file)
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -8113,19 +8113,19 @@
 ;; Optimize (1LL<<x)-1
 ;; XXX this also needs to be fixed to handle equal subregs
 ;; XXX first before we could re-enable it.
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=h")
-       (plus:DI (ashift:DI (const_int 1)
-                           (match_operand:SI 2 "arith_operand" "rI"))
-                (const_int -1)))]
-  "0 && TARGET_V8PLUS"
-  "*
-{
-  if (GET_CODE (operands[2]) == REG && REGNO (operands[2]) == REGNO (operands[0]))
-    return \"mov\\t1, %L0\;sllx\\t%L0, %2, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\";
-  return \"mov\\t1, %H0\;sllx\\t%H0, %2, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\";
-}"
-  [(set_attr "length" "4")])
+;(define_insn ""
+;  [(set (match_operand:DI 0 "register_operand" "=h")
+;      (plus:DI (ashift:DI (const_int 1)
+;                          (match_operand:SI 1 "arith_operand" "rI"))
+;               (const_int -1)))]
+;  "0 && TARGET_V8PLUS"
+;  "*
+;{
+;  if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == REGNO (operands[0]))
+;    return \"mov\\t1, %L0\;sllx\\t%L0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\";
+;  return \"mov\\t1, %H0\;sllx\\t%H0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\";
+;}"
+;  [(set_attr "length" "4")])
 
 (define_insn "*cmp_cc_ashift_1"
   [(set (reg:CC_NOOV 100)

diff --git a/gcc/genoutput.c b/gcc/genoutput.c
index 57a9028aee833e30a8f3d5bf88bd01ab23154bc7..a5674c952794d7d7769a4d81b20474121b016290 100644 (file)
--- a/gcc/genoutput.c
+++ b/gcc/genoutput.c
@@ -182,6 +182,7 @@ static int compare_operands PARAMS ((struct operand_data *,
 static void place_operands PARAMS ((struct data *));
 static void process_template PARAMS ((struct data *, const char *));
 static void validate_insn_alternatives PARAMS ((struct data *));
+static void validate_insn_operands PARAMS ((struct data *));
 static void gen_insn PARAMS ((rtx, int));
 static void gen_peephole PARAMS ((rtx, int));
 static void gen_expand PARAMS ((rtx, int));
@@ -737,6 +738,22 @@ validate_insn_alternatives (d)
   /* Record the insn's overall number of alternatives.  */
   d->n_alternatives = n;
 }
+
+/* Verify that there are no gaps in operand numbers for INSNs.  */
+
+static void
+validate_insn_operands (d)
+     struct data *d;
+{
+  int i;
+
+  for (i = 0; i < d->n_operands; ++i)
+    if (d->operand[i].seen == 0)
+      {
+       message_with_line (d->lineno, "missing operand %d", i);
+       have_error = 1;
+      }
+}
 \f
 /* Look at a define_insn just read.  Assign its code number.  Record
    on idata the template and the number of arguments.  If the insn has
@@ -774,6 +791,7 @@ gen_insn (insn, lineno)
   d->n_operands = max_opno + 1;
   d->n_dups = num_dups;
 
+  validate_insn_operands (d);
   validate_insn_alternatives (d);
   place_operands (d);
   process_template (d, XSTR (insn, 3));