m32r.c (move_src_operand): Fix 32-bit int test.

        * config/m32r/m32r.c (move_src_operand): Fix 32-bit int test.
        * config/m32r/m32r.md (and ior xor splitters): Swap operands
        to match insn patterns.

From-SVN: r48679

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7df79a9748672ee7acf8a5df87172adaa91b7e32..65dc90f93cb98bcad2e77b21b7efeda3497516eb 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2002-01-09  Richard Henderson  <rth@redhat.com>
+
+       * config/m32r/m32r.c (move_src_operand): Fix 32-bit int test.
+       * config/m32r/m32r.md (and ior xor splitters): Swap operands
+       to match insn patterns.
+
 2002-01-09  Richard Henderson  <rth@redhat.com>
 
        * regrename.c (find_oldest_value_reg): Use gen_rtx_raw_REG.

diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c
index a3692c9af5c134852de4a2a8f179165106f3a559..9ae218e1d061ee0a99d1dbab9b3662d9f4a86acf 100644 (file)
--- a/gcc/config/m32r/m32r.c
+++ b/gcc/config/m32r/m32r.c
@@ -793,7 +793,13 @@ move_src_operand (op, mode)
         loadable with one insn, and split the rest into two.  The instances
         where this would help should be rare and the current way is
         simpler.  */
-      return UINT32_P (INTVAL (op));
+      if (HOST_BITS_PER_WIDE_INT > 32)
+       {
+         HOST_WIDE_INT rest = INTVAL (op) >> 31;
+         return (rest == 0 || rest == -1);
+       }
+      else
+       return 1;
     case LABEL_REF :
       return TARGET_ADDR24;
     case CONST_DOUBLE :

diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md
index 2d10057f0f3ade51dc95170b8c809fc7b3cc3cf6..a8e28db0ba987a9128ad5faff6f190b237e7fc07 100644 (file)
--- a/gcc/config/m32r/m32r.md
+++ b/gcc/config/m32r/m32r.md
@@ -1032,7 +1032,7 @@
                (match_operand:SI 2 "int8_operand" "")))]
   "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
   [(set (match_dup 0) (match_dup 2))
-   (set (match_dup 0) (and:SI (match_dup 1) (match_dup 0)))]
+   (set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))]
   "")
 
 (define_insn "iorsi3"
@@ -1064,7 +1064,7 @@
                (match_operand:SI 2 "int8_operand" "")))]
   "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
   [(set (match_dup 0) (match_dup 2))
-   (set (match_dup 0) (ior:SI (match_dup 1) (match_dup 0)))]
+   (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 1)))]
   "")
 
 (define_insn "xorsi3"
@@ -1096,7 +1096,7 @@
                (match_operand:SI 2 "int8_operand" "")))]
   "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
   [(set (match_dup 0) (match_dup 2))
-   (set (match_dup 0) (xor:SI (match_dup 1) (match_dup 0)))]
+   (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))]
   "")
 
 (define_insn "negsi2"