* config/i386/emmintrin.h: Fix comment typos.
* config/i386/i386.c: Likewise.
* config/i386/i386.h: Likewise.
* config/i386/sco5.h: Likewise.
* config/ia64/ia64.c: Likewise.
* config/ia64/itanium2.md: Likewise.
From-SVN: r68857
+2003-07-02 Kazu Hirata <kazu@cs.umass.edu>
+
+ * config/i386/emmintrin.h: Fix comment typos.
+ * config/i386/i386.c: Likewise.
+ * config/i386/i386.h: Likewise.
+ * config/i386/sco5.h: Likewise.
+ * config/ia64/ia64.c: Likewise.
+ * config/ia64/itanium2.md: Likewise.
+
2003-07-02 H.J. Lu <hongjiu.lu@intel.com>
* dbxout.c (pending_bincls): Replace DBX_USE_BINCLS with
__builtin_ia32_storesd (__P, (__v2df)__A);
}
-/* Store the lower DPFP value acrosd two words. */
+/* Store the lower DPFP value across two words. */
static __inline void
_mm_store1_pd (double *__P, __m128d __A)
{
if (AGGREGATE_TYPE_P (type))
{
- /* Walk the agregates recursivly. */
+ /* Walk the agregates recursively. */
if (TREE_CODE (type) == RECORD_TYPE
|| TREE_CODE (type) == UNION_TYPE
|| TREE_CODE (type) == QUAL_UNION_TYPE)
code = swap_condition (code);
}
- /* Try to expand the comparsion and verify that we end up with carry flag
- based comparsion. This is fails to be true only when we decide to expand
- comparsion using arithmetic that is not too common scenario. */
+ /* Try to expand the comparison and verify that we end up with carry flag
+ based comparison. This is fails to be true only when we decide to expand
+ comparison using arithmetic that is not too common scenario. */
start_sequence ();
compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
&second_test, &bypass_test);
floating unit pipeline preparation stages, the memory operands
for floating point are cheaper.
- ??? For Athlon it the difference is most propbably 2. */
+ ??? For Athlon it the difference is most probably 2. */
if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
loadcost = 3;
else
/* We don't have exact information about the insn sizes, but we may assume
quite safely that we are informed about all 1 byte insns and memory
- address sizes. This is enought to elliminate unnecesary padding in
+ address sizes. This is enough to eliminate unnecessary padding in
99% of cases. */
static int
return 2;
}
-/* AMD K8 core misspredicts jumps when there are more than 3 jumps in 16 byte
+/* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
window. */
static void
&& ((GET_CODE (prev) == JUMP_INSN && any_condjump_p (prev))
|| GET_CODE (prev) == CALL_INSN))
replace = true;
- /* Empty functions get branch misspredict even when the jump destination
+ /* Empty functions get branch mispredict even when the jump destination
is not visible to us. */
if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
replace = true;
#define RETURN_IN_MEMORY(TYPE) \
ix86_return_in_memory (TYPE)
-/* This is overriden by <cygwin.h>. */
+/* This is overridden by <cygwin.h>. */
#define MS_AGGREGATE_RETURN 0
\f
* Here's the reason why. If we dont define them, and we dont define them
* to always emit to the same section, the default is to emit to "named"
* ctors and dtors sections. This would be great if we could use GNU ld,
- * but we can't. The native linker could possibly be trained to coallesce
+ * but we can't. The native linker could possibly be trained to coalesce
* named ctors sections, but that hasn't been done either. So if we don't
* define these, many C++ ctors and dtors dont get run, because they never
* wind up in the ctors/dtors arrays.
break;
case FR_REGS:
- /* Need to go through general regsters to get to other class regs. */
+ /* Need to go through general registers to get to other class regs. */
if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
return GR_REGS;
(define_reservation "2_M_only_um01" "2_M0_only_um01|2_M1_only_um01")
;; I instruction is dispersed to the lowest numbered I unit
-;; not already in use. Remeber about possible spliting.
+;; not already in use. Remeber about possible splitting.
(define_reservation "2_I0"
"2_0mi.i+2_ui0|2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0\
|2_0mfi.+2_ui0|2_0mi.b+2_ui0|(2_1mi.i|2_1mi.b)+(2_ui0|2_ui1)\
+(2b_um2|2b_um3)")
;; I instruction is dispersed to the lowest numbered I unit
-;; not already in use. Remeber about possible spliting.
+;; not already in use. Remeber about possible splitting.
(define_reservation "2b_I"
"2b_0mi.i+2_2+2b_ui0|2b_0mii.+2_3+(2b_ui0|2b_ui1)|2b_0mmi.+2_3+2b_ui0\
|2b_0mfi.+2_3+2b_ui0|2b_0mi.b+2_2+2b_ui0\