riscv: riscv-cores.def: Add T-Head XuanTie C906

This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906".
The C906 is shipped for quite some time (it is the core of the Allwinner D1).
Note, that the tuning struct for the C906 is already part of GCC (it is
also name "thead-c906").

gcc/ChangeLog:

	* config/riscv/riscv-cores.def (RISCV_CORE): Add "thead-c906".

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/mcpu-thead-c906.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 2a834cae21db6bb0a8189b33e9493c2f58ac19e0..7d87ab7ce28f045f659b58d30ca339c54f4a7830 100644 (file)
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -73,4 +73,8 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
 RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
 RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
 
+RISCV_CORE("thead-c906",      "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
+                             "xtheadcondmov_xtheadfmemidx_xtheadmac_"
+                             "xtheadmemidx_xtheadmempair_xtheadsync",
+                             "thead-c906")
 #undef RISCV_CORE

diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c
new file mode 100644 (file)
index 0000000..a71b43a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=thead-c906" { target { rv64 } } } */
+/* T-Head XuanTie C906 => rv64imafdc */
+
+#if !((__riscv_xlen == 64)             \
+      && !defined(__riscv_32e)         \
+      && defined(__riscv_mul)          \
+      && defined(__riscv_atomic)       \
+      && (__riscv_flen == 64)          \
+      && defined(__riscv_compressed)   \
+      && defined(__riscv_xtheadba)     \
+      && defined(__riscv_xtheadbb)     \
+      && defined(__riscv_xtheadbs)     \
+      && defined(__riscv_xtheadcmo)    \
+      && defined(__riscv_xtheadcondmov)        \
+      && defined(__riscv_xtheadfmemidx)        \
+      && defined(__riscv_xtheadmac)    \
+      && defined(__riscv_xtheadmemidx) \
+      && defined(__riscv_xtheadmempair)        \
+      && defined(__riscv_xtheadsync))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+  return 0;
+}