]> gcc.gnu.org Git - gcc.git/commitdiff
arc: Update (u)maddhisi4 patterns
authorClaudiu Zissulescu <claziss@synopsys.com>
Tue, 16 Nov 2021 10:07:02 +0000 (12:07 +0200)
committerClaudiu Zissulescu <claziss@synopsys.com>
Tue, 16 Nov 2021 10:34:59 +0000 (12:34 +0200)
The (u)maddsihi4 patterns are using the ARC's VMAC2H(U)
instruction with null destination, however, VMAC2H(U) doesn't
rewrite the accumulator.  This patch solves the destination issue
of VMAC2H by replacing it with DMACH(U) instruction.

gcc/

* config/arc/arc.md (maddhisi4): Use a single move to accumulator.
(umaddhisi4): Likewise.
(machi): Update pattern.
(umachi): Likewise.

gcc/testsuite/

* gcc.target/arc/tmac-4.c: New test.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
gcc/config/arc/arc.md
gcc/testsuite/gcc.target/arc/tmac-4.c [new file with mode: 0644]

index 4919d275820712b201db725ba70c32cf8cfd2579..74ec38f1526a50a69082ffafd5ae1f76d13dfea2 100644 (file)
@@ -6023,26 +6023,26 @@ core_3, archs4x, archs4xd, archs4xd_slow"
 (define_expand "maddhisi4"
   [(match_operand:SI 0 "register_operand" "")
    (match_operand:HI 1 "register_operand" "")
-   (match_operand:HI 2 "extend_operand"   "")
+   (match_operand:HI 2 "register_operand" "")
    (match_operand:SI 3 "register_operand" "")]
   "TARGET_PLUS_MACD"
   "{
-   rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
+   rtx acc_reg = gen_rtx_REG (SImode, ACCL_REGNO);
 
    emit_move_insn (acc_reg, operands[3]);
-   emit_insn (gen_machi (operands[1], operands[2]));
-   emit_move_insn (operands[0], acc_reg);
+   emit_insn (gen_machi (operands[0], operands[1], operands[2], acc_reg));
    DONE;
   }")
 
 (define_insn "machi"
-  [(set (reg:SI ARCV2_ACC)
+  [(set (match_operand:SI 0 "register_operand" "=Ral,r")
        (plus:SI
-        (mult:SI (sign_extend:SI (match_operand:HI 0 "register_operand" "%r"))
-                 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))
-        (reg:SI ARCV2_ACC)))]
+        (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r,r"))
+                 (sign_extend:SI (match_operand:HI 2 "register_operand" "r,r")))
+        (match_operand:SI 3 "accl_operand" "")))
+   (clobber (reg:DI ARCV2_ACC))]
   "TARGET_PLUS_MACD"
-  "vmac2h\\t0,%0,%1"
+  "dmach\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "no")
@@ -6056,22 +6056,22 @@ core_3, archs4x, archs4xd, archs4xd_slow"
    (match_operand:SI 3 "register_operand" "")]
   "TARGET_PLUS_MACD"
   "{
-   rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
+   rtx acc_reg = gen_rtx_REG (SImode, ACCL_REGNO);
 
    emit_move_insn (acc_reg, operands[3]);
-   emit_insn (gen_umachi (operands[1], operands[2]));
-   emit_move_insn (operands[0], acc_reg);
+   emit_insn (gen_umachi (operands[0], operands[1], operands[2], acc_reg));
    DONE;
   }")
 
 (define_insn "umachi"
-  [(set (reg:SI ARCV2_ACC)
+  [(set (match_operand:SI 0 "register_operand" "=Ral,r")
        (plus:SI
-        (mult:SI (zero_extend:SI (match_operand:HI 0 "register_operand" "%r"))
-                 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
-        (reg:SI ARCV2_ACC)))]
+        (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%r,r"))
+                 (zero_extend:SI (match_operand:HI 2 "register_operand" "r,r")))
+        (match_operand:SI 3 "accl_operand" "")))
+   (clobber (reg:DI ARCV2_ACC))]
   "TARGET_PLUS_MACD"
-  "vmac2hu\\t0,%0,%1"
+  "dmachu\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "no")
diff --git a/gcc/testsuite/gcc.target/arc/tmac-4.c b/gcc/testsuite/gcc.target/arc/tmac-4.c
new file mode 100644 (file)
index 0000000..3c6b993
--- /dev/null
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
+/* { dg-options "-O3 -mbig-endian -mcpu=hs38" } */
+
+struct a {};
+struct b {
+  int c;
+  int d;
+};
+
+struct {
+  struct a e;
+  struct b f[];
+} g;
+short h;
+
+extern void bar (int *);
+
+int foo(void)
+{
+  struct b *a;
+  for (;;)
+    {
+      a = &g.f[h];
+      bar(&a->d);
+    }
+}
+
+/* { dg-final { scan-assembler "dmach" } } */
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