Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1323e27d33b62a866875cb58a7b7c127540c2617..cb36d8b7f68e4c7903e64f100b3c2b9254fac45e 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,238 @@
+2022-11-28  Andrew Pinski  <apinski@marvell.com>
+
+       * match.pd ((A / (1 << B)) -> (A >> B).):
+       Fix comment.
+
+2022-11-28  Sinan  <sinan.lin@linux.alibaba.com>
+
+       * config/riscv/riscv.cc (riscv_build_integer): Improve some cases
+       of loading 64bit constants for rv32.
+
+2022-11-28  Maciej W. Rozycki  <macro@embecosm.com>
+
+       * config/riscv/riscv.cc (riscv_emit_int_order_test): Use EQ 0
+       rather that XOR 1 for LE and LEU operations.
+
+2022-11-28  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/107896
+       * tree-vect-stmts.cc (supportable_widening_operation):
+       Handle non-vector mode intermediate mode.
+
+2022-11-28  Frolov Daniil  <frolov.da@phystech.edu>
+
+       * gimple-ssa-sprintf.cc (fmtresult::type_max_digits): Handle
+       base == 2.
+       (tree_digits): Likewise.
+       (format_integer): Likewise.
+       (parse_directive): Add cases for %b and %B directives.
+
+2022-11-28  Fei Gao  <gaofei@eswincomputing.com>
+
+       * config/riscv/riscv.cc (riscv_first_stack_step): Fix computation
+       of MIN_FIRST_STEP to cover FP save area too.
+
+2022-11-28  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/107493
+       * tree-scalar-evolution.cc (scev_dfs::follow_ssa_edge_expr):
+       Only handle no-op and sign-changing conversions.
+
+2022-11-28  Tobias Burnus  <tobias@codesourcery.com>
+
+       * config/gcn/gcn.cc (gcn_expand_builtin_1): Work on s1 instead
+       of s[0:1] and use USE to prevent removal of setting that register.
+       * config/gcn/gcn.md (prologue_use_di): Remove.
+
+2022-11-28  Yuri Gribov  <y.gribov@samsung.com>
+
+       PR sanitizer/106558
+       * sanopt.cc: Do not optimize out checks for non-SSA addresses.
+
+2022-11-28  Jakub Jelinek  <jakub@redhat.com>
+
+       PR target/106875
+       * config/i386/i386.opt (x_ix86_abi): Remove TargetSave.
+       (ix86_abi): Replace it with TargetVariable.
+       * config/i386/i386-options.cc (ix86_function_specific_save,
+       ix86_function_specific_restore): Don't save and restore x_ix86_abi.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * config/arm/mve.md (mve_vrmlaldavhq_<supf>v4si,
+       mve_vrmlaldavhaq_<supf>v4si): Fix spacing vs tabs.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * config/arm/mve.md (mve_vmlaldavaq_<supf><mode>)
+       (mve_vmlaldavaxq_s<mode>, mve_vmlaldavaxq_p_<supf><mode>): Fix
+       spacing vs tabs.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * config/arm/mve.md (mve_vsubq_n_f<mode>): Fix spacing.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * config/arm/mve.md (mve_vaddlvq_p_<supf>v4si)
+       (mve_vaddq_n_<supf><mode>, mve_vaddvaq_<supf><mode>)
+       (mve_vaddlvaq_<supf>v4si, mve_vaddq_n_f<mode>)
+       (mve_vaddlvaq_p_<supf>v4si, mve_vaddq<mode>, mve_vaddq_f<mode>):
+       Fix spacing.
+
+2022-11-28  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+       * config/arm/arm_mve.h (__arm_vsubq_x FP): New overloads.
+       (__arm_vsubq_x Integer): New.
+
+2022-11-28  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+       PR target/107515
+       * config/arm/arm_mve.h (__ARM_mve_typeid): Add float types.
+
+2022-11-28  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+       PR target/96795
+       * config/arm/arm_mve.h (__arm_vaddq): Fix Overloading.
+       (__arm_vmulq): Likewise.
+       (__arm_vcmpeqq): Likewise.
+       (__arm_vcmpneq): Likewise.
+       (__arm_vmaxnmavq): Likewise.
+       (__arm_vmaxnmvq): Likewise.
+       (__arm_vminnmavq): Likewise.
+       (__arm_vsubq): Likewise.
+       (__arm_vminnmvq): Likewise.
+       (__arm_vrshlq): Likewise.
+       (__arm_vqsubq): Likewise.
+       (__arm_vqdmulltq): Likewise.
+       (__arm_vqdmullbq): Likewise.
+       (__arm_vqdmulhq): Likewise.
+       (__arm_vqaddq): Likewise.
+       (__arm_vhaddq): Likewise.
+       (__arm_vhsubq): Likewise.
+       (__arm_vqdmlashq): Likewise.
+       (__arm_vqrdmlahq): Likewise.
+       (__arm_vmlasq): Likewise.
+       (__arm_vqdmlahq): Likewise.
+       (__arm_vmaxnmavq_p): Likewise.
+       (__arm_vmaxnmvq_p): Likewise.
+       (__arm_vminnmavq_p): Likewise.
+       (__arm_vminnmvq_p): Likewise.
+       (__arm_vfmasq_m): Likewise.
+       (__arm_vsetq_lane): Likewise.
+       (__arm_vcmpneq_m): Likewise.
+       (__arm_vhaddq_x): Likewise.
+       (__arm_vhsubq_x): Likewise.
+       (__arm_vqrdmlashq_m): Likewise.
+       (__arm_vqdmlashq_m): Likewise.
+       (__arm_vmlaldavaxq_p): Likewise.
+       (__arm_vmlasq_m): Likewise.
+       (__arm_vqdmulhq_m): Likewise.
+       (__arm_vqdmulltq_m): Likewise.
+       (__arm_viwdupq_m): Likewise.
+       (__arm_viwdupq_u16): Likewise.
+       (__arm_viwdupq_u32): Likewise.
+       (__arm_viwdupq_u8): Likewise.
+       (__arm_vdwdupq_m): Likewise.
+       (__arm_vdwdupq_u16): Likewise.
+       (__arm_vdwdupq_u32): Likewise.
+       (__arm_vdwdupq_u8): Likewise.
+       (__arm_vaddlvaq): Likewise.
+       (__arm_vaddlvaq_p): Likewise.
+       (__arm_vaddvaq): Likewise.
+       (__arm_vaddvaq_p): Likewise.
+       (__arm_vcmphiq_m): Likewise.
+       (__arm_vmladavaq_p): Likewise.
+       (__arm_vmladavaxq): Likewise.
+       (__arm_vmlaldavaxq): Likewise.
+       (__arm_vrmlaldavhaq_p): Likewise.
+
+2022-11-28  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+       PR target/96795
+       * config/arm/arm_mve.h (__arm_vaddq_m_n_s8): Change types.
+       (__arm_vaddq_m_n_s32): Likewise.
+       (__arm_vaddq_m_n_s16): Likewise.
+       (__arm_vaddq_m_n_u8): Likewise.
+       (__arm_vaddq_m_n_u32): Likewise.
+       (__arm_vaddq_m_n_u16): Likewise.
+       (__arm_vaddq_m): Fix Overloading.
+       (__ARM_mve_coerce3): New.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * config/arm/mve.md (mve_vabsq_f<mode>): Fix spacing.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * config/arm/mve.md (@mve_vcmp<mve_cmp_op>q_<mode>): Fix
+       spacing.
+       * config/arm/arm_mve.h (__arm_vcmpgtq_m, __arm_vcmpleq_m)
+       (__arm_vcmpltq_m, __arm_vcmpneq_m): Add missing defines.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * config/arm/mve.md (mve_vdupq_n_f<mode>)
+       (mve_vdupq_n_<supf><mode>, mve_vdupq_m_n_<supf><mode>)
+       (mve_vdupq_m_n_f<mode>): Fix spacing.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * config/arm/mve.md (mve_vdwdupq_m_wb_u<mode>_insn): Fix spacing.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * config/arm/mve.md (mve_vddupq_u<mode>_insn): Fix 'vddup.u'
+       spacing.
+       (mve_vddupq_m_wb_u<mode>_insn): Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * config/arm/vfp.md (*thumb2_movhi_vfp, *thumb2_movhi_fp16): Fix
+       'vmsr' spacing and reg capitalization.
+
+2022-11-28  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/107876
+       * tree-ssa-loop-unswitch.cc (clean_up_after_unswitching): Wipe
+       dominator info if we removed an edge.
+
+2022-11-28  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/107867
+       * tree-ssa-forwprop.cc (pass_forwprop::execute): Handle
+       abnormal cleanup after substitution.
+
+2022-11-28  Lulu Cheng  <chenglulu@loongson.cn>
+
+       * config/loongarch/loongarch.cc (enum loongarch_load_imm_method):
+       Remove the member METHOD_INSV that is not currently used.
+       (struct loongarch_integer_op): Define a new member curr_value,
+       that records the value of the number stored in the destination
+       register immediately after the current instruction has run.
+       (loongarch_build_integer): Assign a value to the curr_value member variable.
+       (loongarch_move_integer): Adds information for the immediate load instruction.
+       * config/loongarch/loongarch.md (*movdi_32bit): Redefine as define_insn_and_split.
+       (*movdi_64bit): Likewise.
+       (*movsi_internal): Likewise.
+       (*movhi_internal): Likewise.
+       * config/loongarch/predicates.md: Return true as long as it is CONST_INT, ensure
+       that the immediate number is not optimized by decomposition during expand
+       optimization loop.
+
+2022-11-28  liuhongt  <hongtao.liu@intel.com>
+
+       PR target/107748
+       * config/i386/avx512bf16intrin.h (_mm_cvtsbh_ss): Refined.
+       * config/i386/i386-builtin-types.def (FLOAT_FTYPE_BFLOAT16):
+       New function type.
+       * config/i386/i386-builtin.def (BDESC): New builtin.
+       * config/i386/i386-expand.cc (ix86_expand_args_builtin):
+       Handle the builtin.
+       * config/i386/i386.md (extendbfsf2): New expander.
+       (extendbfsf2_1): New define_insn.
+       (truncsfbf2): Ditto.
+
 2022-11-26  Andrew Pinski  <apinski@marvell.com>
 
        PR tree-optimization/103356

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index bca26078d6eb48fb1b94b04f7deae3cc2f2f5cb9..7063790611d6f803b6a1ea16bb56ddf5433e999c 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20221128
+20221129

diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog
index 34a26957249472dd0449343c41ec9c77a55b6409..00b37566a423d4c45df83c73ef743a6d09d04dc3 100644 (file)
--- a/gcc/ada/ChangeLog
+++ b/gcc/ada/ChangeLog
@@ -1,3 +1,49 @@
+2022-11-28  Eric Botcazou  <ebotcazou@adacore.com>
+
+       * libgnat/g-traceb.ads: Minor tweaks in the commentary.
+       (Executable_Load_Address): New function.
+       * doc/gnat_ugn/gnat_and_program_execution.rst (Non-Symbolic
+       Traceback): Adjust to PIE default on Linux.
+       (Symbolic Traceback): Likewise.
+       * doc/gnat_ugn/gnat_utility_programs.rst (gnatsymbolize): Likewise.
+       * gnat_ugn.texi: Regenerate.
+
+2022-11-28  Joel Brobecker  <brobecker@adacore.com>
+
+       * doc/share/conf.py (extensions): Add 'sphinx_rtd_theme'.
+       (html_theme): Set to 'sphinx_rtd_theme'.
+
+2022-11-28  Claire Dross  <dross@adacore.com>
+
+       * libgnat/g-souinf.ads (Source_Code_Information): Add a new
+       volatile abstract state and add it in the global contract of all
+       functions defined in Source_Info.
+
+2022-11-28  Eric Botcazou  <ebotcazou@adacore.com>
+
+       * exp_ch6.adb (Expand_Actuals.Add_Call_By_Copy_Code): Deal with a
+       reference to a validation variable in the actual.
+       (Expand_Actuals.Add_Validation_Call_By_Copy_Code): Minor tweak.
+       (Expand_Actuals): Call Add_Validation_Call_By_Copy_Code directly
+       only if Add_Call_By_Copy_Code is not to be invoked.
+
+2022-11-28  Eric Botcazou  <ebotcazou@adacore.com>
+
+       * adaint.c [Linux]: Include <link.h>.
+       (__gnat_get_executable_load_address) [Linux]: Enable.
+
+2022-11-28  Yannick Moy  <moy@adacore.com>
+
+       * sem_prag.adb (Check_Part_Of_Abstract_State): Add verification
+       related to use of Part_Of, so that constituents in private childs
+       that refer to state in a sibling or parent unit force that unit to
+       have a body.
+       * sem_util.adb (Check_State_Refinements): Drop the requirement to
+       have always a package body for state refinement, when the package
+       state is mentioned in no Part_Of specification.
+       * sem_ch3.adb (Analyze_Declarations): Refresh SPARK refs in comment.
+       * sem_ch7.adb (Analyze_Package_Declaration): Likewise.
+
 2022-11-24  Eric Botcazou  <ebotcazou@adacore.com>
 
        * gcc-interface/trans.cc (gnat_to_gnu) <N_Assignment_Statement>: Add

diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index a8c08ca48a830a973cf7f4158ea179c09b2a3c2f..8dbaede4f224c1668486fb5cdef7ec7e5cb522c5 100644 (file)
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,20 @@
+2022-11-28  Jason Merrill  <jason@redhat.com>
+
+       PR c++/101733
+       * parser.cc (cp_parser_requirement): Parse tentatively for the
+       'typename' case.
+
+2022-11-28  Jason Merrill  <jason@redhat.com>
+
+       * parser.cc (cp_parser_decl_specifier_seq): Change 'concept bool'
+       diagnostic from pedwarn to permerror.
+
+2022-11-28  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+           Yvan ROUX  <yvan.roux@foss.st.com>
+
+       * module.cc: On Windows, 'A:Foo' is supposed to be a module
+       and not a path.
+
 2022-11-22  Jason Merrill  <jason@redhat.com>
 
        PR c++/107781

diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 069f2e52e854ec53059a614907a95f3b1ec14d27..ba7c04811beca4a13832046e8cf00bafcc760ac6 100644 (file)
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,29 @@
+2022-11-28  Harald Anlauf  <anlauf@gmx.de>
+
+       PR fortran/107819
+       * trans-stmt.cc (gfc_conv_elemental_dependencies): In checking for
+       elemental dependencies, treat dummy argument with VALUE attribute
+       as implicitly having intent(in).
+
+2022-11-28  Tobias Burnus  <tobias@codesourcery.com>
+
+       * openmp.cc (OMP_DO_CLAUSES, OMP_SCOPE_CLAUSES,
+       OMP_SECTIONS_CLAUSES): Add 'nowait'.
+       (OMP_SINGLE_CLAUSES): Add 'nowait' and 'copyprivate'.
+       (gfc_match_omp_distribute_parallel_do,
+       gfc_match_omp_distribute_parallel_do_simd,
+       gfc_match_omp_parallel_do,
+       gfc_match_omp_parallel_do_simd,
+       gfc_match_omp_parallel_sections,
+       gfc_match_omp_teams_distribute_parallel_do,
+       gfc_match_omp_teams_distribute_parallel_do_simd): Disallow 'nowait'.
+       (gfc_match_omp_workshare): Match 'nowait' clause.
+       (gfc_match_omp_end_single): Use clause matcher for 'nowait'.
+       (resolve_omp_clauses): Reject 'nowait' + 'copyprivate'.
+       * parse.cc (decode_omp_directive): Break too long line.
+       (parse_omp_do, parse_omp_structured_block): Diagnose duplicated
+       'nowait' clause.
+
 2022-11-23  Steve Kargl  <kargl@gcc.gnu.org>
 
        PR fortran/107577

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 09fa78ada2daed70474699127ff33766359c8719..850b32d9d7a59b28a1d6f409bf66d99fec257bba 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,1042 @@
+2022-11-28  Jason Merrill  <jason@redhat.com>
+
+       PR c++/101733
+       * g++.dg/cpp2a/concepts-requires32.C: New test.
+
+2022-11-28  Sinan  <sinan.lin@linux.alibaba.com>
+
+       * gcc.target/riscv/rv32-load-64bit-constant.c: New test.
+
+2022-11-28  Maciej W. Rozycki  <macro@embecosm.com>
+
+       * gcc.target/riscv/sge.c: New test.
+       * gcc.target/riscv/sgeu.c: New test.
+       * gcc.target/riscv/sle.c: New test.
+       * gcc.target/riscv/sleu.c: New test.
+
+2022-11-28  Harald Anlauf  <anlauf@gmx.de>
+
+       PR fortran/107819
+       * gfortran.dg/elemental_dependency_7.f90: New test.
+
+2022-11-28  Frolov Daniil  <frolov.da@phystech.edu>
+
+       * gcc.dg/Wformat-overflow1.c: New test.
+
+2022-11-28  Fei Gao  <gaofei@eswincomputing.com>
+
+       * gcc.target/riscv/pr93304.c: Adapt testcase for the change, constrain
+       match to assembly instructions only.
+       * gcc.target/riscv/rvv/base/spill-11.c: Adapt testcase for the change.
+       * gcc.target/riscv/stack_frame.c: New test.
+
+2022-11-28  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/107493
+       * gcc.dg/torture/pr107493.c: New testcase.
+
+2022-11-28  Tobias Burnus  <tobias@codesourcery.com>
+
+       * gfortran.dg/gomp/copyprivate-1.f90: New test.
+       * gfortran.dg/gomp/copyprivate-2.f90: New test.
+       * gfortran.dg/gomp/nowait-2.f90: Move dg-error tests ...
+       * gfortran.dg/gomp/nowait-4.f90: ... to this new file.
+       * gfortran.dg/gomp/nowait-5.f90: New test.
+       * gfortran.dg/gomp/nowait-6.f90: New test.
+       * gfortran.dg/gomp/nowait-7.f90: New test.
+       * gfortran.dg/gomp/nowait-8.f90: New test.
+
+2022-11-28  Yuri Gribov  <y.gribov@samsung.com>
+
+       PR sanitizer/106558
+       * c-c++-common/asan/pr106558.c: New test.
+
+2022-11-28  Jakub Jelinek  <jakub@redhat.com>
+
+       PR target/106875
+       * g++.target/i386/pr106875.C: New test.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c: Improve tests.
+       * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_s16.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_s32.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_s8.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_u16.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_u32.c:
+       * gcc.target/arm/mve/intrinsics/vqsubq_u8.c:
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c:
+       * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c:
+       * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c:
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Improve tests.
+       * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vqaddq_u8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Improve tests.
+       * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c: Improve tests.
+       * gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c: Improve tests.
+       * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vsubq_f16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_m_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_x_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_x_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_x_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_x_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_x_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_x_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_x_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsubq_x_u8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vmulq_f16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vmulq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_m_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_m_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_m_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_m_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_m_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_x_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_x_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_x_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_x_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_x_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_x_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_x_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmulq_x_u8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddlvq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddlvq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_m_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_m_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_m_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_m_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_m_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_x_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_x_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_x_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_x_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_x_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_x_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_x_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddq_x_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvaq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvaq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvaq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvaq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvaq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvaq_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vaddvq_u8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vabsq_f16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabsq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabsq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabsq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabsq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabsq_x_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabsq_x_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabsq_x_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabsq_x_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabsq_x_s8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vabdq_f16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_m_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_m_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_m_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_m_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_m_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_x_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_x_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_x_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_x_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_x_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_x_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_x_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabdq_x_u8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabavq_p_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabavq_p_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabavq_p_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabavq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabavq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabavq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabavq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabavq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vabavq_u8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxaq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxaq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxaq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxavq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxavq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxavq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxq_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_u8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminaq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminaq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminaq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminavq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminavq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminavq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmaq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmaq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminq_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminq_x_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminq_x_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminq_x_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminq_x_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminq_x_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminq_x_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_u8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmphiq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmphiq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmphiq_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpleq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpltq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcmpneq_u8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c: Improve tests.
+       * gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vidupq_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vidupq_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vidupq_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c: Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c : Improve test.
+       * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c : Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vddupq_n_u16.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vddupq_n_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vddupq_n_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c : Likewise.
+       * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c : Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c:
+       Update test.
+       * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c:
+       Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c:
+       Likewise.
+
+2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Improve test.
+       * gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcreateq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Likewise.
+
+2022-11-28  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/107876
+       * g++.dg/tree-ssa/pr107876.C: New testcase.
+
+2022-11-28  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/107867
+       * g++.dg/pr107867.C: New testcase.
+
+2022-11-28  Lulu Cheng  <chenglulu@loongson.cn>
+
+       * gcc.target/loongarch/imm-load.c: New test.
+       * gcc.target/loongarch/imm-load1.c: New test.
+
+2022-11-28  liuhongt  <hongtao.liu@intel.com>
+
+       * gcc.target/i386/avx512bf16-cvtsbh2ss-1.c: Scan pslld.
+       * gcc.target/i386/extendbfsf.c: New test.
+
 2022-11-26  Andrew Pinski  <apinski@marvell.com>
 
        PR tree-optimization/103356

diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog
index afb0fad9b2fe2c15f022b20b7f944c7dd3e4c192..f29085ad6dc7e485614e18d1cc00b7e921eba7fe 100644 (file)
--- a/libgomp/ChangeLog
+++ b/libgomp/ChangeLog
@@ -1,3 +1,7 @@
+2022-11-28  Tobias Burnus  <tobias@codesourcery.com>
+
+       * libgomp.texi (OpenMP 5.2): Mark end-directive as Y.
+
 2022-11-25  Sandra Loosemore  <sandra@codesourcery.com>
 
        * testsuite/lib/libgomp.exp: Load scanoffloadipa.exp library.

diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 6e776d412c2d5863ac0a1683b43b265eafcc70e8..9937419a56eb9a00c9bacdd9f040eddcb7458c91 100644 (file)
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,52 @@
+2022-11-28  François Dumont  <fdumont@gcc.gnu.org>
+
+       * testsuite/20_util/function/cons/70692.cc: Adapt dg-error message.
+
+2022-11-28  Jonathan Wakely  <jwakely@redhat.com>
+
+       PR libstdc++/107801
+       * src/c++17/memory_resource.cc (chunk::_M_bytes): Change type
+       from uint32_t to bitset::size_type. Adjust static assertion.
+       (__pool_resource::_Pool::replenish): Cast to size_t after
+       multiplication instead of before.
+       (__pool_resource::_M_alloc_pools): Ensure both arguments to
+       std::max have type size_t.
+
+2022-11-28  Jonathan Wakely  <jwakely@redhat.com>
+
+       * include/std/string_view (basic_string_view::copy) Use explicit
+       template argument for call to std::min<size_t>.
+       (basic_string_view::substr): Likewise.
+
+2022-11-28  Jonathan Wakely  <jwakely@redhat.com>
+
+       PR libstdc++/107885
+       * libsupc++/hash_bytes.cc (_Hash_bytes): Convert to size_t
+       instead of implicit integer promotion to 16 bits.
+
+2022-11-28  Jonathan Wakely  <jwakely@redhat.com>
+
+       * testsuite/26_numerics/random/subtract_with_carry_engine/cons/lwg3809.cc:
+       Replace non-ASCII character.
+
+2022-11-28  Jonathan Wakely  <jwakely@redhat.com>
+
+       * testsuite/20_util/is_complete_or_unbounded/memoization_neg.cc:
+       Simplify dg-prune-output pattern.
+       * testsuite/lib/prune.exp (libstdc++-dg-prune): Prune "::__8".
+
+2022-11-28  Jonathan Wakely  <jwakely@redhat.com>
+
+       PR libstdc++/107466
+       * include/bits/random.h (subtract_with_carry_engine): Use 32-bit
+       type for default seed. Use 0u as default argument for
+       subtract_with_carry_engine(result_type) constructor and
+       seed(result_type) member function.
+       * include/bits/random.tcc (subtract_with_carry_engine): Use
+       32-bit type for default seed and engine used for initial state.
+       * testsuite/26_numerics/random/subtract_with_carry_engine/cons/lwg3809.cc:
+       New test.
+
 2022-11-25  Jonathan Wakely  <jwakely@redhat.com>
 
        * acinclude.m4 (GLIBCXX_CHECK_UCHAR_H): Don't use AC_MSG_RESULT