]> gcc.gnu.org Git - gcc.git/commitdiff
RISC-V: Allow const 17-31 for vector shift.
authorRobin Dapp <rdapp@ventanamicro.com>
Fri, 18 Aug 2023 14:16:54 +0000 (16:16 +0200)
committerRobin Dapp <rdapp@ventanamicro.com>
Thu, 24 Aug 2023 11:12:49 +0000 (13:12 +0200)
This patch adds a missing constraint in order to be able to print (and
not ICE) vector immediates 17-31 for vector shifts.

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_print_operand): Allow vk operand.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/shift-immediate.c: New test.

gcc/config/riscv/riscv.cc
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c [new file with mode: 0644]

index 49062bef9fca4a6c9224667ed88a3b29699de192..0f60ffe5f60b425bd712995d527b5e0e497c512b 100644 (file)
@@ -4954,7 +4954,8 @@ riscv_print_operand (FILE *file, rtx op, int letter)
            else if (satisfies_constraint_Wc0 (op))
              asm_fprintf (file, "0");
            else if (satisfies_constraint_vi (op)
-                    || satisfies_constraint_vj (op))
+                    || satisfies_constraint_vj (op)
+                    || satisfies_constraint_vk (op))
              asm_fprintf (file, "%wd", INTVAL (elt));
            else
              output_operand_lossage ("invalid vector constant");
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c
new file mode 100644 (file)
index 0000000..a2e1c33
--- /dev/null
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -O2 --param=riscv-autovec-preference=scalable" } */
+
+#define uint8_t unsigned char
+
+void foo1 (uint8_t *a)
+{
+    uint8_t b = a[0];
+    int val = 0;
+
+    for (int i = 0; i < 4; i++)
+    {
+        a[i] = (val & 1) ? (-val) >> 17 : val;
+        val += b;
+    }
+}
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