[(set_attr "type" "vecsimple")])
;; Vector Count Trailing Zero Least-Significant Bits Byte
-(define_insn "vctzlsbb_<mode>"
- [(set (match_operand:SI 0 "register_operand" "=r")
+(define_insn "*vctzlsbb_zext_<mode>"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI
(unspec:SI
[(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand" "v")]
- UNSPEC_VCTZLSBB))]
+ UNSPEC_VCTZLSBB)))]
+ "TARGET_P9_VECTOR"
+ "vctzlsbb %0,%1"
+ [(set_attr "type" "vecsimple")])
+
+;; Vector Count Trailing Zero Least-Significant Bits Byte
+(define_insn "vctzlsbb_<mode>"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI
+ [(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand" "v")]
+ UNSPEC_VCTZLSBB))]
"TARGET_P9_VECTOR"
"vctzlsbb %0,%1"
[(set_attr "type" "vecsimple")])
--- /dev/null
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power9 -O2 " } */
+
+#include <altivec.h>
+
+unsigned int foo (vector unsigned char a, vector unsigned char b) {
+ return vec_first_match_or_eos_index (a, b);
+}
+/* { dg-final { scan-assembler-not {\mrldicl\M} } } */