+2018-02-21 Segher Boessenkool <segher@kernel.crashing.org>
+
+ * config/rs6000/altivec.md: Delete contraint arguments to
+ define_expand, define_split, and define_peephole2, and in
+ define_insn_and_split if always unused.
+ * config/rs6000/darwin.md: Ditto.
+ * config/rs6000/dfp.md: Ditto.
+ * config/rs6000/rs6000.md: Ditto.
+ * config/rs6000/sync.md: Ditto.
+ * config/rs6000/vector.md: Ditto.
+ * config/rs6000/vsx.md: Ditto.
+
2018-02-21 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/altivec.md: Write output control strings as braced
;; Load up a vector with the most significant bit set by loading up -1 and
;; doing a shift left
(define_split
- [(set (match_operand:VM 0 "altivec_register_operand" "")
- (match_operand:VM 1 "easy_vector_constant_msb" ""))]
+ [(set (match_operand:VM 0 "altivec_register_operand")
+ (match_operand:VM 1 "easy_vector_constant_msb"))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && reload_completed"
[(const_int 0)]
{
})
(define_split
- [(set (match_operand:VM 0 "altivec_register_operand" "")
- (match_operand:VM 1 "easy_vector_constant_add_self" ""))]
+ [(set (match_operand:VM 0 "altivec_register_operand")
+ (match_operand:VM 1 "easy_vector_constant_add_self"))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && reload_completed"
[(set (match_dup 0) (match_dup 3))
(set (match_dup 0) (match_dup 4))]
})
(define_split
- [(set (match_operand:VM 0 "altivec_register_operand" "")
- (match_operand:VM 1 "easy_vector_constant_vsldoi" ""))]
+ [(set (match_operand:VM 0 "altivec_register_operand")
+ (match_operand:VM 1 "easy_vector_constant_vsldoi"))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && can_create_pseudo_p ()"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 4) (match_dup 5))
;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
(define_expand "altivec_mulv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (fma:V4SF (match_operand:V4SF 1 "register_operand" "")
- (match_operand:V4SF 2 "register_operand" "")
+ [(set (match_operand:V4SF 0 "register_operand")
+ (fma:V4SF (match_operand:V4SF 1 "register_operand")
+ (match_operand:V4SF 2 "register_operand")
(match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
{
[(set_attr "type" "veccomplex")])
(define_expand "mulv4si3"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V4SI 1 "register_operand" ""))
- (use (match_operand:V4SI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V4SI 1 "register_operand"))
+ (use (match_operand:V4SI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtx zero;
})
(define_expand "mulv8hi3"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtx zero = gen_reg_rtx (V8HImode);
[(set_attr "type" "veccomplex")])
(define_expand "altivec_vmrghb"
- [(use (match_operand:V16QI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:V16QI 2 "register_operand" ""))]
+ [(use (match_operand:V16QI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrghh"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrghw"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V4SI 1 "register_operand" ""))
- (use (match_operand:V4SI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V4SI 1 "register_operand"))
+ (use (match_operand:V4SI 2 "register_operand"))]
"VECTOR_MEM_ALTIVEC_P (V4SImode)"
{
rtvec v;
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrglb"
- [(use (match_operand:V16QI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:V16QI 2 "register_operand" ""))]
+ [(use (match_operand:V16QI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrglh"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrglw"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V4SI 1 "register_operand" ""))
- (use (match_operand:V4SI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V4SI 1 "register_operand"))
+ (use (match_operand:V4SI 2 "register_operand"))]
"VECTOR_MEM_ALTIVEC_P (V4SImode)"
{
rtvec v;
[(set_attr "type" "vecperm")])
(define_expand "vec_widen_umult_even_v16qi"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:V16QI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
})
(define_expand "vec_widen_smult_even_v16qi"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:V16QI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
})
(define_expand "vec_widen_umult_even_v8hi"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
})
(define_expand "vec_widen_smult_even_v8hi"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
})
(define_expand "vec_widen_umult_odd_v16qi"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:V16QI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
})
(define_expand "vec_widen_smult_odd_v16qi"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:V16QI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
})
(define_expand "vec_widen_umult_odd_v8hi"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
})
(define_expand "vec_widen_smult_odd_v8hi"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
[(set_attr "type" "veccomplex")])
(define_expand "altivec_vspltb"
- [(use (match_operand:V16QI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
+ [(use (match_operand:V16QI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:QI 2 "u5bit_cint_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
[(set_attr "type" "vecperm")])
(define_expand "altivec_vsplth"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:QI 2 "u5bit_cint_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
[(set_attr "type" "vecperm")])
(define_expand "altivec_vspltw"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V4SI 1 "register_operand" ""))
- (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V4SI 1 "register_operand"))
+ (use (match_operand:QI 2 "u5bit_cint_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
[(set_attr "type" "vecperm")])
(define_expand "altivec_vspltsf"
- [(use (match_operand:V4SF 0 "register_operand" ""))
- (use (match_operand:V4SF 1 "register_operand" ""))
- (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
+ [(use (match_operand:V4SF 0 "register_operand"))
+ (use (match_operand:V4SF 1 "register_operand"))
+ (use (match_operand:QI 2 "u5bit_cint_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
[(set_attr "type" "vecfloat")])
(define_expand "altivec_vperm_<mode>"
- [(set (match_operand:VM 0 "register_operand" "")
- (unspec:VM [(match_operand:VM 1 "register_operand" "")
- (match_operand:VM 2 "register_operand" "")
- (match_operand:V16QI 3 "register_operand" "")]
+ [(set (match_operand:VM 0 "register_operand")
+ (unspec:VM [(match_operand:VM 1 "register_operand")
+ (match_operand:VM 2 "register_operand")
+ (match_operand:V16QI 3 "register_operand")]
UNSPEC_VPERM))]
"TARGET_ALTIVEC"
{
(set_attr "length" "4")])
(define_expand "altivec_vperm_<mode>_uns"
- [(set (match_operand:VM 0 "register_operand" "")
- (unspec:VM [(match_operand:VM 1 "register_operand" "")
- (match_operand:VM 2 "register_operand" "")
- (match_operand:V16QI 3 "register_operand" "")]
+ [(set (match_operand:VM 0 "register_operand")
+ (unspec:VM [(match_operand:VM 1 "register_operand")
+ (match_operand:VM 2 "register_operand")
+ (match_operand:V16QI 3 "register_operand")]
UNSPEC_VPERM_UNS))]
"TARGET_ALTIVEC"
{
(set_attr "length" "4")])
(define_expand "vec_permv16qi"
- [(set (match_operand:V16QI 0 "register_operand" "")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
- (match_operand:V16QI 2 "register_operand" "")
- (match_operand:V16QI 3 "register_operand" "")]
+ [(set (match_operand:V16QI 0 "register_operand")
+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand")
+ (match_operand:V16QI 2 "register_operand")
+ (match_operand:V16QI 3 "register_operand")]
UNSPEC_VPERM))]
"TARGET_ALTIVEC"
{
[(set_attr "type" "vecfloat")])
(define_expand "altivec_copysign_v4sf3"
- [(use (match_operand:V4SF 0 "register_operand" ""))
- (use (match_operand:V4SF 1 "register_operand" ""))
- (use (match_operand:V4SF 2 "register_operand" ""))]
+ [(use (match_operand:V4SF 0 "register_operand"))
+ (use (match_operand:V4SF 1 "register_operand"))
+ (use (match_operand:V4SF 2 "register_operand"))]
"VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
{
rtx mask = gen_reg_rtx (V4SImode);
[(set_attr "type" "vecsimple")])
(define_expand "altivec_lvsl"
- [(use (match_operand:V16QI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "memory_operand" ""))]
+ [(use (match_operand:V16QI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "memory_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
[(set_attr "type" "vecload")])
(define_expand "build_vector_mask_for_load"
- [(set (match_operand:V16QI 0 "register_operand" "")
- (unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))]
+ [(set (match_operand:V16QI 0 "register_operand")
+ (unspec:V16QI [(match_operand 1 "memory_operand")] UNSPEC_LVSR))]
"TARGET_ALTIVEC"
{
rtx addr;
[(set_attr "type" "vecsimple")])
(define_expand "neg<mode>2"
- [(set (match_operand:VI2 0 "register_operand" "")
- (neg:VI2 (match_operand:VI2 1 "register_operand" "")))]
+ [(set (match_operand:VI2 0 "register_operand")
+ (neg:VI2 (match_operand:VI2 1 "register_operand")))]
"<VI_unit>"
{
if (!TARGET_P9_VECTOR || (<MODE>mode != V4SImode && <MODE>mode != V2DImode))
})
(define_expand "altivec_negv4sf2"
- [(use (match_operand:V4SF 0 "register_operand" ""))
- (use (match_operand:V4SF 1 "register_operand" ""))]
+ [(use (match_operand:V4SF 0 "register_operand"))
+ (use (match_operand:V4SF 1 "register_operand"))]
"TARGET_ALTIVEC"
{
rtx neg0;
[(set_attr "type" "vecstore")])
(define_expand "vec_unpacks_float_hi_v8hi"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
+ [(set (match_operand:V4SF 0 "register_operand")
+ (unspec:V4SF [(match_operand:V8HI 1 "register_operand")]
UNSPEC_VUPKHS_V4SF))]
"TARGET_ALTIVEC"
{
})
(define_expand "vec_unpacks_float_lo_v8hi"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
+ [(set (match_operand:V4SF 0 "register_operand")
+ (unspec:V4SF [(match_operand:V8HI 1 "register_operand")]
UNSPEC_VUPKLS_V4SF))]
"TARGET_ALTIVEC"
{
})
(define_expand "vec_unpacku_float_hi_v8hi"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
+ [(set (match_operand:V4SF 0 "register_operand")
+ (unspec:V4SF [(match_operand:V8HI 1 "register_operand")]
UNSPEC_VUPKHU_V4SF))]
"TARGET_ALTIVEC"
{
})
(define_expand "vec_unpacku_float_lo_v8hi"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
+ [(set (match_operand:V4SF 0 "register_operand")
+ (unspec:V4SF [(match_operand:V8HI 1 "register_operand")]
UNSPEC_VUPKLU_V4SF))]
"TARGET_ALTIVEC"
{
(define_expand "bcd<bcd_add_sub>_<code>"
[(parallel [(set (reg:CCFP CR6_REGNO)
(compare:CCFP
- (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "")
- (match_operand:V1TI 2 "register_operand" "")
- (match_operand:QI 3 "const_0_to_1_operand" "")]
+ (unspec:V2DF [(match_operand:V1TI 1 "register_operand")
+ (match_operand:V1TI 2 "register_operand")
+ (match_operand:QI 3 "const_0_to_1_operand")]
UNSPEC_BCD_ADD_SUB)
(match_dup 4)))
- (clobber (match_scratch:V1TI 5 ""))])
- (set (match_operand:SI 0 "register_operand" "")
+ (clobber (match_scratch:V1TI 5))])
+ (set (match_operand:SI 0 "register_operand")
(BCD_TEST:SI (reg:CCFP CR6_REGNO)
(const_int 0)))]
"TARGET_P8_VECTOR"
;; a register class for CR6.
(define_peephole2
- [(parallel [(set (match_operand:V1TI 0 "register_operand" "")
- (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "")
- (match_operand:V1TI 2 "register_operand" "")
- (match_operand:QI 3 "const_0_to_1_operand" "")]
+ [(parallel [(set (match_operand:V1TI 0 "register_operand")
+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand")
+ (match_operand:V1TI 2 "register_operand")
+ (match_operand:QI 3 "const_0_to_1_operand")]
UNSPEC_BCD_ADD_SUB))
(clobber (reg:CCFP CR6_REGNO))])
(parallel [(set (reg:CCFP CR6_REGNO)
(match_dup 2)
(match_dup 3)]
UNSPEC_BCD_ADD_SUB)
- (match_operand:V2DF 4 "zero_constant" "")))
- (clobber (match_operand:V1TI 5 "register_operand" ""))])]
+ (match_operand:V2DF 4 "zero_constant")))
+ (clobber (match_operand:V1TI 5 "register_operand"))])]
"TARGET_P8_VECTOR"
[(parallel [(set (match_dup 0)
(unspec:V1TI [(match_dup 1)
;; Mach-O PIC trickery.
(define_expand "macho_high"
- [(set (match_operand 0 "" "")
- (high (match_operand 1 "" "")))]
+ [(set (match_operand 0 "")
+ (high (match_operand 1 "")))]
"TARGET_MACHO"
{
if (TARGET_64BIT)
"lis %0,ha16(%1)")
(define_expand "macho_low"
- [(set (match_operand 0 "" "")
- (lo_sum (match_operand 1 "" "")
- (match_operand 2 "" "")))]
+ [(set (match_operand 0 "")
+ (lo_sum (match_operand 1 "")
+ (match_operand 2 "")))]
"TARGET_MACHO"
{
if (TARGET_64BIT)
"la %0,lo16(%2)(%1)")
(define_split
- [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
- (match_operand:DI 1 "short_cint_operand" "")))
- (match_operand:V4SI 2 "register_operand" ""))
- (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
+ [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand")
+ (match_operand:DI 1 "short_cint_operand")))
+ (match_operand:V4SI 2 "register_operand"))
+ (clobber (match_operand:DI 3 "gpc_reg_operand"))]
"TARGET_MACHO && TARGET_64BIT"
[(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
(set (mem:V4SI (match_dup 3))
(define_expand "load_macho_picbase"
[(set (reg:SI LR_REGNO)
- (unspec [(match_operand 0 "" "")]
+ (unspec [(match_operand 0 "")]
UNSPEC_LD_MPIC))]
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
{
(set_attr "length" "4")])
(define_expand "macho_correct_pic"
- [(set (match_operand 0 "" "")
- (plus (match_operand 1 "" "")
- (unspec [(match_operand 2 "" "")
- (match_operand 3 "" "")]
+ [(set (match_operand 0 "")
+ (plus (match_operand 1 "")
+ (unspec [(match_operand 2 "")
+ (match_operand 3 "")]
UNSPEC_MPIC_CORRECT)))]
"DEFAULT_ABI == ABI_DARWIN"
{
(define_expand "reload_macho_picbase"
[(set (reg:SI LR_REGNO)
- (unspec [(match_operand 0 "" "")]
+ (unspec [(match_operand 0 "")]
UNSPEC_RELD_MPIC))]
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
{
[(set (match_dup 3)
(compare:CCFP
(unspec:D64_D128
- [(match_operand:SI 1 "const_int_operand" "n")
- (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
+ [(match_operand:SI 1 "const_int_operand")
+ (match_operand:D64_D128 2 "gpc_reg_operand")]
UNSPEC_DTSTSFI)
(match_dup 4)))
- (set (match_operand:SI 0 "register_operand" "")
+ (set (match_operand:SI 0 "register_operand")
(DFP_TEST:SI (match_dup 3)
(const_int 0)))
]
"dlmzb. %0,%1,%2")
(define_expand "strlensi"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (unspec:SI [(match_operand:BLK 1 "general_operand" "")
- (match_operand:QI 2 "const_int_operand" "")
- (match_operand 3 "const_int_operand" "")]
+ [(set (match_operand:SI 0 "gpc_reg_operand")
+ (unspec:SI [(match_operand:BLK 1 "general_operand")
+ (match_operand:QI 2 "const_int_operand")
+ (match_operand 3 "const_int_operand")]
UNSPEC_DLMZB_STRLEN))
- (clobber (match_scratch:CC 4 "=x"))]
+ (clobber (match_scratch:CC 4))]
"TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
{
rtx result = operands[0];
;; Fixed-point arithmetic insns.
(define_expand "add<mode>3"
- [(set (match_operand:SDI 0 "gpc_reg_operand" "")
- (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
- (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
+ [(set (match_operand:SDI 0 "gpc_reg_operand")
+ (plus:SDI (match_operand:SDI 1 "gpc_reg_operand")
+ (match_operand:SDI 2 "reg_or_add_cint_operand")))]
""
{
if (<MODE>mode == DImode && !TARGET_POWERPC64)
;; add should be last in case the result gets used in an address.
(define_split
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
- (match_operand:GPR 2 "non_add_cint_operand" "")))]
+ [(set (match_operand:GPR 0 "gpc_reg_operand")
+ (plus:GPR (match_operand:GPR 1 "gpc_reg_operand")
+ (match_operand:GPR 2 "non_add_cint_operand")))]
""
[(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
(set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
(define_expand "one_cmpl<mode>2"
- [(set (match_operand:SDI 0 "gpc_reg_operand" "")
- (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SDI 0 "gpc_reg_operand")
+ (not:SDI (match_operand:SDI 1 "gpc_reg_operand")))]
""
{
if (<MODE>mode == DImode && !TARGET_POWERPC64)
(define_expand "sub<mode>3"
- [(set (match_operand:SDI 0 "gpc_reg_operand" "")
- (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
- (match_operand:SDI 2 "gpc_reg_operand" "")))]
+ [(set (match_operand:SDI 0 "gpc_reg_operand")
+ (minus:SDI (match_operand:SDI 1 "reg_or_short_operand")
+ (match_operand:SDI 2 "gpc_reg_operand")))]
""
{
if (<MODE>mode == DImode && !TARGET_POWERPC64)
(define_expand "popcount<mode>2"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:GPR 0 "gpc_reg_operand")
+ (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand")))]
"TARGET_POPCNTB || TARGET_POPCNTD"
{
rs6000_emit_popcount (operands[0], operands[1]);
(define_expand "parity<mode>2"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:GPR 0 "gpc_reg_operand")
+ (parity:GPR (match_operand:GPR 1 "gpc_reg_operand")))]
"TARGET_POPCNTB"
{
rs6000_emit_parity (operands[0], operands[1]);
;; complex code.
(define_expand "bswapdi2"
- [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
+ [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand")
(bswap:DI
- (match_operand:DI 1 "reg_or_mem_operand" "")))
- (clobber (match_scratch:DI 2 ""))
- (clobber (match_scratch:DI 3 ""))])]
+ (match_operand:DI 1 "reg_or_mem_operand")))
+ (clobber (match_scratch:DI 2))
+ (clobber (match_scratch:DI 3))])]
""
{
rtx dest = operands[0];
[(set_attr "length" "16,12,36")])
(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
- (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
- (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
+ [(set (match_operand:DI 0 "gpc_reg_operand")
+ (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand")))
+ (clobber (match_operand:DI 2 "gpc_reg_operand"))
+ (clobber (match_operand:DI 3 "gpc_reg_operand"))]
"TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
[(const_int 0)]
{
})
(define_split
- [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
- (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
- (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
- (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
+ [(set (match_operand:DI 0 "indexed_or_indirect_operand")
+ (bswap:DI (match_operand:DI 1 "gpc_reg_operand")))
+ (clobber (match_operand:DI 2 "gpc_reg_operand"))
+ (clobber (match_operand:DI 3 "gpc_reg_operand"))]
"TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
[(const_int 0)]
{
})
(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
- (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
- (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
+ [(set (match_operand:DI 0 "gpc_reg_operand")
+ (bswap:DI (match_operand:DI 1 "gpc_reg_operand")))
+ (clobber (match_operand:DI 2 "gpc_reg_operand"))
+ (clobber (match_operand:DI 3 "gpc_reg_operand"))]
"TARGET_POWERPC64 && !TARGET_P9_VECTOR && reload_completed"
[(const_int 0)]
{
[(set_attr "length" "16,12,36")])
(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
- (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
+ [(set (match_operand:DI 0 "gpc_reg_operand")
+ (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand")))
+ (clobber (match_operand:SI 2 "gpc_reg_operand"))]
"!TARGET_POWERPC64 && reload_completed"
[(const_int 0)]
{
})
(define_split
- [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
- (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
- (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
+ [(set (match_operand:DI 0 "indexed_or_indirect_operand")
+ (bswap:DI (match_operand:DI 1 "gpc_reg_operand")))
+ (clobber (match_operand:SI 2 "gpc_reg_operand"))]
"!TARGET_POWERPC64 && reload_completed"
[(const_int 0)]
{
})
(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
- (clobber (match_operand:SI 2 "" ""))]
+ [(set (match_operand:DI 0 "gpc_reg_operand")
+ (bswap:DI (match_operand:DI 1 "gpc_reg_operand")))
+ (clobber (match_operand:SI 2 ""))]
"!TARGET_POWERPC64 && reload_completed"
[(const_int 0)]
{
mulli %0,%1,%2"
[(set_attr "type" "mul")
(set (attr "size")
- (cond [(match_operand:GPR 2 "s8bit_cint_operand" "")
+ (cond [(match_operand:GPR 2 "s8bit_cint_operand")
(const_string "8")
- (match_operand:GPR 2 "short_cint_operand" "")
+ (match_operand:GPR 2 "short_cint_operand")
(const_string "16")]
(const_string "<bits>")))])
;; modulus. If it isn't a power of two, force operands into register and do
;; a normal divide.
(define_expand "div<mode>3"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
- (match_operand:GPR 2 "reg_or_cint_operand" "")))]
+ [(set (match_operand:GPR 0 "gpc_reg_operand")
+ (div:GPR (match_operand:GPR 1 "gpc_reg_operand")
+ (match_operand:GPR 2 "reg_or_cint_operand")))]
""
{
if (CONST_INT_P (operands[2])
;; after a divide.
(define_peephole2
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
- (match_operand:GPR 2 "gpc_reg_operand" "")))
- (set (match_operand:GPR 3 "gpc_reg_operand" "")
+ [(set (match_operand:GPR 0 "gpc_reg_operand")
+ (div:GPR (match_operand:GPR 1 "gpc_reg_operand")
+ (match_operand:GPR 2 "gpc_reg_operand")))
+ (set (match_operand:GPR 3 "gpc_reg_operand")
(mod:GPR (match_dup 1)
(match_dup 2)))]
"TARGET_MODULO
(match_dup 3)))])
(define_peephole2
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
- (match_operand:GPR 2 "gpc_reg_operand" "")))
- (set (match_operand:GPR 3 "gpc_reg_operand" "")
+ [(set (match_operand:GPR 0 "gpc_reg_operand")
+ (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand")
+ (match_operand:GPR 2 "gpc_reg_operand")))
+ (set (match_operand:GPR 3 "gpc_reg_operand")
(umod:GPR (match_dup 1)
(match_dup 2)))]
"TARGET_MODULO
;; those rotate-and-mask operations. Thus, the AND insns come first.
(define_expand "and<mode>3"
- [(set (match_operand:SDI 0 "gpc_reg_operand" "")
- (and:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
- (match_operand:SDI 2 "reg_or_cint_operand" "")))]
+ [(set (match_operand:SDI 0 "gpc_reg_operand")
+ (and:SDI (match_operand:SDI 1 "gpc_reg_operand")
+ (match_operand:SDI 2 "reg_or_cint_operand")))]
""
{
if (<MODE>mode == DImode && !TARGET_POWERPC64)
(define_expand "<code><mode>3"
- [(set (match_operand:SDI 0 "gpc_reg_operand" "")
- (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
- (match_operand:SDI 2 "reg_or_cint_operand" "")))]
+ [(set (match_operand:SDI 0 "gpc_reg_operand")
+ (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand")
+ (match_operand:SDI 2 "reg_or_cint_operand")))]
""
{
if (<MODE>mode == DImode && !TARGET_POWERPC64)
})
(define_split
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
- (match_operand:GPR 2 "non_logical_cint_operand" "")))]
+ [(set (match_operand:GPR 0 "gpc_reg_operand")
+ (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand")
+ (match_operand:GPR 2 "non_logical_cint_operand")))]
""
[(set (match_dup 3)
(iorxor:GPR (match_dup 1)
;; Builtins to replace a division to generate FRE reciprocal estimate
;; instructions and the necessary fixup instructions
(define_expand "recip<mode>3"
- [(match_operand:RECIPF 0 "gpc_reg_operand" "")
- (match_operand:RECIPF 1 "gpc_reg_operand" "")
- (match_operand:RECIPF 2 "gpc_reg_operand" "")]
+ [(match_operand:RECIPF 0 "gpc_reg_operand")
+ (match_operand:RECIPF 1 "gpc_reg_operand")
+ (match_operand:RECIPF 2 "gpc_reg_operand")]
"RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
{
rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
;; We used to also check optimize_insn_for_speed_p () but problems with guessed
;; frequencies (pr68212/pr77536) yields that unreliable so it was removed.
(define_split
- [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
- (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
- (match_operand 2 "gpc_reg_operand" "")))]
+ [(set (match_operand:RECIPF 0 "gpc_reg_operand")
+ (div:RECIPF (match_operand 1 "gpc_reg_operand")
+ (match_operand 2 "gpc_reg_operand")))]
"RS6000_RECIP_AUTO_RE_P (<MODE>mode)
&& can_create_pseudo_p () && flag_finite_math_only
&& !flag_trapping_math && flag_reciprocal_math"
;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
;; appropriate fixup.
(define_expand "rsqrt<mode>2"
- [(match_operand:RECIPF 0 "gpc_reg_operand" "")
- (match_operand:RECIPF 1 "gpc_reg_operand" "")]
+ [(match_operand:RECIPF 0 "gpc_reg_operand")
+ (match_operand:RECIPF 1 "gpc_reg_operand")]
"RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
{
rs6000_emit_swsqrt (operands[0], operands[1], 1);
;; -mupper-regs-{df,sf} option is enabled.
(define_expand "abs<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))]
"TARGET_<MODE>_INSN"
"")
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_expand "neg<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))]
"TARGET_<MODE>_INSN"
"")
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_expand "add<mode>3"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
- (match_operand:SFDF 2 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
+ (match_operand:SFDF 2 "gpc_reg_operand")))]
"TARGET_<MODE>_INSN"
"")
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_expand "sub<mode>3"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
- (match_operand:SFDF 2 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
+ (match_operand:SFDF 2 "gpc_reg_operand")))]
"TARGET_<MODE>_INSN"
"")
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_expand "mul<mode>3"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
- (match_operand:SFDF 2 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
+ (match_operand:SFDF 2 "gpc_reg_operand")))]
"TARGET_<MODE>_INSN"
"")
(set_attr "fp_type" "fp_mul_<Fs>")])
(define_expand "div<mode>3"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
- (match_operand:SFDF 2 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
+ (match_operand:SFDF 2 "gpc_reg_operand")))]
"TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
{
if (RS6000_RECIP_AUTO_RE_P (<MODE>mode)
(set_attr "fp_type" "fp_sqrt_<Fs>")])
(define_expand "sqrt<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))]
"TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
&& (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
{
[(set_attr "type" "fp")])
(define_expand "truncdfsf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "")
- (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand")
+ (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"")
;; when little-endian.
(define_expand "signbit<mode>2"
[(set (match_dup 2)
- (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))
+ (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand")))
(set (match_dup 3)
(subreg:DI (match_dup 2) 0))
(set (match_dup 4)
(match_dup 5))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand")
(match_dup 6))]
"TARGET_HARD_FLOAT
&& (!FLOAT128_IEEE_P (<MODE>mode)
(define_expand "copysign<mode>3"
[(set (match_dup 3)
- (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
+ (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))
(set (match_dup 4)
(neg:SFDF (abs:SFDF (match_dup 1))))
- (set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
+ (set (match_operand:SFDF 0 "gpc_reg_operand")
+ (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand")
(match_dup 5))
(match_dup 3)
(match_dup 4)))]
;; to allow either DF/SF to use only traditional registers.
(define_expand "s<minmax><mode>3"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
- (match_operand:SFDF 2 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
+ (match_operand:SFDF 2 "gpc_reg_operand")))]
"TARGET_MINMAX_<MODE>"
{
rs6000_emit_minmax (operands[0], <SMINMAX>, operands[1], operands[2]);
;; instruction.
(define_insn_and_split "*s<minmax><mode>3_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
- (match_operand:SFDF 2 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
+ (match_operand:SFDF 2 "gpc_reg_operand")))]
"!TARGET_VSX && TARGET_MINMAX_<MODE>"
"#"
"&& 1"
})
(define_expand "mov<mode>cc"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (if_then_else:GPR (match_operand 1 "comparison_operator" "")
- (match_operand:GPR 2 "gpc_reg_operand" "")
- (match_operand:GPR 3 "gpc_reg_operand" "")))]
+ [(set (match_operand:GPR 0 "gpc_reg_operand")
+ (if_then_else:GPR (match_operand 1 "comparison_operator")
+ (match_operand:GPR 2 "gpc_reg_operand")
+ (match_operand:GPR 3 "gpc_reg_operand")))]
"TARGET_ISEL"
{
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
;; Floating point conditional move
(define_expand "mov<mode>cc"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (if_then_else:SFDF (match_operand 1 "comparison_operator" "")
- (match_operand:SFDF 2 "gpc_reg_operand" "")
- (match_operand:SFDF 3 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (if_then_else:SFDF (match_operand 1 "comparison_operator")
+ (match_operand:SFDF 2 "gpc_reg_operand")
+ (match_operand:SFDF 3 "gpc_reg_operand")))]
"TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT"
{
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
; then to have the insns split later (between sched1 and final).
(define_expand "floatsidf2"
- [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
- (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
+ [(parallel [(set (match_operand:DF 0 "gpc_reg_operand")
+ (float:DF (match_operand:SI 1 "nonimmediate_operand")))
(use (match_dup 2))
(use (match_dup 3))
(clobber (match_dup 4))
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
(define_expand "floatunssisf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "")
- (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand")
+ (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand")))]
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& ((TARGET_FCFIDUS && TARGET_LFIWZX)
|| (TARGET_DOUBLE_FLOAT && TARGET_FCFID
})
(define_expand "floatunssidf2"
- [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
- (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
+ [(parallel [(set (match_operand:DF 0 "gpc_reg_operand")
+ (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand")))
(use (match_dup 2))
(use (match_dup 3))
(clobber (match_dup 4))
(define_expand "floatuns<QHI:mode><FP_ISA3:mode>2"
[(parallel [(set (match_operand:FP_ISA3 0 "vsx_register_operand")
(unsigned_float:FP_ISA3
- (match_operand:QHI 1 "input_operand" "")))
- (clobber (match_scratch:DI 2 ""))
- (clobber (match_scratch:DI 3 ""))])]
+ (match_operand:QHI 1 "input_operand")))
+ (clobber (match_scratch:DI 2))
+ (clobber (match_scratch:DI 3))])]
"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
{
if (MEM_P (operands[1]))
})
(define_expand "fix_trunc<mode>si2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SI 0 "gpc_reg_operand")
+ (fix:SI (match_operand:SFDF 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && <TARGET_FLOAT>"
{
if (!TARGET_P8_VECTOR)
(set_attr "type" "fp")])
(define_expand "fix_trunc<mode>di2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:DI 0 "gpc_reg_operand")
+ (fix:DI (match_operand:SFDF 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFID"
"")
})
(define_expand "fixuns_trunc<mode>si2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SI 0 "gpc_reg_operand")
+ (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX"
{
if (!TARGET_P8_VECTOR)
(define_expand "lround<mode>di2"
[(set (match_dup 2)
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand")]
UNSPEC_XSRDPI))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
+ (set (match_operand:DI 0 "gpc_reg_operand")
(unspec:DI [(match_dup 2)]
UNSPEC_FCTID))]
"TARGET_<MODE>_FPR && TARGET_VSX"
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
(define_expand "floatsisf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "")
- (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand")
+ (float:SF (match_operand:SI 1 "nonimmediate_operand")))]
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& ((TARGET_FCFIDS && TARGET_LFIWAX)
|| (TARGET_DOUBLE_FLOAT && TARGET_FCFID
(set_attr "type" "fpload")])
(define_expand "floatunsdidf2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ [(set (match_operand:DF 0 "gpc_reg_operand")
(unsigned_float:DF
- (match_operand:DI 1 "gpc_reg_operand" "")))]
+ (match_operand:DI 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_FCFIDU"
"")
(set_attr "type" "fpload")])
(define_expand "floatdisf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "")
- (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand")
+ (float:SF (match_operand:DI 1 "gpc_reg_operand")))]
"TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
{
;; by a bit that won't be lost at that stage, but is below the SFmode
;; rounding position.
(define_expand "floatdisf2_internal2"
- [(parallel [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
+ [(parallel [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "")
(const_int 53)))
(clobber (reg:DI CA_REGNO))])
- (set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
- (const_int 2047)))
+ (set (match_operand:DI 0 "") (and:DI (match_dup 1)
+ (const_int 2047)))
(set (match_dup 3) (plus:DI (match_dup 3)
(const_int 1)))
(set (match_dup 0) (plus:DI (match_dup 0)
(set (match_dup 0) (and:DI (match_dup 0)
(const_int -2048)))
(set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
- (label_ref (match_operand:DI 2 "" ""))
+ (label_ref (match_operand:DI 2 ""))
(pc)))
(set (match_dup 0) (match_dup 1))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
})
(define_expand "floatunsdisf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "")
- (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand")
+ (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
"")
;; also allow for the output being the same as one of the inputs.
(define_expand "addti3"
- [(set (match_operand:TI 0 "gpc_reg_operand" "")
- (plus:TI (match_operand:TI 1 "gpc_reg_operand" "")
- (match_operand:TI 2 "reg_or_short_operand" "")))]
+ [(set (match_operand:TI 0 "gpc_reg_operand")
+ (plus:TI (match_operand:TI 1 "gpc_reg_operand")
+ (match_operand:TI 2 "reg_or_short_operand")))]
"TARGET_64BIT"
{
rtx lo0 = gen_lowpart (DImode, operands[0]);
})
(define_expand "subti3"
- [(set (match_operand:TI 0 "gpc_reg_operand" "")
- (minus:TI (match_operand:TI 1 "reg_or_short_operand" "")
- (match_operand:TI 2 "gpc_reg_operand" "")))]
+ [(set (match_operand:TI 0 "gpc_reg_operand")
+ (minus:TI (match_operand:TI 1 "reg_or_short_operand")
+ (match_operand:TI 2 "gpc_reg_operand")))]
"TARGET_64BIT"
{
rtx lo0 = gen_lowpart (DImode, operands[0]);
;; 128-bit logical operations expanders
(define_expand "and<mode>3"
- [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
- (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
- (match_operand:BOOL_128 2 "vlogical_operand" "")))]
+ [(set (match_operand:BOOL_128 0 "vlogical_operand")
+ (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")
+ (match_operand:BOOL_128 2 "vlogical_operand")))]
""
"")
(define_expand "ior<mode>3"
- [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
- (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
- (match_operand:BOOL_128 2 "vlogical_operand" "")))]
+ [(set (match_operand:BOOL_128 0 "vlogical_operand")
+ (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")
+ (match_operand:BOOL_128 2 "vlogical_operand")))]
""
"")
(define_expand "xor<mode>3"
- [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
- (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
- (match_operand:BOOL_128 2 "vlogical_operand" "")))]
+ [(set (match_operand:BOOL_128 0 "vlogical_operand")
+ (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")
+ (match_operand:BOOL_128 2 "vlogical_operand")))]
""
"")
(define_expand "one_cmpl<mode>2"
- [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
- (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
+ [(set (match_operand:BOOL_128 0 "vlogical_operand")
+ (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")))]
""
"")
(define_expand "nor<mode>3"
- [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
+ [(set (match_operand:BOOL_128 0 "vlogical_operand")
(and:BOOL_128
- (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
- (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
+ (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand"))
+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand"))))]
""
"")
(define_expand "andc<mode>3"
- [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
+ [(set (match_operand:BOOL_128 0 "vlogical_operand")
(and:BOOL_128
- (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
- (match_operand:BOOL_128 1 "vlogical_operand" "")))]
+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand"))
+ (match_operand:BOOL_128 1 "vlogical_operand")))]
""
"")
;; Power8 vector logical instructions.
(define_expand "eqv<mode>3"
- [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
+ [(set (match_operand:BOOL_128 0 "vlogical_operand")
(not:BOOL_128
- (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
- (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
+ (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")
+ (match_operand:BOOL_128 2 "vlogical_operand"))))]
"<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
"")
;; Rewrite nand into canonical form
(define_expand "nand<mode>3"
- [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
+ [(set (match_operand:BOOL_128 0 "vlogical_operand")
(ior:BOOL_128
- (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
- (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
+ (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand"))
+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand"))))]
"<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
"")
;; The canonical form is to have the negated element first, so we need to
;; reverse arguments.
(define_expand "orc<mode>3"
- [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
+ [(set (match_operand:BOOL_128 0 "vlogical_operand")
(ior:BOOL_128
- (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
- (match_operand:BOOL_128 1 "vlogical_operand" "")))]
+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand"))
+ (match_operand:BOOL_128 1 "vlogical_operand")))]
"<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
"")
;; Set up a register with a value from the GOT table
(define_expand "movsi_got"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (unspec:SI [(match_operand:SI 1 "got_operand" "")
+ [(set (match_operand:SI 0 "gpc_reg_operand")
+ (unspec:SI [(match_operand:SI 1 "got_operand")
(match_dup 2)] UNSPEC_MOVSI_GOT))]
"DEFAULT_ABI == ABI_V4 && flag_pic == 1"
{
;; Used by sched, shorten_branches and final when the GOT pseudo reg
;; didn't get allocated to a hard register.
(define_split
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
- (match_operand:SI 2 "memory_operand" "")]
+ [(set (match_operand:SI 0 "gpc_reg_operand")
+ (unspec:SI [(match_operand:SI 1 "got_no_const_operand")
+ (match_operand:SI 2 "memory_operand")]
UNSPEC_MOVSI_GOT))]
"DEFAULT_ABI == ABI_V4
&& flag_pic == 1
;; sequence.
(define_split
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (match_operand:SI 1 "const_int_operand" ""))]
+ [(set (match_operand:SI 0 "gpc_reg_operand")
+ (match_operand:SI 1 "const_int_operand"))]
"(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
&& (INTVAL (operands[1]) & 0xffff) != 0"
[(set (match_dup 0)
"")
\f
(define_expand "mov<mode>"
- [(set (match_operand:INT 0 "general_operand" "")
- (match_operand:INT 1 "any_operand" ""))]
+ [(set (match_operand:INT 0 "general_operand")
+ (match_operand:INT 1 "any_operand"))]
""
{
rs6000_emit_move (operands[0], operands[1], <MODE>mode);
;; an integer register or memory, we store just the high-order 4 bits.
;; This lets us not shift in the most common case of CR0.
(define_expand "movcc"
- [(set (match_operand:CC 0 "nonimmediate_operand" "")
- (match_operand:CC 1 "nonimmediate_operand" ""))]
+ [(set (match_operand:CC 0 "nonimmediate_operand")
+ (match_operand:CC 1 "nonimmediate_operand"))]
""
"")
;; Move 32-bit binary/decimal floating point
(define_expand "mov<mode>"
- [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
- (match_operand:FMOVE32 1 "any_operand" ""))]
+ [(set (match_operand:FMOVE32 0 "nonimmediate_operand")
+ (match_operand:FMOVE32 1 "any_operand"))]
"<fmove_ok>"
{
rs6000_emit_move (operands[0], operands[1], <MODE>mode);
})
(define_split
- [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
- (match_operand:FMOVE32 1 "const_double_operand" ""))]
+ [(set (match_operand:FMOVE32 0 "gpc_reg_operand")
+ (match_operand:FMOVE32 1 "const_double_operand"))]
"reload_completed
&& ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
|| (GET_CODE (operands[0]) == SUBREG
\f
;; Move 64-bit binary/decimal floating point
(define_expand "mov<mode>"
- [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
- (match_operand:FMOVE64 1 "any_operand" ""))]
+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand")
+ (match_operand:FMOVE64 1 "any_operand"))]
""
{
rs6000_emit_move (operands[0], operands[1], <MODE>mode);
})
(define_split
- [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
- (match_operand:FMOVE64 1 "const_int_operand" ""))]
+ [(set (match_operand:FMOVE64 0 "gpc_reg_operand")
+ (match_operand:FMOVE64 1 "const_int_operand"))]
"! TARGET_POWERPC64 && reload_completed
&& ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
|| (GET_CODE (operands[0]) == SUBREG
})
(define_split
- [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
- (match_operand:FMOVE64 1 "const_double_operand" ""))]
+ [(set (match_operand:FMOVE64 0 "gpc_reg_operand")
+ (match_operand:FMOVE64 1 "const_double_operand"))]
"! TARGET_POWERPC64 && reload_completed
&& ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
|| (GET_CODE (operands[0]) == SUBREG
})
(define_split
- [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
- (match_operand:FMOVE64 1 "const_double_operand" ""))]
+ [(set (match_operand:FMOVE64 0 "gpc_reg_operand")
+ (match_operand:FMOVE64 1 "const_double_operand"))]
"TARGET_POWERPC64 && reload_completed
&& ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
|| (GET_CODE (operands[0]) == SUBREG
(set_attr "length" "4,4,4,4,4,8,12,16,4")])
\f
(define_expand "mov<mode>"
- [(set (match_operand:FMOVE128 0 "general_operand" "")
- (match_operand:FMOVE128 1 "any_operand" ""))]
+ [(set (match_operand:FMOVE128 0 "general_operand")
+ (match_operand:FMOVE128 1 "any_operand"))]
""
{
rs6000_emit_move (operands[0], operands[1], <MODE>mode);
[(set_attr "length" "20,20,16")])
(define_expand "extenddf<mode>2"
- [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
- (float_extend:FLOAT128 (match_operand:DF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:FLOAT128 0 "gpc_reg_operand")
+ (float_extend:FLOAT128 (match_operand:DF 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
if (FLOAT128_IEEE_P (<MODE>mode))
})
(define_expand "extendsf<mode>2"
- [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
- (float_extend:FLOAT128 (match_operand:SF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:FLOAT128 0 "gpc_reg_operand")
+ (float_extend:FLOAT128 (match_operand:SF 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
if (FLOAT128_IEEE_P (<MODE>mode))
})
(define_expand "trunc<mode>df2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "")
- (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:DF 0 "gpc_reg_operand")
+ (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
if (FLOAT128_IEEE_P (<MODE>mode))
(set_attr "fp_type" "fp_addsub_d")])
(define_expand "trunc<mode>sf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "")
- (float_truncate:SF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand")
+ (float_truncate:SF (match_operand:FLOAT128 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
if (FLOAT128_IEEE_P (<MODE>mode))
(set_attr "length" "20")])
(define_expand "fix_trunc<mode>si2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (fix:SI (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SI 0 "gpc_reg_operand")
+ (fix:SI (match_operand:FLOAT128 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
rtx op0 = operands[0];
})
(define_expand "fix_trunc<mode>si2_fprs"
- [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (fix:SI (match_operand:IBM128 1 "gpc_reg_operand" "")))
+ [(parallel [(set (match_operand:SI 0 "gpc_reg_operand")
+ (fix:SI (match_operand:IBM128 1 "gpc_reg_operand")))
(clobber (match_dup 2))
(clobber (match_dup 3))
(clobber (match_dup 4))
})
(define_expand "fix_trunc<mode>di2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (fix:DI (match_operand:IEEE128 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:DI 0 "gpc_reg_operand")
+ (fix:DI (match_operand:IEEE128 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
if (!TARGET_FLOAT128_HW)
})
(define_expand "fixuns_trunc<IEEE128:mode><SDI:mode>2"
- [(set (match_operand:SDI 0 "gpc_reg_operand" "")
- (unsigned_fix:SDI (match_operand:IEEE128 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SDI 0 "gpc_reg_operand")
+ (unsigned_fix:SDI (match_operand:IEEE128 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], true);
})
(define_expand "floatdi<mode>2"
- [(set (match_operand:IEEE128 0 "gpc_reg_operand" "")
- (float:IEEE128 (match_operand:DI 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:IEEE128 0 "gpc_reg_operand")
+ (float:IEEE128 (match_operand:DI 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
if (!TARGET_FLOAT128_HW)
})
(define_expand "floatunsdi<IEEE128:mode>2"
- [(set (match_operand:IEEE128 0 "gpc_reg_operand" "")
- (unsigned_float:IEEE128 (match_operand:DI 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:IEEE128 0 "gpc_reg_operand")
+ (unsigned_float:IEEE128 (match_operand:DI 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
if (!TARGET_FLOAT128_HW)
})
(define_expand "floatuns<IEEE128:mode>2"
- [(set (match_operand:IEEE128 0 "gpc_reg_operand" "")
- (unsigned_float:IEEE128 (match_operand:SI 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:IEEE128 0 "gpc_reg_operand")
+ (unsigned_float:IEEE128 (match_operand:SI 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
rtx op0 = operands[0];
})
(define_expand "neg<mode>2"
- [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
- (neg:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:FLOAT128 0 "gpc_reg_operand")
+ (neg:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand")))]
"FLOAT128_IEEE_P (<MODE>mode)
|| (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)"
{
(set_attr "length" "8")])
(define_expand "abs<mode>2"
- [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
- (abs:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:FLOAT128 0 "gpc_reg_operand")
+ (abs:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand")))]
"FLOAT128_IEEE_P (<MODE>mode)
|| (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)"
{
})
(define_expand "abs<mode>2_internal"
- [(set (match_operand:IBM128 0 "gpc_reg_operand" "")
- (match_operand:IBM128 1 "gpc_reg_operand" ""))
+ [(set (match_operand:IBM128 0 "gpc_reg_operand")
+ (match_operand:IBM128 1 "gpc_reg_operand"))
(set (match_dup 3) (match_dup 5))
(set (match_dup 5) (abs:DF (match_dup 5)))
(set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
(set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
- (label_ref (match_operand 2 "" ""))
+ (label_ref (match_operand 2 ""))
(pc)))
(set (match_dup 6) (neg:DF (match_dup 6)))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
;; register
(define_expand "ieee_128bit_negative_zero"
- [(set (match_operand:V16QI 0 "register_operand" "") (match_dup 1))]
+ [(set (match_operand:V16QI 0 "register_operand") (match_dup 1))]
"TARGET_FLOAT128_TYPE"
{
rtvec v = rtvec_alloc (16);
;; We use expand to convert from IBM double double to IEEE 128-bit
;; and trunc for the opposite.
(define_expand "extendiftf2"
- [(set (match_operand:TF 0 "gpc_reg_operand" "")
- (float_extend:TF (match_operand:IF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:TF 0 "gpc_reg_operand")
+ (float_extend:TF (match_operand:IF 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
})
(define_expand "extendifkf2"
- [(set (match_operand:KF 0 "gpc_reg_operand" "")
- (float_extend:KF (match_operand:IF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:KF 0 "gpc_reg_operand")
+ (float_extend:KF (match_operand:IF 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
})
(define_expand "extendtfkf2"
- [(set (match_operand:KF 0 "gpc_reg_operand" "")
- (float_extend:KF (match_operand:TF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:KF 0 "gpc_reg_operand")
+ (float_extend:KF (match_operand:TF 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
})
(define_expand "trunciftf2"
- [(set (match_operand:IF 0 "gpc_reg_operand" "")
- (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:IF 0 "gpc_reg_operand")
+ (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
})
(define_expand "truncifkf2"
- [(set (match_operand:IF 0 "gpc_reg_operand" "")
- (float_truncate:IF (match_operand:KF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:IF 0 "gpc_reg_operand")
+ (float_truncate:IF (match_operand:KF 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
})
(define_expand "trunckftf2"
- [(set (match_operand:TF 0 "gpc_reg_operand" "")
- (float_truncate:TF (match_operand:KF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:TF 0 "gpc_reg_operand")
+ (float_truncate:TF (match_operand:KF 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
})
(define_expand "trunctfif2"
- [(set (match_operand:IF 0 "gpc_reg_operand" "")
- (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:IF 0 "gpc_reg_operand")
+ (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
(set_attr "type" "three")])
(define_split
- [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
- (match_operand:FMOVE128_GPR 1 "input_operand" ""))]
+ [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand")
+ (match_operand:FMOVE128_GPR 1 "input_operand"))]
"reload_completed
&& (int_reg_operand (operands[0], <MODE>mode)
|| int_reg_operand (operands[1], <MODE>mode))
(set_attr "size" "64")])
(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (match_operand:DI 1 "const_int_operand" ""))]
+ [(set (match_operand:DI 0 "gpc_reg_operand")
+ (match_operand:DI 1 "const_int_operand"))]
"! TARGET_POWERPC64 && reload_completed
&& gpr_or_gpr_p (operands[0], operands[1])
&& !direct_move_p (operands[0], operands[1])"
})
(define_split
- [(set (match_operand:DIFD 0 "nonimmediate_operand" "")
- (match_operand:DIFD 1 "input_operand" ""))]
+ [(set (match_operand:DIFD 0 "nonimmediate_operand")
+ (match_operand:DIFD 1 "input_operand"))]
"reload_completed && !TARGET_POWERPC64
&& gpr_or_gpr_p (operands[0], operands[1])
&& !direct_move_p (operands[0], operands[1])"
;; When non-easy constants can go in the TOC, this should use
;; easy_fp_constant predicate.
(define_split
- [(set (match_operand:DI 0 "int_reg_operand_not_pseudo" "")
- (match_operand:DI 1 "const_int_operand" ""))]
+ [(set (match_operand:DI 0 "int_reg_operand_not_pseudo")
+ (match_operand:DI 1 "const_int_operand"))]
"TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
[(set (match_dup 0) (match_dup 2))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
})
(define_split
- [(set (match_operand:DI 0 "int_reg_operand_not_pseudo" "")
- (match_operand:DI 1 "const_scalar_int_operand" ""))]
+ [(set (match_operand:DI 0 "int_reg_operand_not_pseudo")
+ (match_operand:DI 1 "const_scalar_int_operand"))]
"TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
[(set (match_dup 0) (match_dup 2))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
})
(define_split
- [(set (match_operand:DI 0 "altivec_register_operand" "")
- (match_operand:DI 1 "s5bit_cint_operand" ""))]
+ [(set (match_operand:DI 0 "altivec_register_operand")
+ (match_operand:DI 1 "s5bit_cint_operand"))]
"TARGET_VSX && reload_completed"
[(const_int 0)]
{
;; Split integer constants that can be loaded with XXSPLTIB and a
;; sign extend operation.
(define_split
- [(set (match_operand:INT_ISA3 0 "altivec_register_operand" "")
- (match_operand:INT_ISA3 1 "xxspltib_constant_split" ""))]
+ [(set (match_operand:INT_ISA3 0 "altivec_register_operand")
+ (match_operand:INT_ISA3 1 "xxspltib_constant_split"))]
"TARGET_P9_VECTOR && reload_completed"
[(const_int 0)]
{
(set_attr "length" "8")])
(define_split
- [(set (match_operand:TI2 0 "int_reg_operand" "")
- (match_operand:TI2 1 "const_scalar_int_operand" ""))]
+ [(set (match_operand:TI2 0 "int_reg_operand")
+ (match_operand:TI2 1 "const_scalar_int_operand"))]
"TARGET_POWERPC64
&& (VECTOR_MEM_NONE_P (<MODE>mode)
|| (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
})
(define_split
- [(set (match_operand:TI2 0 "nonimmediate_operand" "")
- (match_operand:TI2 1 "input_operand" ""))]
+ [(set (match_operand:TI2 0 "nonimmediate_operand")
+ (match_operand:TI2 1 "input_operand"))]
"reload_completed
&& gpr_or_gpr_p (operands[0], operands[1])
&& !direct_move_p (operands[0], operands[1])
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
\f
(define_expand "setmemsi"
- [(parallel [(set (match_operand:BLK 0 "" "")
- (match_operand 2 "const_int_operand" ""))
- (use (match_operand:SI 1 "" ""))
- (use (match_operand:SI 3 "" ""))])]
+ [(parallel [(set (match_operand:BLK 0 "")
+ (match_operand 2 "const_int_operand"))
+ (use (match_operand:SI 1 ""))
+ (use (match_operand:SI 3 ""))])]
""
{
/* If value to set is not zero, use the library routine. */
;; Argument 3 is the alignment
(define_expand "movmemsi"
- [(parallel [(set (match_operand:BLK 0 "" "")
- (match_operand:BLK 1 "" ""))
- (use (match_operand:SI 2 "" ""))
- (use (match_operand:SI 3 "" ""))])]
+ [(parallel [(set (match_operand:BLK 0 "")
+ (match_operand:BLK 1 ""))
+ (use (match_operand:SI 2 ""))
+ (use (match_operand:SI 3 ""))])]
""
{
if (expand_block_move (operands))
;; Also this optimization interferes with scalars going into
;; altivec registers (the code does reloading through the FPRs).
(define_peephole2
- [(set (match_operand:DF 0 "gpc_reg_operand" "")
- (match_operand:DF 1 "any_operand" ""))
- (set (match_operand:DF 2 "gpc_reg_operand" "")
+ [(set (match_operand:DF 0 "gpc_reg_operand")
+ (match_operand:DF 1 "any_operand"))
+ (set (match_operand:DF 2 "gpc_reg_operand")
(match_dup 0))]
"!TARGET_VSX
&& peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) (match_dup 1))])
(define_peephole2
- [(set (match_operand:SF 0 "gpc_reg_operand" "")
- (match_operand:SF 1 "any_operand" ""))
- (set (match_operand:SF 2 "gpc_reg_operand" "")
+ [(set (match_operand:SF 0 "gpc_reg_operand")
+ (match_operand:SF 1 "any_operand"))
+ (set (match_operand:SF 2 "gpc_reg_operand")
(match_dup 0))]
"!TARGET_P8_VECTOR
&& peep2_reg_dead_p (2, operands[0])"
"add %0,%1,%2@tls")
(define_expand "tls_get_tpointer"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
+ [(set (match_operand:SI 0 "gpc_reg_operand")
(unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
"TARGET_XCOFF && HAVE_AS_TLS"
{
"bla __get_tpointer")
(define_expand "tls_get_addr<mode>"
- [(set (match_operand:P 0 "gpc_reg_operand" "")
- (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
- (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
+ [(set (match_operand:P 0 "gpc_reg_operand")
+ (unspec:P [(match_operand:P 1 "gpc_reg_operand")
+ (match_operand:P 2 "gpc_reg_operand")] UNSPEC_TLSTLS))]
"TARGET_XCOFF && HAVE_AS_TLS"
{
emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
;; the constant size. The value is forced into a register if necessary.
;;
(define_expand "allocate_stack"
- [(set (match_operand 0 "gpc_reg_operand" "")
- (minus (reg 1) (match_operand 1 "reg_or_cint_operand" "")))
+ [(set (match_operand 0 "gpc_reg_operand")
+ (minus (reg 1) (match_operand 1 "reg_or_cint_operand")))
(set (reg 1)
(minus (reg 1) (match_dup 1)))]
""
;; save area is a memory location.
(define_expand "save_stack_function"
- [(match_operand 0 "any_operand" "")
- (match_operand 1 "any_operand" "")]
+ [(match_operand 0 "any_operand")
+ (match_operand 1 "any_operand")]
""
"DONE;")
(define_expand "restore_stack_function"
- [(match_operand 0 "any_operand" "")
- (match_operand 1 "any_operand" "")]
+ [(match_operand 0 "any_operand")
+ (match_operand 1 "any_operand")]
""
"DONE;")
[(set (match_dup 2) (match_dup 3))
(set (match_dup 4) (match_dup 2))
(match_dup 5)
- (set (match_operand 0 "register_operand" "")
- (match_operand 1 "register_operand" ""))]
+ (set (match_operand 0 "register_operand")
+ (match_operand 1 "register_operand"))]
""
{
rtvec p;
(define_expand "save_stack_nonlocal"
[(set (match_dup 3) (match_dup 4))
- (set (match_operand 0 "memory_operand" "") (match_dup 3))
- (set (match_dup 2) (match_operand 1 "register_operand" ""))]
+ (set (match_operand 0 "memory_operand") (match_dup 3))
+ (set (match_dup 2) (match_operand 1 "register_operand"))]
""
{
int units_per_word = (TARGET_32BIT) ? 4 : 8;
})
(define_expand "restore_stack_nonlocal"
- [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
+ [(set (match_dup 2) (match_operand 1 "memory_operand"))
(set (match_dup 3) (match_dup 4))
(set (match_dup 5) (match_dup 2))
(match_dup 6)
- (set (match_operand 0 "register_operand" "") (match_dup 3))]
+ (set (match_operand 0 "register_operand") (match_dup 3))]
""
{
int units_per_word = (TARGET_32BIT) ? 4 : 8;
(define_expand "load_toc_v4_PIC_1b"
[(parallel [(set (reg:SI LR_REGNO)
(unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
- (label_ref (match_operand 1 "" ""))]
+ (label_ref (match_operand 1 ""))]
UNSPEC_TOCPTR))
(match_dup 1)])]
"TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
;; On Darwin, we need to reload the picbase.
(define_expand "builtin_setjmp_receiver"
- [(use (label_ref (match_operand 0 "" "")))]
+ [(use (label_ref (match_operand 0 "")))]
"(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
|| (TARGET_TOC && TARGET_MINIMAL_TOC)
|| (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
\f
;; Call and call_value insns
(define_expand "call"
- [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
- (match_operand 1 "" ""))
- (use (match_operand 2 "" ""))
+ [(parallel [(call (mem:SI (match_operand 0 "address_operand"))
+ (match_operand 1 ""))
+ (use (match_operand 2 ""))
(clobber (reg:SI LR_REGNO))])]
""
{
})
(define_expand "call_value"
- [(parallel [(set (match_operand 0 "" "")
- (call (mem:SI (match_operand 1 "address_operand" ""))
- (match_operand 2 "" "")))
- (use (match_operand 3 "" ""))
+ [(parallel [(set (match_operand 0 "")
+ (call (mem:SI (match_operand 1 "address_operand"))
+ (match_operand 2 "")))
+ (use (match_operand 3 ""))
(clobber (reg:SI LR_REGNO))])]
""
{
;; Call subroutine returning any type.
(define_expand "untyped_call"
- [(parallel [(call (match_operand 0 "" "")
+ [(parallel [(call (match_operand 0 "")
(const_int 0))
- (match_operand 1 "" "")
- (match_operand 2 "" "")])]
+ (match_operand 1 "")
+ (match_operand 2 "")])]
""
{
int i;
;; sibling call patterns
(define_expand "sibcall"
- [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
- (match_operand 1 "" ""))
- (use (match_operand 2 "" ""))
+ [(parallel [(call (mem:SI (match_operand 0 "address_operand"))
+ (match_operand 1 ""))
+ (use (match_operand 2 ""))
(simple_return)])]
""
{
})
(define_expand "sibcall_value"
- [(parallel [(set (match_operand 0 "register_operand" "")
- (call (mem:SI (match_operand 1 "address_operand" ""))
- (match_operand 2 "" "")))
- (use (match_operand 3 "" ""))
+ [(parallel [(set (match_operand 0 "register_operand")
+ (call (mem:SI (match_operand 1 "address_operand"))
+ (match_operand 2 "")))
+ (use (match_operand 3 ""))
(simple_return)])]
""
{
(define_expand "cbranch<mode>4"
[(use (match_operator 0 "comparison_operator"
- [(match_operand:GPR 1 "gpc_reg_operand" "")
- (match_operand:GPR 2 "reg_or_short_operand" "")]))
- (use (match_operand 3 ""))]
+ [(match_operand:GPR 1 "gpc_reg_operand")
+ (match_operand:GPR 2 "reg_or_short_operand")]))
+ (use (match_operand 3))]
""
{
/* Take care of the possibility that operands[2] might be negative but
(define_expand "cbranch<mode>4"
[(use (match_operator 0 "comparison_operator"
- [(match_operand:FP 1 "gpc_reg_operand" "")
- (match_operand:FP 2 "gpc_reg_operand" "")]))
- (use (match_operand 3 ""))]
+ [(match_operand:FP 1 "gpc_reg_operand")
+ (match_operand:FP 2 "gpc_reg_operand")]))
+ (use (match_operand 3))]
""
{
rs6000_emit_cbranch (<MODE>mode, operands);
(define_peephole2
[(set (match_operand:SI 0 "register_operand")
- (match_operand:SI 1 "logical_const_operand" ""))
+ (match_operand:SI 1 "logical_const_operand"))
(set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
[(match_dup 0)
- (match_operand:SI 2 "logical_const_operand" "")]))
- (set (match_operand:CC 4 "cc_reg_operand" "")
- (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
+ (match_operand:SI 2 "logical_const_operand")]))
+ (set (match_operand:CC 4 "cc_reg_operand")
+ (compare:CC (match_operand:SI 5 "gpc_reg_operand")
(match_dup 0)))
(set (pc)
(if_then_else (match_operator 6 "equality_operator"
[(match_dup 4) (const_int 0)])
- (match_operand 7 "" "")
- (match_operand 8 "" "")))]
+ (match_operand 7 "")
+ (match_operand 8 "")))]
"peep2_reg_dead_p (3, operands[0])
&& peep2_reg_dead_p (4, operands[4])
&& REGNO (operands[0]) != REGNO (operands[5])"
[(set_attr "length" "8")])
(define_split
- [(set (match_operand:CC 3 "cc_reg_operand" "")
- (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "short_cint_operand" "")))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
+ [(set (match_operand:CC 3 "cc_reg_operand")
+ (compare:CC (match_operand:SI 1 "gpc_reg_operand")
+ (match_operand:SI 2 "short_cint_operand")))
+ (set (match_operand:SI 0 "gpc_reg_operand")
+ (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand")))]
""
[(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
(define_split
- [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
- (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "u_short_cint_operand" "")))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
+ [(set (match_operand:CCUNS 3 "cc_reg_operand")
+ (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand")
+ (match_operand:SI 2 "u_short_cint_operand")))
+ (set (match_operand:SI 0 "gpc_reg_operand")
+ (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand")))]
""
[(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
(set_attr "length" "8,16")])
(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+ [(set (match_operand:CC 0 "cc_reg_not_cr0_operand")
(compare:CC (match_operator:SI 1 "scc_comparison_operator"
- [(match_operand 2 "cc_reg_operand" "")
+ [(match_operand 2 "cc_reg_operand")
(const_int 0)])
(const_int 0)))
- (set (match_operand:SI 3 "gpc_reg_operand" "")
+ (set (match_operand:SI 3 "gpc_reg_operand")
(match_op_dup 1 [(match_dup 2) (const_int 0)]))]
"TARGET_32BIT && reload_completed"
[(set (match_dup 3)
; faster; for instance, on the 601 and 750.
(define_expand "movsi_to_cr_one"
- [(set (match_operand:CC 0 "cc_reg_operand" "")
- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
+ [(set (match_operand:CC 0 "cc_reg_operand")
+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand")
(match_dup 2)] UNSPEC_MOVESI_TO_CR))]
""
"operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
; This is used in compiling the unwind routines.
(define_expand "eh_return"
- [(use (match_operand 0 "general_operand" ""))]
+ [(use (match_operand 0 "general_operand"))]
""
{
if (TARGET_32BIT)
"#")
(define_split
- [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
- (clobber (match_scratch 1 ""))]
+ [(unspec_volatile [(match_operand 0 "register_operand")] UNSPECV_EH_RR)
+ (clobber (match_scratch 1))]
"reload_completed"
[(const_int 0)]
{
;; Note that the conditions for expansion are in the FMA_F iterator.
(define_expand "fma<mode>4"
- [(set (match_operand:FMA_F 0 "gpc_reg_operand" "")
+ [(set (match_operand:FMA_F 0 "gpc_reg_operand")
(fma:FMA_F
- (match_operand:FMA_F 1 "gpc_reg_operand" "")
- (match_operand:FMA_F 2 "gpc_reg_operand" "")
- (match_operand:FMA_F 3 "gpc_reg_operand" "")))]
+ (match_operand:FMA_F 1 "gpc_reg_operand")
+ (match_operand:FMA_F 2 "gpc_reg_operand")
+ (match_operand:FMA_F 3 "gpc_reg_operand")))]
""
"")
; Altivec only has fma and nfms.
(define_expand "fms<mode>4"
- [(set (match_operand:FMA_F 0 "gpc_reg_operand" "")
+ [(set (match_operand:FMA_F 0 "gpc_reg_operand")
(fma:FMA_F
- (match_operand:FMA_F 1 "gpc_reg_operand" "")
- (match_operand:FMA_F 2 "gpc_reg_operand" "")
- (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand" ""))))]
+ (match_operand:FMA_F 1 "gpc_reg_operand")
+ (match_operand:FMA_F 2 "gpc_reg_operand")
+ (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand"))))]
"!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
"")
;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
(define_expand "fnma<mode>4"
- [(set (match_operand:FMA_F 0 "gpc_reg_operand" "")
+ [(set (match_operand:FMA_F 0 "gpc_reg_operand")
(neg:FMA_F
(fma:FMA_F
- (match_operand:FMA_F 1 "gpc_reg_operand" "")
- (match_operand:FMA_F 2 "gpc_reg_operand" "")
- (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand" "")))))]
+ (match_operand:FMA_F 1 "gpc_reg_operand")
+ (match_operand:FMA_F 2 "gpc_reg_operand")
+ (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand")))))]
"!HONOR_SIGNED_ZEROS (<MODE>mode)"
"")
;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
(define_expand "fnms<mode>4"
- [(set (match_operand:FMA_F 0 "gpc_reg_operand" "")
+ [(set (match_operand:FMA_F 0 "gpc_reg_operand")
(neg:FMA_F
(fma:FMA_F
- (match_operand:FMA_F 1 "gpc_reg_operand" "")
- (match_operand:FMA_F 2 "gpc_reg_operand" "")
- (match_operand:FMA_F 3 "gpc_reg_operand" ""))))]
+ (match_operand:FMA_F 1 "gpc_reg_operand")
+ (match_operand:FMA_F 2 "gpc_reg_operand")
+ (match_operand:FMA_F 3 "gpc_reg_operand"))))]
"!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
"")
; Not an official optab name, but used from builtins.
(define_expand "nfma<mode>4"
- [(set (match_operand:FMA_F 0 "gpc_reg_operand" "")
+ [(set (match_operand:FMA_F 0 "gpc_reg_operand")
(neg:FMA_F
(fma:FMA_F
- (match_operand:FMA_F 1 "gpc_reg_operand" "")
- (match_operand:FMA_F 2 "gpc_reg_operand" "")
- (match_operand:FMA_F 3 "gpc_reg_operand" ""))))]
+ (match_operand:FMA_F 1 "gpc_reg_operand")
+ (match_operand:FMA_F 2 "gpc_reg_operand")
+ (match_operand:FMA_F 3 "gpc_reg_operand"))))]
"!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
"")
; Not an official optab name, but used from builtins.
(define_expand "nfms<mode>4"
- [(set (match_operand:FMA_F 0 "gpc_reg_operand" "")
+ [(set (match_operand:FMA_F 0 "gpc_reg_operand")
(neg:FMA_F
(fma:FMA_F
- (match_operand:FMA_F 1 "gpc_reg_operand" "")
- (match_operand:FMA_F 2 "gpc_reg_operand" "")
- (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand" "")))))]
+ (match_operand:FMA_F 1 "gpc_reg_operand")
+ (match_operand:FMA_F 2 "gpc_reg_operand")
+ (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand")))))]
""
"")
\f
(define_expand "rs6000_get_timebase"
- [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
+ [(use (match_operand:DI 0 "gpc_reg_operand"))]
""
{
if (TARGET_POWERPC64)
;; (addis followed by load) even on power8.
(define_split
- [(set (match_operand:INT1 0 "toc_fusion_or_p9_reg_operand" "")
- (match_operand:INT1 1 "toc_fusion_mem_raw" ""))]
+ [(set (match_operand:INT1 0 "toc_fusion_or_p9_reg_operand")
+ (match_operand:INT1 1 "toc_fusion_mem_raw"))]
"TARGET_TOC_FUSION_INT && can_create_pseudo_p ()"
[(parallel [(set (match_dup 0) (match_dup 2))
(unspec [(const_int 0)] UNSPEC_FUSION_ADDIS)
;; insn
(define_peephole2
- [(set (match_operand:P 0 "base_reg_operand" "")
- (match_operand:P 1 "fusion_gpr_addis" ""))
- (set (match_operand:INT1 2 "base_reg_operand" "")
- (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
+ [(set (match_operand:P 0 "base_reg_operand")
+ (match_operand:P 1 "fusion_gpr_addis"))
+ (set (match_operand:INT1 2 "base_reg_operand")
+ (match_operand:INT1 3 "fusion_gpr_mem_load"))]
"TARGET_P8_FUSION
&& fusion_gpr_load_p (operands[0], operands[1], operands[2],
operands[3])"
;; ISA 3.0 (power9) fusion support
;; Merge addis with floating load/store to FPRs (or GPRs).
(define_peephole2
- [(set (match_operand:P 0 "base_reg_operand" "")
- (match_operand:P 1 "fusion_gpr_addis" ""))
- (set (match_operand:SFDF 2 "toc_fusion_or_p9_reg_operand" "")
- (match_operand:SFDF 3 "fusion_offsettable_mem_operand" ""))]
+ [(set (match_operand:P 0 "base_reg_operand")
+ (match_operand:P 1 "fusion_gpr_addis"))
+ (set (match_operand:SFDF 2 "toc_fusion_or_p9_reg_operand")
+ (match_operand:SFDF 3 "fusion_offsettable_mem_operand"))]
"TARGET_P9_FUSION && peep2_reg_dead_p (2, operands[0])
&& fusion_p9_p (operands[0], operands[1], operands[2], operands[3])"
[(const_int 0)]
})
(define_peephole2
- [(set (match_operand:P 0 "base_reg_operand" "")
- (match_operand:P 1 "fusion_gpr_addis" ""))
- (set (match_operand:SFDF 2 "offsettable_mem_operand" "")
- (match_operand:SFDF 3 "toc_fusion_or_p9_reg_operand" ""))]
+ [(set (match_operand:P 0 "base_reg_operand")
+ (match_operand:P 1 "fusion_gpr_addis"))
+ (set (match_operand:SFDF 2 "offsettable_mem_operand")
+ (match_operand:SFDF 3 "toc_fusion_or_p9_reg_operand"))]
"TARGET_P9_FUSION && peep2_reg_dead_p (2, operands[0])
&& fusion_p9_p (operands[0], operands[1], operands[2], operands[3])
&& !rtx_equal_p (operands[0], operands[3])"
})
(define_peephole2
- [(set (match_operand:SDI 0 "int_reg_operand" "")
- (match_operand:SDI 1 "upper16_cint_operand" ""))
+ [(set (match_operand:SDI 0 "int_reg_operand")
+ (match_operand:SDI 1 "upper16_cint_operand"))
(set (match_dup 0)
(ior:SDI (match_dup 0)
- (match_operand:SDI 2 "u_short_cint_operand" "")))]
+ (match_operand:SDI 2 "u_short_cint_operand")))]
"TARGET_P9_FUSION"
[(set (match_dup 0)
(unspec:SDI [(match_dup 1)
(match_dup 2)] UNSPEC_FUSION_P9))])
(define_peephole2
- [(set (match_operand:SDI 0 "int_reg_operand" "")
- (match_operand:SDI 1 "upper16_cint_operand" ""))
- (set (match_operand:SDI 2 "int_reg_operand" "")
+ [(set (match_operand:SDI 0 "int_reg_operand")
+ (match_operand:SDI 1 "upper16_cint_operand"))
+ (set (match_operand:SDI 2 "int_reg_operand")
(ior:SDI (match_dup 0)
- (match_operand:SDI 3 "u_short_cint_operand" "")))]
+ (match_operand:SDI 3 "u_short_cint_operand")))]
"TARGET_P9_FUSION
&& !rtx_equal_p (operands[0], operands[2])
&& peep2_reg_dead_p (2, operands[0])"
(KF "DI")])
(define_expand "unpack<mode>"
- [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "")
+ [(set (match_operand:<FP128_64> 0 "nonimmediate_operand")
(unspec:<FP128_64>
- [(match_operand:FMOVE128 1 "register_operand" "")
- (match_operand:QI 2 "const_0_to_1_operand" "")]
+ [(match_operand:FMOVE128 1 "register_operand")
+ (match_operand:QI 2 "const_0_to_1_operand")]
UNSPEC_UNPACK_128BIT))]
"FLOAT128_2REG_P (<MODE>mode)"
"")
(ior "logical_operand") (xor "logical_operand") (and "and_operand")])
(define_expand "mem_thread_fence"
- [(match_operand:SI 0 "const_int_operand" "")] ;; model
+ [(match_operand:SI 0 "const_int_operand")] ;; model
""
{
enum memmodel model = memmodel_base (INTVAL (operands[0]));
(set_attr "length" "4")])
(define_expand "atomic_load<mode>"
- [(set (match_operand:AINT 0 "register_operand" "") ;; output
- (match_operand:AINT 1 "memory_operand" "")) ;; memory
- (use (match_operand:SI 2 "const_int_operand" ""))] ;; model
+ [(set (match_operand:AINT 0 "register_operand") ;; output
+ (match_operand:AINT 1 "memory_operand")) ;; memory
+ (use (match_operand:SI 2 "const_int_operand"))] ;; model
""
{
if (<MODE>mode == TImode && !TARGET_SYNC_TI)
(set_attr "length" "4")])
(define_expand "atomic_store<mode>"
- [(set (match_operand:AINT 0 "memory_operand" "") ;; memory
- (match_operand:AINT 1 "register_operand" "")) ;; input
- (use (match_operand:SI 2 "const_int_operand" ""))] ;; model
+ [(set (match_operand:AINT 0 "memory_operand") ;; memory
+ (match_operand:AINT 1 "register_operand")) ;; input
+ (use (match_operand:SI 2 "const_int_operand"))] ;; model
""
{
if (<MODE>mode == TImode && !TARGET_SYNC_TI)
;; is indexed or indirect before register allocation.
(define_expand "load_lockedti"
- [(use (match_operand:TI 0 "quad_int_reg_operand" ""))
- (use (match_operand:TI 1 "memory_operand" ""))]
+ [(use (match_operand:TI 0 "quad_int_reg_operand"))
+ (use (match_operand:TI 1 "memory_operand"))]
"TARGET_SYNC_TI"
{
rtx op0 = operands[0];
;; is indexed or indirect before register allocation.
(define_expand "store_conditionalti"
- [(use (match_operand:CC 0 "cc_reg_operand" ""))
- (use (match_operand:TI 1 "memory_operand" ""))
- (use (match_operand:TI 2 "quad_int_reg_operand" ""))]
+ [(use (match_operand:CC 0 "cc_reg_operand"))
+ (use (match_operand:TI 1 "memory_operand"))
+ (use (match_operand:TI 2 "quad_int_reg_operand"))]
"TARGET_SYNC_TI"
{
rtx op0 = operands[0];
[(set_attr "type" "store_c")])
(define_expand "atomic_compare_and_swap<mode>"
- [(match_operand:SI 0 "int_reg_operand" "") ;; bool out
- (match_operand:AINT 1 "int_reg_operand" "") ;; val out
- (match_operand:AINT 2 "memory_operand" "") ;; memory
- (match_operand:AINT 3 "reg_or_short_operand" "") ;; expected
- (match_operand:AINT 4 "int_reg_operand" "") ;; desired
- (match_operand:SI 5 "const_int_operand" "") ;; is_weak
- (match_operand:SI 6 "const_int_operand" "") ;; model succ
- (match_operand:SI 7 "const_int_operand" "")] ;; model fail
+ [(match_operand:SI 0 "int_reg_operand") ;; bool out
+ (match_operand:AINT 1 "int_reg_operand") ;; val out
+ (match_operand:AINT 2 "memory_operand") ;; memory
+ (match_operand:AINT 3 "reg_or_short_operand") ;; expected
+ (match_operand:AINT 4 "int_reg_operand") ;; desired
+ (match_operand:SI 5 "const_int_operand") ;; is_weak
+ (match_operand:SI 6 "const_int_operand") ;; model succ
+ (match_operand:SI 7 "const_int_operand")] ;; model fail
""
{
rs6000_expand_atomic_compare_and_swap (operands);
})
(define_expand "atomic_exchange<mode>"
- [(match_operand:AINT 0 "int_reg_operand" "") ;; output
- (match_operand:AINT 1 "memory_operand" "") ;; memory
- (match_operand:AINT 2 "int_reg_operand" "") ;; input
- (match_operand:SI 3 "const_int_operand" "")] ;; model
+ [(match_operand:AINT 0 "int_reg_operand") ;; output
+ (match_operand:AINT 1 "memory_operand") ;; memory
+ (match_operand:AINT 2 "int_reg_operand") ;; input
+ (match_operand:SI 3 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_exchange (operands);
})
(define_expand "atomic_<fetchop_name><mode>"
- [(match_operand:AINT 0 "memory_operand" "") ;; memory
+ [(match_operand:AINT 0 "memory_operand") ;; memory
(FETCHOP:AINT (match_dup 0)
- (match_operand:AINT 1 "<fetchop_pred>" "")) ;; operand
- (match_operand:SI 2 "const_int_operand" "")] ;; model
+ (match_operand:AINT 1 "<fetchop_pred>")) ;; operand
+ (match_operand:SI 2 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_op (<CODE>, operands[0], operands[1],
})
(define_expand "atomic_nand<mode>"
- [(match_operand:AINT 0 "memory_operand" "") ;; memory
- (match_operand:AINT 1 "int_reg_operand" "") ;; operand
- (match_operand:SI 2 "const_int_operand" "")] ;; model
+ [(match_operand:AINT 0 "memory_operand") ;; memory
+ (match_operand:AINT 1 "int_reg_operand") ;; operand
+ (match_operand:SI 2 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_op (NOT, operands[0], operands[1],
})
(define_expand "atomic_fetch_<fetchop_name><mode>"
- [(match_operand:AINT 0 "int_reg_operand" "") ;; output
- (match_operand:AINT 1 "memory_operand" "") ;; memory
+ [(match_operand:AINT 0 "int_reg_operand") ;; output
+ (match_operand:AINT 1 "memory_operand") ;; memory
(FETCHOP:AINT (match_dup 1)
- (match_operand:AINT 2 "<fetchop_pred>" "")) ;; operand
- (match_operand:SI 3 "const_int_operand" "")] ;; model
+ (match_operand:AINT 2 "<fetchop_pred>")) ;; operand
+ (match_operand:SI 3 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_op (<CODE>, operands[1], operands[2],
})
(define_expand "atomic_fetch_nand<mode>"
- [(match_operand:AINT 0 "int_reg_operand" "") ;; output
- (match_operand:AINT 1 "memory_operand" "") ;; memory
- (match_operand:AINT 2 "int_reg_operand" "") ;; operand
- (match_operand:SI 3 "const_int_operand" "")] ;; model
+ [(match_operand:AINT 0 "int_reg_operand") ;; output
+ (match_operand:AINT 1 "memory_operand") ;; memory
+ (match_operand:AINT 2 "int_reg_operand") ;; operand
+ (match_operand:SI 3 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_op (NOT, operands[1], operands[2],
})
(define_expand "atomic_<fetchop_name>_fetch<mode>"
- [(match_operand:AINT 0 "int_reg_operand" "") ;; output
- (match_operand:AINT 1 "memory_operand" "") ;; memory
+ [(match_operand:AINT 0 "int_reg_operand") ;; output
+ (match_operand:AINT 1 "memory_operand") ;; memory
(FETCHOP:AINT (match_dup 1)
- (match_operand:AINT 2 "<fetchop_pred>" "")) ;; operand
- (match_operand:SI 3 "const_int_operand" "")] ;; model
+ (match_operand:AINT 2 "<fetchop_pred>")) ;; operand
+ (match_operand:SI 3 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_op (<CODE>, operands[1], operands[2],
})
(define_expand "atomic_nand_fetch<mode>"
- [(match_operand:AINT 0 "int_reg_operand" "") ;; output
- (match_operand:AINT 1 "memory_operand" "") ;; memory
- (match_operand:AINT 2 "int_reg_operand" "") ;; operand
- (match_operand:SI 3 "const_int_operand" "")] ;; model
+ [(match_operand:AINT 0 "int_reg_operand") ;; output
+ (match_operand:AINT 1 "memory_operand") ;; memory
+ (match_operand:AINT 2 "int_reg_operand") ;; operand
+ (match_operand:SI 3 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_op (NOT, operands[1], operands[2],
;; Vector move instructions. Little-endian VSX loads and stores require
;; special handling to circumvent "element endianness."
(define_expand "mov<mode>"
- [(set (match_operand:VEC_M 0 "nonimmediate_operand" "")
- (match_operand:VEC_M 1 "any_operand" ""))]
+ [(set (match_operand:VEC_M 0 "nonimmediate_operand")
+ (match_operand:VEC_M 1 "any_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (can_create_pseudo_p ())
;; Generic vector floating point load/store instructions. These will match
;; insns defined in vsx.md or altivec.md depending on the switches.
(define_expand "vector_load_<mode>"
- [(set (match_operand:VEC_M 0 "vfloat_operand" "")
- (match_operand:VEC_M 1 "memory_operand" ""))]
+ [(set (match_operand:VEC_M 0 "vfloat_operand")
+ (match_operand:VEC_M 1 "memory_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_store_<mode>"
- [(set (match_operand:VEC_M 0 "memory_operand" "")
- (match_operand:VEC_M 1 "vfloat_operand" ""))]
+ [(set (match_operand:VEC_M 0 "memory_operand")
+ (match_operand:VEC_M 1 "vfloat_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
;; Splits if a GPR register was chosen for the move
(define_split
- [(set (match_operand:VEC_L 0 "nonimmediate_operand" "")
- (match_operand:VEC_L 1 "input_operand" ""))]
+ [(set (match_operand:VEC_L 0 "nonimmediate_operand")
+ (match_operand:VEC_L 1 "input_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)
&& reload_completed
&& gpr_or_gpr_p (operands[0], operands[1])
;; instructions silently ignore the bottom 3 bits of the address, and VSX does
;; not.
(define_expand "vector_altivec_load_<mode>"
- [(set (match_operand:VEC_M 0 "vfloat_operand" "")
- (match_operand:VEC_M 1 "memory_operand" ""))]
+ [(set (match_operand:VEC_M 0 "vfloat_operand")
+ (match_operand:VEC_M 1 "memory_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
})
(define_expand "vector_altivec_store_<mode>"
- [(set (match_operand:VEC_M 0 "memory_operand" "")
- (match_operand:VEC_M 1 "vfloat_operand" ""))]
+ [(set (match_operand:VEC_M 0 "memory_operand")
+ (match_operand:VEC_M 1 "vfloat_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
\f
;; Generic floating point vector arithmetic support
(define_expand "add<mode>3"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (plus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (plus:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "sub<mode>3"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (minus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (minus:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "mul<mode>3"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
})
(define_expand "div<mode>3"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (div:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (div:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
{
if (RS6000_RECIP_AUTO_RE_P (<MODE>mode)
})
(define_expand "neg<mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
})
(define_expand "abs<mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
})
(define_expand "smin<mode>3"
- [(set (match_operand:VEC_F 0 "register_operand" "")
- (smin:VEC_F (match_operand:VEC_F 1 "register_operand" "")
- (match_operand:VEC_F 2 "register_operand" "")))]
+ [(set (match_operand:VEC_F 0 "register_operand")
+ (smin:VEC_F (match_operand:VEC_F 1 "register_operand")
+ (match_operand:VEC_F 2 "register_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "smax<mode>3"
- [(set (match_operand:VEC_F 0 "register_operand" "")
- (smax:VEC_F (match_operand:VEC_F 1 "register_operand" "")
- (match_operand:VEC_F 2 "register_operand" "")))]
+ [(set (match_operand:VEC_F 0 "register_operand")
+ (smax:VEC_F (match_operand:VEC_F 1 "register_operand")
+ (match_operand:VEC_F 2 "register_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "sqrt<mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode
})
(define_expand "rsqrte<mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")]
UNSPEC_RSQRT))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "re<mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "f")]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")]
UNSPEC_FRES))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "ftrunc<mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_ceil<mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")]
UNSPEC_FRIP))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_floor<mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")]
UNSPEC_FRIM))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_btrunc<mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_copysign<mode>3"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")] UNSPEC_COPYSIGN))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")] UNSPEC_COPYSIGN))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
\f
;; Vector comparisons
(define_expand "vcond<mode><mode>"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
(if_then_else:VEC_F
(match_operator 3 "comparison_operator"
- [(match_operand:VEC_F 4 "vfloat_operand" "")
- (match_operand:VEC_F 5 "vfloat_operand" "")])
- (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
+ [(match_operand:VEC_F 4 "vfloat_operand")
+ (match_operand:VEC_F 5 "vfloat_operand")])
+ (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
})
(define_expand "vcondv4sfv4si"
- [(set (match_operand:V4SF 0 "vfloat_operand" "")
+ [(set (match_operand:V4SF 0 "vfloat_operand")
(if_then_else:V4SF
(match_operator 3 "comparison_operator"
- [(match_operand:V4SI 4 "vint_operand" "")
- (match_operand:V4SI 5 "vint_operand" "")])
- (match_operand:V4SF 1 "vfloat_operand" "")
- (match_operand:V4SF 2 "vfloat_operand" "")))]
+ [(match_operand:V4SI 4 "vint_operand")
+ (match_operand:V4SI 5 "vint_operand")])
+ (match_operand:V4SF 1 "vfloat_operand")
+ (match_operand:V4SF 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& VECTOR_UNIT_ALTIVEC_P (V4SImode)"
{
})
(define_expand "vcondv4siv4sf"
- [(set (match_operand:V4SI 0 "vint_operand" "")
+ [(set (match_operand:V4SI 0 "vint_operand")
(if_then_else:V4SI
(match_operator 3 "comparison_operator"
- [(match_operand:V4SF 4 "vfloat_operand" "")
- (match_operand:V4SF 5 "vfloat_operand" "")])
- (match_operand:V4SI 1 "vint_operand" "")
- (match_operand:V4SI 2 "vint_operand" "")))]
+ [(match_operand:V4SF 4 "vfloat_operand")
+ (match_operand:V4SF 5 "vfloat_operand")])
+ (match_operand:V4SI 1 "vint_operand")
+ (match_operand:V4SI 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& VECTOR_UNIT_ALTIVEC_P (V4SImode)"
{
})
(define_expand "vconduv4sfv4si"
- [(set (match_operand:V4SF 0 "vfloat_operand" "")
+ [(set (match_operand:V4SF 0 "vfloat_operand")
(if_then_else:V4SF
(match_operator 3 "comparison_operator"
- [(match_operand:V4SI 4 "vint_operand" "")
- (match_operand:V4SI 5 "vint_operand" "")])
- (match_operand:V4SF 1 "vfloat_operand" "")
- (match_operand:V4SF 2 "vfloat_operand" "")))]
+ [(match_operand:V4SI 4 "vint_operand")
+ (match_operand:V4SI 5 "vint_operand")])
+ (match_operand:V4SF 1 "vfloat_operand")
+ (match_operand:V4SF 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& VECTOR_UNIT_ALTIVEC_P (V4SImode)"
{
})
(define_expand "vector_eq<mode>"
- [(set (match_operand:VEC_C 0 "vlogical_operand" "")
- (eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
- (match_operand:VEC_C 2 "vlogical_operand" "")))]
+ [(set (match_operand:VEC_C 0 "vlogical_operand")
+ (eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand")
+ (match_operand:VEC_C 2 "vlogical_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_gt<mode>"
- [(set (match_operand:VEC_C 0 "vlogical_operand" "")
- (gt:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
- (match_operand:VEC_C 2 "vlogical_operand" "")))]
+ [(set (match_operand:VEC_C 0 "vlogical_operand")
+ (gt:VEC_C (match_operand:VEC_C 1 "vlogical_operand")
+ (match_operand:VEC_C 2 "vlogical_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_ge<mode>"
- [(set (match_operand:VEC_F 0 "vlogical_operand" "")
- (ge:VEC_F (match_operand:VEC_F 1 "vlogical_operand" "")
- (match_operand:VEC_F 2 "vlogical_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vlogical_operand")
+ (ge:VEC_F (match_operand:VEC_F 1 "vlogical_operand")
+ (match_operand:VEC_F 2 "vlogical_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
; >= for integer vectors: swap operands and apply not-greater-than
(define_expand "vector_nlt<mode>"
- [(set (match_operand:VEC_I 3 "vlogical_operand" "")
- (gt:VEC_I (match_operand:VEC_I 2 "vlogical_operand" "")
- (match_operand:VEC_I 1 "vlogical_operand" "")))
- (set (match_operand:VEC_I 0 "vlogical_operand" "")
+ [(set (match_operand:VEC_I 3 "vlogical_operand")
+ (gt:VEC_I (match_operand:VEC_I 2 "vlogical_operand")
+ (match_operand:VEC_I 1 "vlogical_operand")))
+ (set (match_operand:VEC_I 0 "vlogical_operand")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
})
(define_expand "vector_gtu<mode>"
- [(set (match_operand:VEC_I 0 "vint_operand" "")
- (gtu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
+ [(set (match_operand:VEC_I 0 "vint_operand")
+ (gtu:VEC_I (match_operand:VEC_I 1 "vint_operand")
+ (match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
; >= for integer vectors: swap operands and apply not-greater-than
(define_expand "vector_nltu<mode>"
- [(set (match_operand:VEC_I 3 "vlogical_operand" "")
- (gtu:VEC_I (match_operand:VEC_I 2 "vlogical_operand" "")
- (match_operand:VEC_I 1 "vlogical_operand" "")))
- (set (match_operand:VEC_I 0 "vlogical_operand" "")
+ [(set (match_operand:VEC_I 3 "vlogical_operand")
+ (gtu:VEC_I (match_operand:VEC_I 2 "vlogical_operand")
+ (match_operand:VEC_I 1 "vlogical_operand")))
+ (set (match_operand:VEC_I 0 "vlogical_operand")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
})
(define_expand "vector_geu<mode>"
- [(set (match_operand:VEC_I 0 "vint_operand" "")
- (geu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
+ [(set (match_operand:VEC_I 0 "vint_operand")
+ (geu:VEC_I (match_operand:VEC_I 1 "vint_operand")
+ (match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
; <= for integer vectors: apply not-greater-than
(define_expand "vector_ngt<mode>"
- [(set (match_operand:VEC_I 3 "vlogical_operand" "")
- (gt:VEC_I (match_operand:VEC_I 1 "vlogical_operand" "")
- (match_operand:VEC_I 2 "vlogical_operand" "")))
- (set (match_operand:VEC_I 0 "vlogical_operand" "")
+ [(set (match_operand:VEC_I 3 "vlogical_operand")
+ (gt:VEC_I (match_operand:VEC_I 1 "vlogical_operand")
+ (match_operand:VEC_I 2 "vlogical_operand")))
+ (set (match_operand:VEC_I 0 "vlogical_operand")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
})
(define_expand "vector_ngtu<mode>"
- [(set (match_operand:VEC_I 3 "vlogical_operand" "")
- (gtu:VEC_I (match_operand:VEC_I 1 "vlogical_operand" "")
- (match_operand:VEC_I 2 "vlogical_operand" "")))
- (set (match_operand:VEC_I 0 "vlogical_operand" "")
+ [(set (match_operand:VEC_I 3 "vlogical_operand")
+ (gtu:VEC_I (match_operand:VEC_I 1 "vlogical_operand")
+ (match_operand:VEC_I 2 "vlogical_operand")))
+ (set (match_operand:VEC_I 0 "vlogical_operand")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
})
(define_insn_and_split "*vector_uneq<mode>"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"#"
""
})
(define_insn_and_split "*vector_ltgt<mode>"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"#"
""
})
(define_insn_and_split "*vector_ordered<mode>"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"#"
""
})
(define_insn_and_split "*vector_unordered<mode>"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"#"
""
;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask
;; which is in the reverse order that we want
(define_expand "vector_select_<mode>"
- [(set (match_operand:VEC_L 0 "vlogical_operand" "")
+ [(set (match_operand:VEC_L 0 "vlogical_operand")
(if_then_else:VEC_L
- (ne:CC (match_operand:VEC_L 3 "vlogical_operand" "")
+ (ne:CC (match_operand:VEC_L 3 "vlogical_operand")
(match_dup 4))
- (match_operand:VEC_L 2 "vlogical_operand" "")
- (match_operand:VEC_L 1 "vlogical_operand" "")))]
+ (match_operand:VEC_L 2 "vlogical_operand")
+ (match_operand:VEC_L 1 "vlogical_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"operands[4] = CONST0_RTX (<MODE>mode);")
(define_expand "vector_select_<mode>_uns"
- [(set (match_operand:VEC_L 0 "vlogical_operand" "")
+ [(set (match_operand:VEC_L 0 "vlogical_operand")
(if_then_else:VEC_L
- (ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand" "")
+ (ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand")
(match_dup 4))
- (match_operand:VEC_L 2 "vlogical_operand" "")
- (match_operand:VEC_L 1 "vlogical_operand" "")))]
+ (match_operand:VEC_L 2 "vlogical_operand")
+ (match_operand:VEC_L 1 "vlogical_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"operands[4] = CONST0_RTX (<MODE>mode);")
(define_expand "vector_eq_<mode>_p"
[(parallel
[(set (reg:CC CR6_REGNO)
- (unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand" "")
- (match_operand:VEC_A 2 "vlogical_operand" ""))]
+ (unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand")
+ (match_operand:VEC_A 2 "vlogical_operand"))]
UNSPEC_PREDICATE))
- (set (match_operand:VEC_A 0 "vlogical_operand" "")
+ (set (match_operand:VEC_A 0 "vlogical_operand")
(eq:VEC_A (match_dup 1)
(match_dup 2)))])]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
(define_expand "vector_gt_<mode>_p"
[(parallel
[(set (reg:CC CR6_REGNO)
- (unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand" "")
- (match_operand:VEC_A 2 "vlogical_operand" ""))]
+ (unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand")
+ (match_operand:VEC_A 2 "vlogical_operand"))]
UNSPEC_PREDICATE))
- (set (match_operand:VEC_A 0 "vlogical_operand" "")
+ (set (match_operand:VEC_A 0 "vlogical_operand")
(gt:VEC_A (match_dup 1)
(match_dup 2)))])]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
(define_expand "vector_ge_<mode>_p"
[(parallel
[(set (reg:CC CR6_REGNO)
- (unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" ""))]
+ (unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand"))]
UNSPEC_PREDICATE))
- (set (match_operand:VEC_F 0 "vfloat_operand" "")
+ (set (match_operand:VEC_F 0 "vfloat_operand")
(ge:VEC_F (match_dup 1)
(match_dup 2)))])]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
(define_expand "vector_gtu_<mode>_p"
[(parallel
[(set (reg:CC CR6_REGNO)
- (unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" ""))]
+ (unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand")
+ (match_operand:VEC_I 2 "vint_operand"))]
UNSPEC_PREDICATE))
- (set (match_operand:VEC_I 0 "vlogical_operand" "")
+ (set (match_operand:VEC_I 0 "vlogical_operand")
(gtu:VEC_I (match_dup 1)
(match_dup 2)))])]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
\f
;; Vector count leading zeros
(define_expand "clz<mode>2"
- [(set (match_operand:VEC_I 0 "register_operand" "")
- (clz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]
+ [(set (match_operand:VEC_I 0 "register_operand")
+ (clz:VEC_I (match_operand:VEC_I 1 "register_operand")))]
"TARGET_P8_VECTOR")
;; Vector count trailing zeros
(define_expand "ctz<mode>2"
- [(set (match_operand:VEC_I 0 "register_operand" "")
- (ctz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]
+ [(set (match_operand:VEC_I 0 "register_operand")
+ (ctz:VEC_I (match_operand:VEC_I 1 "register_operand")))]
"TARGET_P9_VECTOR")
;; Vector population count
(define_expand "popcount<mode>2"
- [(set (match_operand:VEC_I 0 "register_operand" "")
- (popcount:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]
+ [(set (match_operand:VEC_I 0 "register_operand")
+ (popcount:VEC_I (match_operand:VEC_I 1 "register_operand")))]
"TARGET_P8_VECTOR")
;; Vector parity
(define_expand "parity<mode>2"
- [(set (match_operand:VEC_IP 0 "register_operand" "")
- (parity:VEC_IP (match_operand:VEC_IP 1 "register_operand" "")))]
+ [(set (match_operand:VEC_IP 0 "register_operand")
+ (parity:VEC_IP (match_operand:VEC_IP 1 "register_operand")))]
"TARGET_P9_VECTOR")
\f
;; Same size conversions
(define_expand "float<VEC_int><mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
})
(define_expand "floatuns<VEC_int><mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
})
(define_expand "fix_trunc<mode><VEC_int>2"
- [(set (match_operand:<VEC_INT> 0 "vint_operand" "")
- (fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
+ [(set (match_operand:<VEC_INT> 0 "vint_operand")
+ (fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
})
(define_expand "fixuns_trunc<mode><VEC_int>2"
- [(set (match_operand:<VEC_INT> 0 "vint_operand" "")
- (unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
+ [(set (match_operand:<VEC_INT> 0 "vint_operand")
+ (unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
\f
;; Vector initialization, set, extract
(define_expand "vec_init<mode><VEC_base_l>"
- [(match_operand:VEC_E 0 "vlogical_operand" "")
- (match_operand:VEC_E 1 "" "")]
+ [(match_operand:VEC_E 0 "vlogical_operand")
+ (match_operand:VEC_E 1 "")]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
rs6000_expand_vector_init (operands[0], operands[1]);
})
(define_expand "vec_set<mode>"
- [(match_operand:VEC_E 0 "vlogical_operand" "")
- (match_operand:<VEC_base> 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")]
+ [(match_operand:VEC_E 0 "vlogical_operand")
+ (match_operand:<VEC_base> 1 "register_operand")
+ (match_operand 2 "const_int_operand")]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
})
(define_expand "vec_extract<mode><VEC_base_l>"
- [(match_operand:<VEC_base> 0 "register_operand" "")
- (match_operand:VEC_E 1 "vlogical_operand" "")
- (match_operand 2 "const_int_operand" "")]
+ [(match_operand:<VEC_base> 0 "register_operand")
+ (match_operand:VEC_E 1 "vlogical_operand")
+ (match_operand 2 "const_int_operand")]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
rs6000_expand_vector_extract (operands[0], operands[1], operands[2]);
\f
;; Convert double word types to single word types
(define_expand "vec_pack_trunc_v2df"
- [(match_operand:V4SF 0 "vfloat_operand" "")
- (match_operand:V2DF 1 "vfloat_operand" "")
- (match_operand:V2DF 2 "vfloat_operand" "")]
+ [(match_operand:V4SF 0 "vfloat_operand")
+ (match_operand:V2DF 1 "vfloat_operand")
+ (match_operand:V2DF 2 "vfloat_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
{
rtx r1 = gen_reg_rtx (V4SFmode);
})
(define_expand "vec_pack_sfix_trunc_v2df"
- [(match_operand:V4SI 0 "vint_operand" "")
- (match_operand:V2DF 1 "vfloat_operand" "")
- (match_operand:V2DF 2 "vfloat_operand" "")]
+ [(match_operand:V4SI 0 "vint_operand")
+ (match_operand:V2DF 1 "vfloat_operand")
+ (match_operand:V2DF 2 "vfloat_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
{
rtx r1 = gen_reg_rtx (V4SImode);
})
(define_expand "vec_pack_ufix_trunc_v2df"
- [(match_operand:V4SI 0 "vint_operand" "")
- (match_operand:V2DF 1 "vfloat_operand" "")
- (match_operand:V2DF 2 "vfloat_operand" "")]
+ [(match_operand:V4SI 0 "vint_operand")
+ (match_operand:V2DF 1 "vfloat_operand")
+ (match_operand:V2DF 2 "vfloat_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
{
rtx r1 = gen_reg_rtx (V4SImode);
;; Convert single word types to double word
(define_expand "vec_unpacks_hi_v4sf"
- [(match_operand:V2DF 0 "vfloat_operand" "")
- (match_operand:V4SF 1 "vfloat_operand" "")]
+ [(match_operand:V2DF 0 "vfloat_operand")
+ (match_operand:V4SF 1 "vfloat_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
{
rtx reg = gen_reg_rtx (V4SFmode);
})
(define_expand "vec_unpacks_lo_v4sf"
- [(match_operand:V2DF 0 "vfloat_operand" "")
- (match_operand:V4SF 1 "vfloat_operand" "")]
+ [(match_operand:V2DF 0 "vfloat_operand")
+ (match_operand:V4SF 1 "vfloat_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
{
rtx reg = gen_reg_rtx (V4SFmode);
})
(define_expand "vec_unpacks_float_hi_v4si"
- [(match_operand:V2DF 0 "vfloat_operand" "")
- (match_operand:V4SI 1 "vint_operand" "")]
+ [(match_operand:V2DF 0 "vfloat_operand")
+ (match_operand:V4SI 1 "vint_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
{
rtx reg = gen_reg_rtx (V4SImode);
})
(define_expand "vec_unpacks_float_lo_v4si"
- [(match_operand:V2DF 0 "vfloat_operand" "")
- (match_operand:V4SI 1 "vint_operand" "")]
+ [(match_operand:V2DF 0 "vfloat_operand")
+ (match_operand:V4SI 1 "vint_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
{
rtx reg = gen_reg_rtx (V4SImode);
})
(define_expand "vec_unpacku_float_hi_v4si"
- [(match_operand:V2DF 0 "vfloat_operand" "")
- (match_operand:V4SI 1 "vint_operand" "")]
+ [(match_operand:V2DF 0 "vfloat_operand")
+ (match_operand:V4SI 1 "vint_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
{
rtx reg = gen_reg_rtx (V4SImode);
})
(define_expand "vec_unpacku_float_lo_v4si"
- [(match_operand:V2DF 0 "vfloat_operand" "")
- (match_operand:V4SI 1 "vint_operand" "")]
+ [(match_operand:V2DF 0 "vfloat_operand")
+ (match_operand:V4SI 1 "vint_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
{
rtx reg = gen_reg_rtx (V4SImode);
\f
;; Align vector loads with a permute.
(define_expand "vec_realign_load_<mode>"
- [(match_operand:VEC_K 0 "vlogical_operand" "")
- (match_operand:VEC_K 1 "vlogical_operand" "")
- (match_operand:VEC_K 2 "vlogical_operand" "")
- (match_operand:V16QI 3 "vlogical_operand" "")]
+ [(match_operand:VEC_K 0 "vlogical_operand")
+ (match_operand:VEC_K 1 "vlogical_operand")
+ (match_operand:VEC_K 2 "vlogical_operand")
+ (match_operand:V16QI 3 "vlogical_operand")]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (BYTES_BIG_ENDIAN)
;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned
;; since the load already handles it.
(define_expand "movmisalign<mode>"
- [(set (match_operand:VEC_N 0 "nonimmediate_operand" "")
- (match_operand:VEC_N 1 "any_operand" ""))]
+ [(set (match_operand:VEC_N 0 "nonimmediate_operand")
+ (match_operand:VEC_N 1 "any_operand"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_ALLOW_MOVMISALIGN"
"")
;; Note that the vec_shr operation is actually defined as
;; 'shift toward element 0' so is a shr for LE and shl for BE.
(define_expand "vec_shr_<mode>"
- [(match_operand:VEC_L 0 "vlogical_operand" "")
- (match_operand:VEC_L 1 "vlogical_operand" "")
- (match_operand:QI 2 "reg_or_short_operand" "")]
+ [(match_operand:VEC_L 0 "vlogical_operand")
+ (match_operand:VEC_L 1 "vlogical_operand")
+ (match_operand:QI 2 "reg_or_short_operand")]
"TARGET_ALTIVEC"
{
rtx bitshift = operands[2];
;; Expanders for rotate each element in a vector
(define_expand "vrotl<mode>3"
- [(set (match_operand:VEC_I 0 "vint_operand" "")
- (rotate:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
+ [(set (match_operand:VEC_I 0 "vint_operand")
+ (rotate:VEC_I (match_operand:VEC_I 1 "vint_operand")
+ (match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
;; Expanders for arithmetic shift left on each vector element
(define_expand "vashl<mode>3"
- [(set (match_operand:VEC_I 0 "vint_operand" "")
- (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
+ [(set (match_operand:VEC_I 0 "vint_operand")
+ (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand")
+ (match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
;; Expanders for logical shift right on each vector element
(define_expand "vlshr<mode>3"
- [(set (match_operand:VEC_I 0 "vint_operand" "")
- (lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
+ [(set (match_operand:VEC_I 0 "vint_operand")
+ (lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand")
+ (match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
;; Expanders for arithmetic shift right on each vector element
(define_expand "vashr<mode>3"
- [(set (match_operand:VEC_I 0 "vint_operand" "")
- (ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
+ [(set (match_operand:VEC_I 0 "vint_operand")
+ (ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand")
+ (match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
\f
(define_expand "reduc_<VEC_reduc:VEC_reduc_name>_scal_<VEC_F:mode>"
- [(match_operand:<VEC_base> 0 "register_operand" "")
- (VEC_reduc:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
+ [(match_operand:<VEC_base> 0 "register_operand")
+ (VEC_reduc:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
(unspec:VEC_F [(const_int 0)] UNSPEC_REDUC))]
"VECTOR_UNIT_VSX_P (<VEC_F:MODE>mode)"
{
(set_attr "length" "12")])
(define_split
- [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "")
- (match_operand:VSX_D 1 "vsx_register_operand" ""))]
+ [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand")
+ (match_operand:VSX_D 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed"
[(set (match_dup 2)
(vec_select:<MODE>
;; The post-reload split requires that we re-permute the source
;; register in case it is still live.
(define_split
- [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "")
- (match_operand:VSX_D 1 "vsx_register_operand" ""))]
+ [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand")
+ (match_operand:VSX_D 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed"
[(set (match_dup 1)
(vec_select:<MODE>
(set_attr "length" "12")])
(define_split
- [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "")
- (match_operand:VSX_W 1 "vsx_register_operand" ""))]
+ [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand")
+ (match_operand:VSX_W 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed"
[(set (match_dup 2)
(vec_select:<MODE>
;; The post-reload split requires that we re-permute the source
;; register in case it is still live.
(define_split
- [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "")
- (match_operand:VSX_W 1 "vsx_register_operand" ""))]
+ [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand")
+ (match_operand:VSX_W 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed"
[(set (match_dup 1)
(vec_select:<MODE>
(set_attr "length" "12")])
(define_split
- [(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "")
- (match_operand:V8HI 1 "vsx_register_operand" ""))]
+ [(set (match_operand:V8HI 0 "indexed_or_indirect_operand")
+ (match_operand:V8HI 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed"
[(set (match_dup 2)
(vec_select:V8HI
;; The post-reload split requires that we re-permute the source
;; register in case it is still live.
(define_split
- [(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "")
- (match_operand:V8HI 1 "vsx_register_operand" ""))]
+ [(set (match_operand:V8HI 0 "indexed_or_indirect_operand")
+ (match_operand:V8HI 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed"
[(set (match_dup 1)
(vec_select:V8HI
(set_attr "length" "12")])
(define_split
- [(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "")
- (match_operand:V16QI 1 "vsx_register_operand" ""))]
+ [(set (match_operand:V16QI 0 "indexed_or_indirect_operand")
+ (match_operand:V16QI 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed"
[(set (match_dup 2)
(vec_select:V16QI
;; The post-reload split requires that we re-permute the source
;; register in case it is still live.
(define_split
- [(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "")
- (match_operand:V16QI 1 "vsx_register_operand" ""))]
+ [(set (match_operand:V16QI 0 "indexed_or_indirect_operand")
+ (match_operand:V16QI 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed"
[(set (match_dup 1)
(vec_select:V16QI
(set_attr "length" "12,8")])
(define_split
- [(set (match_operand:VSX_LE_128 0 "memory_operand" "")
- (match_operand:VSX_LE_128 1 "vsx_register_operand" ""))]
+ [(set (match_operand:VSX_LE_128 0 "memory_operand")
+ (match_operand:VSX_LE_128 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed && !TARGET_P9_VECTOR"
[(const_int 0)]
{
;; VSX registers on a little endian system. The vector types and IEEE 128-bit
;; floating point are handled by the more generic swap elimination pass.
(define_peephole2
- [(set (match_operand:TI 0 "vsx_register_operand" "")
- (rotate:TI (match_operand:TI 1 "vsx_register_operand" "")
+ [(set (match_operand:TI 0 "vsx_register_operand")
+ (rotate:TI (match_operand:TI 1 "vsx_register_operand")
(const_int 64)))
- (set (match_operand:TI 2 "vsx_register_operand" "")
+ (set (match_operand:TI 2 "vsx_register_operand")
(rotate:TI (match_dup 0)
(const_int 64)))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR
;; The post-reload split requires that we re-permute the source
;; register in case it is still live.
(define_split
- [(set (match_operand:VSX_LE_128 0 "memory_operand" "")
- (match_operand:VSX_LE_128 1 "vsx_register_operand" ""))]
+ [(set (match_operand:VSX_LE_128 0 "memory_operand")
+ (match_operand:VSX_LE_128 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed && !TARGET_P9_VECTOR"
[(const_int 0)]
{
;; Explicit load/store expanders for the builtin functions
(define_expand "vsx_load_<mode>"
- [(set (match_operand:VSX_M 0 "vsx_register_operand" "")
- (match_operand:VSX_M 1 "memory_operand" ""))]
+ [(set (match_operand:VSX_M 0 "vsx_register_operand")
+ (match_operand:VSX_M 1 "memory_operand"))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
/* Expand to swaps if needed, prior to swap optimization. */
})
(define_expand "vsx_store_<mode>"
- [(set (match_operand:VSX_M 0 "memory_operand" "")
- (match_operand:VSX_M 1 "vsx_register_operand" ""))]
+ [(set (match_operand:VSX_M 0 "memory_operand")
+ (match_operand:VSX_M 1 "vsx_register_operand"))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
/* Expand to swaps if needed, prior to swap optimization. */
;; *tdiv* instruction returning the FG flag
(define_expand "vsx_tdiv<mode>3_fg"
[(set (match_dup 3)
- (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")
- (match_operand:VSX_B 2 "vsx_register_operand" "")]
+ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand")
+ (match_operand:VSX_B 2 "vsx_register_operand")]
UNSPEC_VSX_TDIV))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand")
(gt:SI (match_dup 3)
(const_int 0)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
;; *tdiv* instruction returning the FE flag
(define_expand "vsx_tdiv<mode>3_fe"
[(set (match_dup 3)
- (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")
- (match_operand:VSX_B 2 "vsx_register_operand" "")]
+ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand")
+ (match_operand:VSX_B 2 "vsx_register_operand")]
UNSPEC_VSX_TDIV))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand")
(eq:SI (match_dup 3)
(const_int 0)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
;; *tsqrt* returning the fg flag
(define_expand "vsx_tsqrt<mode>2_fg"
[(set (match_dup 2)
- (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")]
+ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand")]
UNSPEC_VSX_TSQRT))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand")
(gt:SI (match_dup 2)
(const_int 0)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
;; *tsqrt* returning the fe flag
(define_expand "vsx_tsqrt<mode>2_fe"
[(set (match_dup 2)
- (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")]
+ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand")]
UNSPEC_VSX_TSQRT))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand")
(eq:SI (match_dup 2)
(const_int 0)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
;; Convert and scale (used by vec_ctf, vec_cts, vec_ctu for double/long long)
(define_expand "vsx_xvcvsxddp_scale"
- [(match_operand:V2DF 0 "vsx_register_operand" "")
- (match_operand:V2DI 1 "vsx_register_operand" "")
- (match_operand:QI 2 "immediate_operand" "")]
+ [(match_operand:V2DF 0 "vsx_register_operand")
+ (match_operand:V2DI 1 "vsx_register_operand")
+ (match_operand:QI 2 "immediate_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode)"
{
rtx op0 = operands[0];
[(set_attr "type" "vecdouble")])
(define_expand "vsx_xvcvuxddp_scale"
- [(match_operand:V2DF 0 "vsx_register_operand" "")
- (match_operand:V2DI 1 "vsx_register_operand" "")
- (match_operand:QI 2 "immediate_operand" "")]
+ [(match_operand:V2DF 0 "vsx_register_operand")
+ (match_operand:V2DI 1 "vsx_register_operand")
+ (match_operand:QI 2 "immediate_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode)"
{
rtx op0 = operands[0];
[(set_attr "type" "vecdouble")])
(define_expand "vsx_xvcvdpsxds_scale"
- [(match_operand:V2DI 0 "vsx_register_operand" "")
- (match_operand:V2DF 1 "vsx_register_operand" "")
- (match_operand:QI 2 "immediate_operand" "")]
+ [(match_operand:V2DI 0 "vsx_register_operand")
+ (match_operand:V2DF 1 "vsx_register_operand")
+ (match_operand:QI 2 "immediate_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode)"
{
rtx op0 = operands[0];
;; convert vector of 64-bit floating point numbers to vector of
;; 64-bit unsigned integer
(define_expand "vsx_xvcvdpuxds_scale"
- [(match_operand:V2DI 0 "vsx_register_operand" "")
- (match_operand:V2DF 1 "vsx_register_operand" "")
- (match_operand:QI 2 "immediate_operand" "")]
+ [(match_operand:V2DI 0 "vsx_register_operand")
+ (match_operand:V2DF 1 "vsx_register_operand")
+ (match_operand:QI 2 "immediate_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode)"
{
rtx op0 = operands[0];
;; Convert a TImode value into V1TImode
(define_expand "vsx_set_v1ti"
- [(match_operand:V1TI 0 "nonimmediate_operand" "")
- (match_operand:V1TI 1 "nonimmediate_operand" "")
- (match_operand:TI 2 "input_operand" "")
- (match_operand:QI 3 "u5bit_cint_operand" "")]
+ [(match_operand:V1TI 0 "nonimmediate_operand")
+ (match_operand:V1TI 1 "nonimmediate_operand")
+ (match_operand:TI 2 "input_operand")
+ (match_operand:QI 3 "u5bit_cint_operand")]
"VECTOR_MEM_VSX_P (V1TImode)"
{
if (operands[3] != const0_rtx)
;; Expanders for builtins
(define_expand "vsx_mergel_<mode>"
- [(use (match_operand:VSX_D 0 "vsx_register_operand" ""))
- (use (match_operand:VSX_D 1 "vsx_register_operand" ""))
- (use (match_operand:VSX_D 2 "vsx_register_operand" ""))]
+ [(use (match_operand:VSX_D 0 "vsx_register_operand"))
+ (use (match_operand:VSX_D 1 "vsx_register_operand"))
+ (use (match_operand:VSX_D 2 "vsx_register_operand"))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
rtvec v;
})
(define_expand "vsx_mergeh_<mode>"
- [(use (match_operand:VSX_D 0 "vsx_register_operand" ""))
- (use (match_operand:VSX_D 1 "vsx_register_operand" ""))
- (use (match_operand:VSX_D 2 "vsx_register_operand" ""))]
+ [(use (match_operand:VSX_D 0 "vsx_register_operand"))
+ (use (match_operand:VSX_D 1 "vsx_register_operand"))
+ (use (match_operand:VSX_D 2 "vsx_register_operand"))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
rtvec v;
\f
;; Power8 Vector fusion. The fused ops must be physically adjacent.
(define_peephole
- [(set (match_operand:P 0 "base_reg_operand" "")
- (match_operand:P 1 "short_cint_operand" ""))
- (set (match_operand:VSX_M 2 "vsx_register_operand" "")
+ [(set (match_operand:P 0 "base_reg_operand")
+ (match_operand:P 1 "short_cint_operand"))
+ (set (match_operand:VSX_M 2 "vsx_register_operand")
(mem:VSX_M (plus:P (match_dup 0)
- (match_operand:P 3 "int_reg_operand" ""))))]
+ (match_operand:P 3 "int_reg_operand"))))]
"TARGET_VSX && TARGET_P8_FUSION && !TARGET_P9_VECTOR"
"li %0,%1\;lx<VSX_M:VSm>x %x2,%0,%3\t\t\t# vector load fusion"
[(set_attr "length" "8")
(set_attr "type" "vecload")])
(define_peephole
- [(set (match_operand:P 0 "base_reg_operand" "")
- (match_operand:P 1 "short_cint_operand" ""))
- (set (match_operand:VSX_M 2 "vsx_register_operand" "")
- (mem:VSX_M (plus:P (match_operand:P 3 "int_reg_operand" "")
+ [(set (match_operand:P 0 "base_reg_operand")
+ (match_operand:P 1 "short_cint_operand"))
+ (set (match_operand:VSX_M 2 "vsx_register_operand")
+ (mem:VSX_M (plus:P (match_operand:P 3 "int_reg_operand")
(match_dup 0))))]
"TARGET_VSX && TARGET_P8_FUSION && !TARGET_P9_VECTOR"
"li %0,%1\;lx<VSX_M:VSm>x %x2,%0,%3\t\t\t# vector load fusion"
git://gcc.gnu.org / gcc.git / commitdiff