case ENB_P7_64:
return TARGET_POPCNTD && TARGET_POWERPC64;
case ENB_P8:
- return TARGET_DIRECT_MOVE;
+ return TARGET_POWER8;
case ENB_P8V:
return TARGET_P8_VECTOR;
case ENB_P9:
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
if ((flags & OPTION_MASK_POPCNTD) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
- if ((flags & OPTION_MASK_P8_VECTOR) != 0)
+ if ((flags & OPTION_MASK_POWER8) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
if ((flags & OPTION_MASK_MODULO) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
fusion here, instead set it in rs6000.cc if we are tuning for a power8
system. */
#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
+ | OPTION_MASK_POWER8 \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_MODULO \
| OPTION_MASK_MULHW \
| OPTION_MASK_NO_UPDATE \
+ | OPTION_MASK_POWER8 \
| OPTION_MASK_P8_FUSION \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_MINMAX \
"-mmultiple");
}
- /* If little-endian, default to -mstrict-align on older processors.
- Testing for direct_move matches power8 and later. */
+ /* If little-endian, default to -mstrict-align on older processors. */
if (!BYTES_BIG_ENDIAN
&& !(processor_target_table[tune_index].target_enable
- & OPTION_MASK_P8_VECTOR))
+ & OPTION_MASK_POWER8))
rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
/* Add some warnings for VSX. */
else
rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
}
- else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
+ else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
else if (TARGET_VSX)
rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
memory support. */
#define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \
|| TARGET_QUAD_MEMORY_ATOMIC \
- || TARGET_DIRECT_MOVE)
+ || TARGET_POWER8)
#define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10"
(const_string "any"))
;; Is this alternative enabled for the current CPU/ISA/etc.?
(match_test "TARGET_VSX"))
(const_int 1)
+ (and (eq_attr "isa" "p8")
+ (match_test "TARGET_POWER8"))
+ (const_int 1)
+
(and (eq_attr "isa" "p8v")
(match_test "TARGET_P8_VECTOR"))
(const_int 1)
AIX does not support the dcbtstt and dcbtt extended mnemonics.
The AIX assembler does not support the three operand form of dcbt
and dcbtst on Power 7 (-mpwr7). */
- int inst_select = INTVAL (operands[2]) || !TARGET_DIRECT_MOVE;
+ int inst_select = INTVAL (operands[2]) || !TARGET_POWER8;
if (REG_P (operands[0]))
{
mvsx-timode
Target RejectNegative Undocumented Ignore
+;; This option exists only to create its MASK. It is not intended for users.
+mpower8-internal
+Target Undocumented Mask(POWER8) Var(rs6000_isa_flags) Warn(Do not use %<-mpower8-internal%>; use %<-mcpu=power8%> instead)
+
mpower8-fusion
Target Mask(P8_FUSION) Var(rs6000_isa_flags)
Fuse certain integer operations together for better performance on power8.
--- /dev/null
+/* PR target/101865 */
+/* { dg-do preprocess } */
+/* { dg-options "-mdejagnu-cpu=power7 -mno-vsx" } */
+
+/* Verify we correctly set the correct set of predefined macros
+ for the given set of options. */
+
+#ifndef _ARCH_PWR7
+#error "_ARCH_PWR7 should be defined for this test"
+#endif
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined for this test"
+#endif
+
+#ifdef _ARCH_PWR8
+#error "_ARCH_PWR8 should not be defined for this test"
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined for this test"
+#endif
--- /dev/null
+/* PR target/101865 */
+/* { dg-do preprocess } */
+/* { dg-options "-mdejagnu-cpu=power8 -mno-altivec -mno-vsx" } */
+
+/* Verify _ARCH_PWR8 is defined for -mcpu=power8 and after disabling
+ both altivec and vsx. */
+
+#ifndef _ARCH_PWR7
+#error "_ARCH_PWR7 should be defined for this test"
+#endif
+
+#ifndef _ARCH_PWR8
+#error "_ARCH_PWR8 should be defined for this test"
+#endif
+
+#ifdef _ARCH_PWR9
+#error "_ARCH_PWR9 should not be defined for this test"
+#endif
+
+#ifdef __ALTIVEC__
+#error "__ALTIVEC__ should not be defined for this test"
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined for this test"
+#endif
--- /dev/null
+/* PR target/101865 */
+/* { dg-do preprocess } */
+/* { dg-options "-mdejagnu-cpu=power8 -mno-altivec -w" } */
+
+/* Verify _ARCH_PWR8 is defined for -mcpu=power8 and after disabling altivec.
+ The -w option is used to silence the -mno-altivec disables -mvsx warning. */
+
+#ifndef _ARCH_PWR7
+#error "_ARCH_PWR7 should be defined for this test"
+#endif
+
+#ifndef _ARCH_PWR8
+#error "_ARCH_PWR8 should be defined for this test"
+#endif
+
+#ifdef _ARCH_PWR9
+#error "_ARCH_PWR9 should not be defined for this test"
+#endif
+
+#ifdef __ALTIVEC__
+#error "__ALTIVEC__ should not be defined for this test"
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined for this test"
+#endif
--- /dev/null
+/* PR target/101865 */
+/* { dg-do preprocess } */
+/* { dg-options "-mdejagnu-cpu=power8 -mno-vsx" } */
+
+/* Verify _ARCH_PWR8 is defined for -mcpu=power8 and after disabling vsx.
+ This also confirms __ALTIVEC__ remains set when VSX is disabled. */
+
+#ifndef _ARCH_PWR7
+#error "_ARCH_PWR7 should be defined for this test"
+#endif
+
+#ifndef _ARCH_PWR8
+#error "_ARCH_PWR8 should be defined for this test"
+#endif
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined for this test"
+#endif
+
+#ifdef _ARCH_PWR9
+#error "_ARCH_PWR9 should not be defined for this test"
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined for this test"
+#endif
--- /dev/null
+/* PR target/101865 */
+/* { dg-do run } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */
+
+/* Verify we correctly set our predefined macros in the face of #pragma usage. */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+volatile int power8_set;
+volatile int vsx_set;
+
+void
+test_default (void)
+{
+#ifdef _ARCH_PWR8
+ power8_set=1;
+#else
+ power8_set=0;
+#endif
+#ifdef __VSX__
+ vsx_set=1;
+#else
+ vsx_set=0;
+#endif
+}
+
+#pragma GCC target "no-vsx"
+void
+test_no_vsx (void)
+{
+#ifdef _ARCH_PWR8
+ power8_set=1;
+#else
+ power8_set=0;
+#endif
+#ifdef __VSX__
+ vsx_set=1;
+#else
+ vsx_set=0;
+#endif
+}
+
+#pragma GCC reset_options
+void
+test_reset_options (void)
+{
+#ifdef _ARCH_PWR8
+ power8_set=1;
+#else
+ power8_set=0;
+#endif
+#ifdef __VSX__
+ vsx_set=1;
+#else
+ vsx_set=0;
+#endif
+}
+
+int
+main (void)
+{
+ test_default ();
+ if (!power8_set)
+ {
+ printf ("_ARCH_PWR8 is not set.\n");
+ abort ();
+ }
+ if (!vsx_set)
+ {
+ printf ("__VSX__ is not set.\n");
+ abort ();
+ }
+
+ test_no_vsx ();
+ if (!power8_set)
+ {
+ printf ("_ARCH_PWR8 is not set.\n");
+ abort ();
+ }
+ if (vsx_set)
+ {
+ printf ("__VSX__ is unexpectedly set.\n");
+ abort ();
+ }
+
+ test_reset_options ();
+ if (!power8_set)
+ {
+ printf ("_ARCH_PWR8 is not set.\n");
+ abort ();
+ }
+ if (!vsx_set)
+ {
+ printf ("__VSX__ is not set.\n");
+ abort ();
+ }
+
+ return 0;
+}
--- /dev/null
+/* PR target/101865 */
+/* { dg-do preprocess } */
+/* { dg-options "-mdejagnu-cpu=power9 -mno-vsx" } */
+
+/* Verify _ARCH_PWR8 is defined for -mcpu=power9 and after disabling vsx.
+ This also confirms __ALTIVEC__ remains set when VSX is disabled. */
+
+#ifndef _ARCH_PWR7
+#error "_ARCH_PWR7 should be defined for this test"
+#endif
+
+#ifndef _ARCH_PWR8
+#error "_ARCH_PWR8 should be defined for this test"
+#endif
+
+#ifndef _ARCH_PWR9
+#error "_ARCH_PWR9 should be defined for this test"
+#endif
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined for this test"
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined for this test"
+#endif