Fix v850 ICE.

	* combine.c (try_combine): When split an instruction pair, where the
	first has a sign_extend src, verify that the src and dest modes match.

From-SVN: r57371

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d28402f9a32eac4cd4588418a70cdac557a2a4f8..103bc9468ba874f2e65d703c4af23953ea744061 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2002-09-20  Jim Wilson  <wilson@redhat.com>
+
+       * combine.c (try_combine): When split an instruction pair, where the
+       first has a sign_extend src, verify that the src and dest modes match.
+
 2002-09-20  Richard Henderson  <rth@redhat.com>
 
        * config/mips/mips.c (dfhigh, dflow, sfhigh, sflow): Remove.

diff --git a/gcc/combine.c b/gcc/combine.c
index 23136194bf085b5e8363c885c2c891e36d2e8a7b..1d6a5b270b70eba958c9c9124a6c883a7c6e807c 100644 (file)
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -2316,6 +2316,10 @@ try_combine (i3, i2, i1, new_direct_jump_p)
      copy.  This saves at least one insn, more if register allocation can
      eliminate the copy.
 
+     We cannot do this if the destination of the first assignment is a
+     condition code register or cc0.  We eliminate this case by making sure
+     the SET_DEST and SET_SRC have the same mode.
+
      We cannot do this if the destination of the second assignment is
      a register that we have already assumed is zero-extended.  Similarly
      for a SUBREG of such a register.  */
@@ -2325,6 +2329,8 @@ try_combine (i3, i2, i1, new_direct_jump_p)
           && XVECLEN (newpat, 0) == 2
           && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
           && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
+          && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
+              == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
           && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
           && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
                           XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))