Patterns zero_extendhisi2, zero_extendqisi2 and extendhisi2_internal can
load value from memory, but they don't treat volatile memory correctly.
Add %v1 before load instructions to emit 'memw' instruction when
-mserialize-volatile is in effect.
2020-04-14 Max Filippov <jcmvbkbc@gmail.com>
gcc/
* config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
(extendhisi2_internal): Add %v1 before the load instructions.
gcc/testsuite/
* gcc.target/xtensa/pr94584.c: New test.
+2020-04-14 Max Filippov <jcmvbkbc@gmail.com>
+
+ PR target/94584
+ * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
+ (extendhisi2_internal): Add %v1 before the load instructions.
+
2020-04-14 Aaron Sawdey <acsawdey@linux.ibm.com>
PR target/94542
""
"@
extui\t%0, %1, 0, 16
- l16ui\t%0, %1"
+ %v1l16ui\t%0, %1"
[(set_attr "type" "arith,load")
(set_attr "mode" "SI")
(set_attr "length" "3,3")])
""
"@
extui\t%0, %1, 0, 8
- l8ui\t%0, %1"
+ %v1l8ui\t%0, %1"
[(set_attr "type" "arith,load")
(set_attr "mode" "SI")
(set_attr "length" "3,3")])
""
"@
sext\t%0, %1, 15
- l16si\t%0, %1"
+ %v1l16si\t%0, %1"
[(set_attr "type" "arith,load")
(set_attr "mode" "SI")
(set_attr "length" "3,3")])
+2020-04-13 Max Filippov <jcmvbkbc@gmail.com>
+
+ PR target/94584
+ * gcc.target/xtensa/pr94584.c: New test.
+
2020-04-14 Iain Sandoe <iain@sandoe.co.uk>
PR c++/94359
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -mserialize-volatile" } */
+
+unsigned long load32 (volatile unsigned long *s)
+{
+ return *s;
+}
+
+short load16s (volatile short *s)
+{
+ return *s;
+}
+
+unsigned short load16u (volatile unsigned short *s)
+{
+ return *s;
+}
+
+unsigned char load8 (volatile unsigned char *s)
+{
+ return *s;
+}
+
+/* { dg-final { scan-assembler-times "memw" 4 } } */