[ARC] Differentiate between ARCv1 and ARCv2 'h'-reg class for ADD insns.

gcc/
2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_output_addsi): Check for h-register class
	when emitting short ADD instructions.

From-SVN: r247195

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7fb9ee86c2816a0021a97ac32da8422120a7378e..b38b429f38bfbeb3f3499c4f41ed8c61a679413e 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * config/arc/arc.c (arc_output_addsi): Check for h-register class
+       when emitting short ADD instructions.
+
 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 
        * config/arc/arc.md (cmpsi_cc_insn_mixed): Use 'h' register

diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 92fecad93d9bc026befa11a4ff84326abd91be2d..d6f500c88b00dbe0957dd683a67018901cde5736 100644 (file)
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -7324,6 +7324,10 @@ arc_output_addsi (rtx *operands, bool cond_p, bool output_p)
   int short_p = (!cond_p && short_0 && satisfies_constraint_Rcq (operands[1]));
   int ret = 0;
 
+#define REG_H_P(OP) (REG_P (OP) && ((TARGET_V2 && REGNO (OP) <= 31     \
+                                    && REGNO (OP) != 30)               \
+                                   || !TARGET_V2))
+
 #define ADDSI_OUTPUT1(FORMAT) do {\
   if (output_p) \
     output_asm_insn (FORMAT, operands);\
@@ -7346,32 +7350,40 @@ arc_output_addsi (rtx *operands, bool cond_p, bool output_p)
         but add1 r0,sp,35 doesn't.  */
       && (!output_p || (get_attr_length (current_output_insn) & 2)))
     {
+      /* Generate add_s a,b,c; add_s b,b,u7; add_s c,b,u3; add_s b,b,h
+        patterns.  */
       if (short_p
-         && (REG_P (operands[2])
-             ? (match || satisfies_constraint_Rcq (operands[2]))
-             : (unsigned) intval <= (match ? 127 : 7)))
-       ADDSI_OUTPUT1 ("add%? %0,%1,%2");
-      if (short_0 && REG_P (operands[1]) && match2)
-       ADDSI_OUTPUT1 ("add%? %0,%2,%1");
+         && ((REG_H_P (operands[2])
+              && (match || satisfies_constraint_Rcq (operands[2])))
+             || (CONST_INT_P (operands[2])
+                 && ((unsigned) intval <= (match ? 127 : 7)))))
+       ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;1");
+
+      /* Generate add_s b,b,h patterns.  */
+      if (short_0 && match2 && REG_H_P (operands[1]))
+       ADDSI_OUTPUT1 ("add%? %0,%2,%1 ;2");
+
+      /* Generate add_s b,sp,u7; add_s sp,sp,u7 patterns.  */
       if ((short_0 || REGNO (operands[0]) == STACK_POINTER_REGNUM)
          && REGNO (operands[1]) == STACK_POINTER_REGNUM && !(intval & ~124))
-       ADDSI_OUTPUT1 ("add%? %0,%1,%2");
+       ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;3");
 
       if ((short_p && (unsigned) neg_intval <= (match ? 31 : 7))
          || (REGNO (operands[0]) == STACK_POINTER_REGNUM
              && match && !(neg_intval & ~124)))
-       ADDSI_OUTPUT1 ("sub%? %0,%1,%n2");
+       ADDSI_OUTPUT1 ("sub%? %0,%1,%n2 ;4");
 
-      if (REG_P(operands[0]) && REG_P(operands[1])
-         && (REGNO(operands[0]) <= 31) && (REGNO(operands[0]) == REGNO(operands[1]))
-         && CONST_INT_P (operands[2]) && ( (intval>= -1) && (intval <= 6)))
-       ADDSI_OUTPUT1 ("add%? %0,%1,%2");
+      /* Generate add_s h,h,s3 patterns.  */
+      if (REG_H_P (operands[0]) && match && TARGET_V2
+         && CONST_INT_P (operands[2]) && ((intval>= -1) && (intval <= 6)))
+       ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;5");
 
-      if (TARGET_CODE_DENSITY && REG_P(operands[0]) && REG_P(operands[1])
-         && ((REGNO(operands[0]) == 0) || (REGNO(operands[0]) == 1))
+      /* Generate add_s r0,b,u6; add_s r1,b,u6 patterns.  */
+      if (TARGET_CODE_DENSITY && REG_P (operands[0]) && REG_P (operands[1])
+         && ((REGNO (operands[0]) == 0) || (REGNO (operands[0]) == 1))
          && satisfies_constraint_Rcq (operands[1])
          && satisfies_constraint_L (operands[2]))
-       ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;3");
+       ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;6");
     }
 
   /* Now try to emit a 32 bit insn without long immediate.  */