2009-01-30 Wolfgang Gellerich <gellerich@de,ibm.com>

	* config/s390/s390.md (*insv<mode>_reg_extimm): Removed.
	(*insv_h_di_reg_extimm): New insn.
	(*insv_l<mode>_reg_extimm): New insn.

From-SVN: r143786

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6dc807bb4ca92fa966d2117be07312c5806bd534..c700951184b857b85d570592f1f8cd57111dd1a1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,10 +1,16 @@
-Hariharan Sandanagobalane <hariharan@picochip.com>
+2009-01-30  Wolfgang Gellerich  <gellerich@de,ibm.com>
+
+       * config/s390/s390.md (*insv<mode>_reg_extimm): Removed.
+       (*insv_h_di_reg_extimm): New insn.
+       (*insv_l<mode>_reg_extimm): New insn.
+
+2009-01-30  Hariharan Sandanagobalane  <hariharan@picochip.com>
 
        * config/picochip/picochip.c (flag_conserve_stack): set
        PARAM_LARGE_STACK_FRAME and PARAM_STACK_FRAME_GROWTH to zero under
        fconserve-stack. Reduce call-overhead used by inliner.
 
-Hariharan Sandanagobalane <hariharan@picochip.com>
+2009-01-30  Hariharan Sandanagobalane  <hariharan@picochip.com>
 
        PR/38157
        * common.opt (flag_conserve_stack): Initialised to zero.

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 9c21977d506d6570ae660ada2f59987a8e857943..0e5546a804b5b6999c9fdda750cf246c1781a28a 100644 (file)
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -3378,27 +3378,28 @@
   [(set_attr "op_type" "RI")
    (set_attr "z10prop" "z10_super_E1")])
 
+; Update the left-most 32 bit of a DI.
+(define_insn "*insv_h_di_reg_extimm"
+  [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
+                        (const_int 32)
+                        (const_int 0))
+       (match_operand:DI 1 "const_int_operand" "n"))]
+  "TARGET_EXTIMM"
+  "iihf\t%0,%o1"
+  [(set_attr "op_type" "RIL")
+   (set_attr "z10prop" "z10_fwd_E1")])
 
-(define_insn "*insv<mode>_reg_extimm"
+; Update the right-most 32 bit of a DI, or the whole of a SI.
+(define_insn "*insv_l<mode>_reg_extimm"
   [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
                        (const_int 32)
                        (match_operand 1 "const_int_operand" "n"))
        (match_operand:P 2 "const_int_operand" "n"))]
   "TARGET_EXTIMM
-   && INTVAL (operands[1]) >= 0
-   && INTVAL (operands[1]) < BITS_PER_WORD
-   && INTVAL (operands[1]) % 32 == 0"
-{
-  switch (BITS_PER_WORD - INTVAL (operands[1]))
-    {
-      case 64: return "iihf\t%0,%o2"; break;
-      case 32: return "iilf\t%0,%o2"; break;
-      default: gcc_unreachable();
-    }
-}
+   && BITS_PER_WORD - INTVAL (operands[1]) == 32"
+  "iilf\t%0,%o2"
   [(set_attr "op_type" "RIL")
-   (set_attr "z10prop" "z10_fwd_E1")])
-
+   (set_attr "z10prop" "z10_fwd_A1")])
 
 ;
 ; extendsidi2 instruction pattern(s).